mvsdio.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Marvell MMC/SD/SDIO driver
  4. *
  5. * Authors: Maen Suleiman, Nicolas Pitre
  6. * Copyright (C) 2008-2009 Marvell Ltd.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/mbus.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/scatterlist.h>
  17. #include <linux/irq.h>
  18. #include <linux/clk.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/mmc/host.h>
  21. #include <linux/mmc/slot-gpio.h>
  22. #include <linux/sizes.h>
  23. #include <asm/unaligned.h>
  24. #include "mvsdio.h"
  25. #define DRIVER_NAME "mvsdio"
  26. static int maxfreq;
  27. static int nodma;
  28. struct mvsd_host {
  29. void __iomem *base;
  30. struct mmc_request *mrq;
  31. spinlock_t lock;
  32. unsigned int xfer_mode;
  33. unsigned int intr_en;
  34. unsigned int ctrl;
  35. unsigned int pio_size;
  36. void *pio_ptr;
  37. unsigned int sg_frags;
  38. unsigned int ns_per_clk;
  39. unsigned int clock;
  40. unsigned int base_clock;
  41. struct timer_list timer;
  42. struct mmc_host *mmc;
  43. struct device *dev;
  44. struct clk *clk;
  45. };
  46. #define mvsd_write(offs, val) writel(val, iobase + (offs))
  47. #define mvsd_read(offs) readl(iobase + (offs))
  48. static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
  49. {
  50. void __iomem *iobase = host->base;
  51. unsigned int tmout;
  52. int tmout_index;
  53. /*
  54. * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
  55. * register is sometimes not set before a while when some
  56. * "unusual" data block sizes are used (such as with the SWITCH
  57. * command), even despite the fact that the XFER_DONE interrupt
  58. * was raised. And if another data transfer starts before
  59. * this bit comes to good sense (which eventually happens by
  60. * itself) then the new transfer simply fails with a timeout.
  61. */
  62. if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
  63. unsigned long t = jiffies + HZ;
  64. unsigned int hw_state, count = 0;
  65. do {
  66. hw_state = mvsd_read(MVSD_HW_STATE);
  67. if (time_after(jiffies, t)) {
  68. dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
  69. break;
  70. }
  71. count++;
  72. } while (!(hw_state & (1 << 13)));
  73. dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
  74. "(hw=0x%04x, count=%d, jiffies=%ld)\n",
  75. hw_state, count, jiffies - (t - HZ));
  76. }
  77. /* If timeout=0 then maximum timeout index is used. */
  78. tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
  79. tmout += data->timeout_clks;
  80. tmout_index = fls(tmout - 1) - 12;
  81. if (tmout_index < 0)
  82. tmout_index = 0;
  83. if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
  84. tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
  85. dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
  86. (data->flags & MMC_DATA_READ) ? "read" : "write",
  87. (u32)sg_virt(data->sg), data->blocks, data->blksz,
  88. tmout, tmout_index);
  89. host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
  90. host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
  91. mvsd_write(MVSD_HOST_CTRL, host->ctrl);
  92. mvsd_write(MVSD_BLK_COUNT, data->blocks);
  93. mvsd_write(MVSD_BLK_SIZE, data->blksz);
  94. if (nodma || (data->blksz | data->sg->offset) & 3 ||
  95. ((!(data->flags & MMC_DATA_READ) && data->sg->offset & 0x3f))) {
  96. /*
  97. * We cannot do DMA on a buffer which offset or size
  98. * is not aligned on a 4-byte boundary.
  99. *
  100. * It also appears the host to card DMA can corrupt
  101. * data when the buffer is not aligned on a 64 byte
  102. * boundary.
  103. */
  104. host->pio_size = data->blocks * data->blksz;
  105. host->pio_ptr = sg_virt(data->sg);
  106. if (!nodma)
  107. dev_dbg(host->dev, "fallback to PIO for data at 0x%p size %d\n",
  108. host->pio_ptr, host->pio_size);
  109. return 1;
  110. } else {
  111. dma_addr_t phys_addr;
  112. host->sg_frags = dma_map_sg(mmc_dev(host->mmc),
  113. data->sg, data->sg_len,
  114. mmc_get_dma_dir(data));
  115. phys_addr = sg_dma_address(data->sg);
  116. mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
  117. mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16);
  118. return 0;
  119. }
  120. }
  121. static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  122. {
  123. struct mvsd_host *host = mmc_priv(mmc);
  124. void __iomem *iobase = host->base;
  125. struct mmc_command *cmd = mrq->cmd;
  126. u32 cmdreg = 0, xfer = 0, intr = 0;
  127. unsigned long flags;
  128. unsigned int timeout;
  129. BUG_ON(host->mrq != NULL);
  130. host->mrq = mrq;
  131. dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
  132. cmd->opcode, mvsd_read(MVSD_HW_STATE));
  133. cmdreg = MVSD_CMD_INDEX(cmd->opcode);
  134. if (cmd->flags & MMC_RSP_BUSY)
  135. cmdreg |= MVSD_CMD_RSP_48BUSY;
  136. else if (cmd->flags & MMC_RSP_136)
  137. cmdreg |= MVSD_CMD_RSP_136;
  138. else if (cmd->flags & MMC_RSP_PRESENT)
  139. cmdreg |= MVSD_CMD_RSP_48;
  140. else
  141. cmdreg |= MVSD_CMD_RSP_NONE;
  142. if (cmd->flags & MMC_RSP_CRC)
  143. cmdreg |= MVSD_CMD_CHECK_CMDCRC;
  144. if (cmd->flags & MMC_RSP_OPCODE)
  145. cmdreg |= MVSD_CMD_INDX_CHECK;
  146. if (cmd->flags & MMC_RSP_PRESENT) {
  147. cmdreg |= MVSD_UNEXPECTED_RESP;
  148. intr |= MVSD_NOR_UNEXP_RSP;
  149. }
  150. if (mrq->data) {
  151. struct mmc_data *data = mrq->data;
  152. int pio;
  153. cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
  154. xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
  155. if (data->flags & MMC_DATA_READ)
  156. xfer |= MVSD_XFER_MODE_TO_HOST;
  157. pio = mvsd_setup_data(host, data);
  158. if (pio) {
  159. xfer |= MVSD_XFER_MODE_PIO;
  160. /* PIO section of mvsd_irq has comments on those bits */
  161. if (data->flags & MMC_DATA_WRITE)
  162. intr |= MVSD_NOR_TX_AVAIL;
  163. else if (host->pio_size > 32)
  164. intr |= MVSD_NOR_RX_FIFO_8W;
  165. else
  166. intr |= MVSD_NOR_RX_READY;
  167. }
  168. if (data->stop) {
  169. struct mmc_command *stop = data->stop;
  170. u32 cmd12reg = 0;
  171. mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
  172. mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16);
  173. if (stop->flags & MMC_RSP_BUSY)
  174. cmd12reg |= MVSD_AUTOCMD12_BUSY;
  175. if (stop->flags & MMC_RSP_OPCODE)
  176. cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
  177. cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
  178. mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
  179. xfer |= MVSD_XFER_MODE_AUTO_CMD12;
  180. intr |= MVSD_NOR_AUTOCMD12_DONE;
  181. } else {
  182. intr |= MVSD_NOR_XFER_DONE;
  183. }
  184. } else {
  185. intr |= MVSD_NOR_CMD_DONE;
  186. }
  187. mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
  188. mvsd_write(MVSD_ARG_HI, cmd->arg >> 16);
  189. spin_lock_irqsave(&host->lock, flags);
  190. host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
  191. host->xfer_mode |= xfer;
  192. mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
  193. mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
  194. mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
  195. mvsd_write(MVSD_CMD, cmdreg);
  196. host->intr_en &= MVSD_NOR_CARD_INT;
  197. host->intr_en |= intr | MVSD_NOR_ERROR;
  198. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  199. mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
  200. timeout = cmd->busy_timeout ? cmd->busy_timeout : 5000;
  201. mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout));
  202. spin_unlock_irqrestore(&host->lock, flags);
  203. }
  204. static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
  205. u32 err_status)
  206. {
  207. void __iomem *iobase = host->base;
  208. if (cmd->flags & MMC_RSP_136) {
  209. unsigned int response[8], i;
  210. for (i = 0; i < 8; i++)
  211. response[i] = mvsd_read(MVSD_RSP(i));
  212. cmd->resp[0] = ((response[0] & 0x03ff) << 22) |
  213. ((response[1] & 0xffff) << 6) |
  214. ((response[2] & 0xfc00) >> 10);
  215. cmd->resp[1] = ((response[2] & 0x03ff) << 22) |
  216. ((response[3] & 0xffff) << 6) |
  217. ((response[4] & 0xfc00) >> 10);
  218. cmd->resp[2] = ((response[4] & 0x03ff) << 22) |
  219. ((response[5] & 0xffff) << 6) |
  220. ((response[6] & 0xfc00) >> 10);
  221. cmd->resp[3] = ((response[6] & 0x03ff) << 22) |
  222. ((response[7] & 0x3fff) << 8);
  223. } else if (cmd->flags & MMC_RSP_PRESENT) {
  224. unsigned int response[3], i;
  225. for (i = 0; i < 3; i++)
  226. response[i] = mvsd_read(MVSD_RSP(i));
  227. cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
  228. ((response[1] & 0xffff) << (14 - 8)) |
  229. ((response[0] & 0x03ff) << (30 - 8));
  230. cmd->resp[1] = ((response[0] & 0xfc00) >> 10);
  231. cmd->resp[2] = 0;
  232. cmd->resp[3] = 0;
  233. }
  234. if (err_status & MVSD_ERR_CMD_TIMEOUT) {
  235. cmd->error = -ETIMEDOUT;
  236. } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
  237. MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
  238. cmd->error = -EILSEQ;
  239. }
  240. err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
  241. MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
  242. MVSD_ERR_CMD_STARTBIT);
  243. return err_status;
  244. }
  245. static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
  246. u32 err_status)
  247. {
  248. void __iomem *iobase = host->base;
  249. if (host->pio_ptr) {
  250. host->pio_ptr = NULL;
  251. host->pio_size = 0;
  252. } else {
  253. dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
  254. mmc_get_dma_dir(data));
  255. }
  256. if (err_status & MVSD_ERR_DATA_TIMEOUT)
  257. data->error = -ETIMEDOUT;
  258. else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
  259. data->error = -EILSEQ;
  260. else if (err_status & MVSD_ERR_XFER_SIZE)
  261. data->error = -EBADE;
  262. err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
  263. MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
  264. dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
  265. mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
  266. data->bytes_xfered =
  267. (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
  268. /* We can't be sure about the last block when errors are detected */
  269. if (data->bytes_xfered && data->error)
  270. data->bytes_xfered -= data->blksz;
  271. /* Handle Auto cmd 12 response */
  272. if (data->stop) {
  273. unsigned int response[3], i;
  274. for (i = 0; i < 3; i++)
  275. response[i] = mvsd_read(MVSD_AUTO_RSP(i));
  276. data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
  277. ((response[1] & 0xffff) << (14 - 8)) |
  278. ((response[0] & 0x03ff) << (30 - 8));
  279. data->stop->resp[1] = ((response[0] & 0xfc00) >> 10);
  280. data->stop->resp[2] = 0;
  281. data->stop->resp[3] = 0;
  282. if (err_status & MVSD_ERR_AUTOCMD12) {
  283. u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
  284. dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
  285. if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
  286. data->stop->error = -ENOEXEC;
  287. else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
  288. data->stop->error = -ETIMEDOUT;
  289. else if (err_cmd12)
  290. data->stop->error = -EILSEQ;
  291. err_status &= ~MVSD_ERR_AUTOCMD12;
  292. }
  293. }
  294. return err_status;
  295. }
  296. static irqreturn_t mvsd_irq(int irq, void *dev)
  297. {
  298. struct mvsd_host *host = dev;
  299. void __iomem *iobase = host->base;
  300. u32 intr_status, intr_done_mask;
  301. int irq_handled = 0;
  302. intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
  303. dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
  304. intr_status, mvsd_read(MVSD_NOR_INTR_EN),
  305. mvsd_read(MVSD_HW_STATE));
  306. /*
  307. * It looks like, SDIO IP can issue one late, spurious irq
  308. * although all irqs should be disabled. To work around this,
  309. * bail out early, if we didn't expect any irqs to occur.
  310. */
  311. if (!mvsd_read(MVSD_NOR_INTR_EN) && !mvsd_read(MVSD_ERR_INTR_EN)) {
  312. dev_dbg(host->dev, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n",
  313. mvsd_read(MVSD_NOR_INTR_STATUS),
  314. mvsd_read(MVSD_NOR_INTR_EN),
  315. mvsd_read(MVSD_ERR_INTR_STATUS),
  316. mvsd_read(MVSD_ERR_INTR_EN));
  317. return IRQ_HANDLED;
  318. }
  319. spin_lock(&host->lock);
  320. /* PIO handling, if needed. Messy business... */
  321. if (host->pio_size &&
  322. (intr_status & host->intr_en &
  323. (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
  324. u16 *p = host->pio_ptr;
  325. int s = host->pio_size;
  326. while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
  327. readsw(iobase + MVSD_FIFO, p, 16);
  328. p += 16;
  329. s -= 32;
  330. intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
  331. }
  332. /*
  333. * Normally we'd use < 32 here, but the RX_FIFO_8W bit
  334. * doesn't appear to assert when there is exactly 32 bytes
  335. * (8 words) left to fetch in a transfer.
  336. */
  337. if (s <= 32) {
  338. while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
  339. put_unaligned(mvsd_read(MVSD_FIFO), p++);
  340. put_unaligned(mvsd_read(MVSD_FIFO), p++);
  341. s -= 4;
  342. intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
  343. }
  344. if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
  345. u16 val[2] = {0, 0};
  346. val[0] = mvsd_read(MVSD_FIFO);
  347. val[1] = mvsd_read(MVSD_FIFO);
  348. memcpy(p, ((void *)&val) + 4 - s, s);
  349. s = 0;
  350. intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
  351. }
  352. if (s == 0) {
  353. host->intr_en &=
  354. ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
  355. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  356. } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
  357. host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
  358. host->intr_en |= MVSD_NOR_RX_READY;
  359. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  360. }
  361. }
  362. dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
  363. s, intr_status, mvsd_read(MVSD_HW_STATE));
  364. host->pio_ptr = p;
  365. host->pio_size = s;
  366. irq_handled = 1;
  367. } else if (host->pio_size &&
  368. (intr_status & host->intr_en &
  369. (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
  370. u16 *p = host->pio_ptr;
  371. int s = host->pio_size;
  372. /*
  373. * The TX_FIFO_8W bit is unreliable. When set, bursting
  374. * 16 halfwords all at once in the FIFO drops data. Actually
  375. * TX_AVAIL does go off after only one word is pushed even if
  376. * TX_FIFO_8W remains set.
  377. */
  378. while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
  379. mvsd_write(MVSD_FIFO, get_unaligned(p++));
  380. mvsd_write(MVSD_FIFO, get_unaligned(p++));
  381. s -= 4;
  382. intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
  383. }
  384. if (s < 4) {
  385. if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
  386. u16 val[2] = {0, 0};
  387. memcpy(((void *)&val) + 4 - s, p, s);
  388. mvsd_write(MVSD_FIFO, val[0]);
  389. mvsd_write(MVSD_FIFO, val[1]);
  390. s = 0;
  391. intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
  392. }
  393. if (s == 0) {
  394. host->intr_en &=
  395. ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
  396. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  397. }
  398. }
  399. dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
  400. s, intr_status, mvsd_read(MVSD_HW_STATE));
  401. host->pio_ptr = p;
  402. host->pio_size = s;
  403. irq_handled = 1;
  404. }
  405. mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
  406. intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
  407. MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
  408. if (intr_status & host->intr_en & ~intr_done_mask) {
  409. struct mmc_request *mrq = host->mrq;
  410. struct mmc_command *cmd = mrq->cmd;
  411. u32 err_status = 0;
  412. del_timer(&host->timer);
  413. host->mrq = NULL;
  414. host->intr_en &= MVSD_NOR_CARD_INT;
  415. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  416. mvsd_write(MVSD_ERR_INTR_EN, 0);
  417. spin_unlock(&host->lock);
  418. if (intr_status & MVSD_NOR_UNEXP_RSP) {
  419. cmd->error = -EPROTO;
  420. } else if (intr_status & MVSD_NOR_ERROR) {
  421. err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
  422. dev_dbg(host->dev, "err 0x%04x\n", err_status);
  423. }
  424. err_status = mvsd_finish_cmd(host, cmd, err_status);
  425. if (mrq->data)
  426. err_status = mvsd_finish_data(host, mrq->data, err_status);
  427. if (err_status) {
  428. dev_err(host->dev, "unhandled error status %#04x\n",
  429. err_status);
  430. cmd->error = -ENOMSG;
  431. }
  432. mmc_request_done(host->mmc, mrq);
  433. irq_handled = 1;
  434. } else
  435. spin_unlock(&host->lock);
  436. if (intr_status & MVSD_NOR_CARD_INT) {
  437. mmc_signal_sdio_irq(host->mmc);
  438. irq_handled = 1;
  439. }
  440. if (irq_handled)
  441. return IRQ_HANDLED;
  442. dev_err(host->dev, "unhandled interrupt status=0x%04x en=0x%04x pio=%d\n",
  443. intr_status, host->intr_en, host->pio_size);
  444. return IRQ_NONE;
  445. }
  446. static void mvsd_timeout_timer(struct timer_list *t)
  447. {
  448. struct mvsd_host *host = from_timer(host, t, timer);
  449. void __iomem *iobase = host->base;
  450. struct mmc_request *mrq;
  451. unsigned long flags;
  452. spin_lock_irqsave(&host->lock, flags);
  453. mrq = host->mrq;
  454. if (mrq) {
  455. dev_err(host->dev, "Timeout waiting for hardware interrupt.\n");
  456. dev_err(host->dev, "hw_state=0x%04x, intr_status=0x%04x intr_en=0x%04x\n",
  457. mvsd_read(MVSD_HW_STATE),
  458. mvsd_read(MVSD_NOR_INTR_STATUS),
  459. mvsd_read(MVSD_NOR_INTR_EN));
  460. host->mrq = NULL;
  461. mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
  462. host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
  463. mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
  464. host->intr_en &= MVSD_NOR_CARD_INT;
  465. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  466. mvsd_write(MVSD_ERR_INTR_EN, 0);
  467. mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
  468. mrq->cmd->error = -ETIMEDOUT;
  469. mvsd_finish_cmd(host, mrq->cmd, 0);
  470. if (mrq->data) {
  471. mrq->data->error = -ETIMEDOUT;
  472. mvsd_finish_data(host, mrq->data, 0);
  473. }
  474. }
  475. spin_unlock_irqrestore(&host->lock, flags);
  476. if (mrq)
  477. mmc_request_done(host->mmc, mrq);
  478. }
  479. static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
  480. {
  481. struct mvsd_host *host = mmc_priv(mmc);
  482. void __iomem *iobase = host->base;
  483. unsigned long flags;
  484. spin_lock_irqsave(&host->lock, flags);
  485. if (enable) {
  486. host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
  487. host->intr_en |= MVSD_NOR_CARD_INT;
  488. } else {
  489. host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
  490. host->intr_en &= ~MVSD_NOR_CARD_INT;
  491. }
  492. mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
  493. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  494. spin_unlock_irqrestore(&host->lock, flags);
  495. }
  496. static void mvsd_power_up(struct mvsd_host *host)
  497. {
  498. void __iomem *iobase = host->base;
  499. dev_dbg(host->dev, "power up\n");
  500. mvsd_write(MVSD_NOR_INTR_EN, 0);
  501. mvsd_write(MVSD_ERR_INTR_EN, 0);
  502. mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
  503. mvsd_write(MVSD_XFER_MODE, 0);
  504. mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
  505. mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
  506. mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
  507. mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
  508. }
  509. static void mvsd_power_down(struct mvsd_host *host)
  510. {
  511. void __iomem *iobase = host->base;
  512. dev_dbg(host->dev, "power down\n");
  513. mvsd_write(MVSD_NOR_INTR_EN, 0);
  514. mvsd_write(MVSD_ERR_INTR_EN, 0);
  515. mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
  516. mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
  517. mvsd_write(MVSD_NOR_STATUS_EN, 0);
  518. mvsd_write(MVSD_ERR_STATUS_EN, 0);
  519. mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
  520. mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
  521. }
  522. static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  523. {
  524. struct mvsd_host *host = mmc_priv(mmc);
  525. void __iomem *iobase = host->base;
  526. u32 ctrl_reg = 0;
  527. if (ios->power_mode == MMC_POWER_UP)
  528. mvsd_power_up(host);
  529. if (ios->clock == 0) {
  530. mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
  531. mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
  532. host->clock = 0;
  533. dev_dbg(host->dev, "clock off\n");
  534. } else if (ios->clock != host->clock) {
  535. u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
  536. if (m > MVSD_BASE_DIV_MAX)
  537. m = MVSD_BASE_DIV_MAX;
  538. mvsd_write(MVSD_CLK_DIV, m);
  539. host->clock = ios->clock;
  540. host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
  541. dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
  542. ios->clock, host->base_clock / (m+1), m);
  543. }
  544. /* default transfer mode */
  545. ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
  546. ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
  547. /* default to maximum timeout */
  548. ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
  549. ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
  550. if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
  551. ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
  552. if (ios->bus_width == MMC_BUS_WIDTH_4)
  553. ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
  554. /*
  555. * The HI_SPEED_EN bit is causing trouble with many (but not all)
  556. * high speed SD, SDHC and SDIO cards. Not enabling that bit
  557. * makes all cards work. So let's just ignore that bit for now
  558. * and revisit this issue if problems for not enabling this bit
  559. * are ever reported.
  560. */
  561. #if 0
  562. if (ios->timing == MMC_TIMING_MMC_HS ||
  563. ios->timing == MMC_TIMING_SD_HS)
  564. ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
  565. #endif
  566. host->ctrl = ctrl_reg;
  567. mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
  568. dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
  569. (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
  570. "push-pull" : "open-drain",
  571. (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
  572. "4bit-width" : "1bit-width",
  573. (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
  574. "high-speed" : "");
  575. if (ios->power_mode == MMC_POWER_OFF)
  576. mvsd_power_down(host);
  577. }
  578. static const struct mmc_host_ops mvsd_ops = {
  579. .request = mvsd_request,
  580. .get_ro = mmc_gpio_get_ro,
  581. .set_ios = mvsd_set_ios,
  582. .enable_sdio_irq = mvsd_enable_sdio_irq,
  583. };
  584. static void
  585. mv_conf_mbus_windows(struct mvsd_host *host,
  586. const struct mbus_dram_target_info *dram)
  587. {
  588. void __iomem *iobase = host->base;
  589. int i;
  590. for (i = 0; i < 4; i++) {
  591. writel(0, iobase + MVSD_WINDOW_CTRL(i));
  592. writel(0, iobase + MVSD_WINDOW_BASE(i));
  593. }
  594. for (i = 0; i < dram->num_cs; i++) {
  595. const struct mbus_dram_window *cs = dram->cs + i;
  596. writel(((cs->size - 1) & 0xffff0000) |
  597. (cs->mbus_attr << 8) |
  598. (dram->mbus_dram_target_id << 4) | 1,
  599. iobase + MVSD_WINDOW_CTRL(i));
  600. writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
  601. }
  602. }
  603. static int mvsd_probe(struct platform_device *pdev)
  604. {
  605. struct device_node *np = pdev->dev.of_node;
  606. struct mmc_host *mmc = NULL;
  607. struct mvsd_host *host = NULL;
  608. const struct mbus_dram_target_info *dram;
  609. int ret, irq;
  610. if (!np) {
  611. dev_err(&pdev->dev, "no DT node\n");
  612. return -ENODEV;
  613. }
  614. irq = platform_get_irq(pdev, 0);
  615. if (irq < 0)
  616. return -ENXIO;
  617. mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
  618. if (!mmc) {
  619. ret = -ENOMEM;
  620. goto out;
  621. }
  622. host = mmc_priv(mmc);
  623. host->mmc = mmc;
  624. host->dev = &pdev->dev;
  625. /*
  626. * Some non-DT platforms do not pass a clock, and the clock
  627. * frequency is passed through platform_data. On DT platforms,
  628. * a clock must always be passed, even if there is no gatable
  629. * clock associated to the SDIO interface (it can simply be a
  630. * fixed rate clock).
  631. */
  632. host->clk = devm_clk_get(&pdev->dev, NULL);
  633. if (IS_ERR(host->clk)) {
  634. dev_err(&pdev->dev, "no clock associated\n");
  635. ret = -EINVAL;
  636. goto out;
  637. }
  638. clk_prepare_enable(host->clk);
  639. mmc->ops = &mvsd_ops;
  640. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  641. mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
  642. mmc->f_max = MVSD_CLOCKRATE_MAX;
  643. mmc->max_blk_size = 2048;
  644. mmc->max_blk_count = 65535;
  645. mmc->max_segs = 1;
  646. mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
  647. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  648. host->base_clock = clk_get_rate(host->clk) / 2;
  649. ret = mmc_of_parse(mmc);
  650. if (ret < 0)
  651. goto out;
  652. if (maxfreq)
  653. mmc->f_max = maxfreq;
  654. spin_lock_init(&host->lock);
  655. host->base = devm_platform_ioremap_resource(pdev, 0);
  656. if (IS_ERR(host->base)) {
  657. ret = PTR_ERR(host->base);
  658. goto out;
  659. }
  660. /* (Re-)program MBUS remapping windows if we are asked to. */
  661. dram = mv_mbus_dram_info();
  662. if (dram)
  663. mv_conf_mbus_windows(host, dram);
  664. mvsd_power_down(host);
  665. ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host);
  666. if (ret) {
  667. dev_err(&pdev->dev, "cannot assign irq %d\n", irq);
  668. goto out;
  669. }
  670. timer_setup(&host->timer, mvsd_timeout_timer, 0);
  671. platform_set_drvdata(pdev, mmc);
  672. ret = mmc_add_host(mmc);
  673. if (ret)
  674. goto out;
  675. if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
  676. dev_dbg(&pdev->dev, "using GPIO for card detection\n");
  677. else
  678. dev_dbg(&pdev->dev, "lacking card detect (fall back to polling)\n");
  679. return 0;
  680. out:
  681. if (mmc) {
  682. if (!IS_ERR(host->clk))
  683. clk_disable_unprepare(host->clk);
  684. mmc_free_host(mmc);
  685. }
  686. return ret;
  687. }
  688. static int mvsd_remove(struct platform_device *pdev)
  689. {
  690. struct mmc_host *mmc = platform_get_drvdata(pdev);
  691. struct mvsd_host *host = mmc_priv(mmc);
  692. mmc_remove_host(mmc);
  693. del_timer_sync(&host->timer);
  694. mvsd_power_down(host);
  695. if (!IS_ERR(host->clk))
  696. clk_disable_unprepare(host->clk);
  697. mmc_free_host(mmc);
  698. return 0;
  699. }
  700. static const struct of_device_id mvsdio_dt_ids[] = {
  701. { .compatible = "marvell,orion-sdio" },
  702. { /* sentinel */ }
  703. };
  704. MODULE_DEVICE_TABLE(of, mvsdio_dt_ids);
  705. static struct platform_driver mvsd_driver = {
  706. .probe = mvsd_probe,
  707. .remove = mvsd_remove,
  708. .driver = {
  709. .name = DRIVER_NAME,
  710. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  711. .of_match_table = mvsdio_dt_ids,
  712. },
  713. };
  714. module_platform_driver(mvsd_driver);
  715. /* maximum card clock frequency (default 50MHz) */
  716. module_param(maxfreq, int, 0);
  717. /* force PIO transfers all the time */
  718. module_param(nodma, int, 0);
  719. MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
  720. MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
  721. MODULE_LICENSE("GPL");
  722. MODULE_ALIAS("platform:mvsdio");