mmci_stm32_sdmmc.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
  4. * Author: Ludovic.barre@st.com for STMicroelectronics.
  5. */
  6. #include <linux/bitfield.h>
  7. #include <linux/delay.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/iopoll.h>
  10. #include <linux/mmc/host.h>
  11. #include <linux/mmc/card.h>
  12. #include <linux/of_address.h>
  13. #include <linux/reset.h>
  14. #include <linux/scatterlist.h>
  15. #include "mmci.h"
  16. #define SDMMC_LLI_BUF_LEN PAGE_SIZE
  17. #define SDMMC_IDMA_BURST BIT(MMCI_STM32_IDMABNDT_SHIFT)
  18. #define DLYB_CR 0x0
  19. #define DLYB_CR_DEN BIT(0)
  20. #define DLYB_CR_SEN BIT(1)
  21. #define DLYB_CFGR 0x4
  22. #define DLYB_CFGR_SEL_MASK GENMASK(3, 0)
  23. #define DLYB_CFGR_UNIT_MASK GENMASK(14, 8)
  24. #define DLYB_CFGR_LNG_MASK GENMASK(27, 16)
  25. #define DLYB_CFGR_LNGF BIT(31)
  26. #define DLYB_NB_DELAY 11
  27. #define DLYB_CFGR_SEL_MAX (DLYB_NB_DELAY + 1)
  28. #define DLYB_CFGR_UNIT_MAX 127
  29. #define DLYB_LNG_TIMEOUT_US 1000
  30. #define SDMMC_VSWEND_TIMEOUT_US 10000
  31. struct sdmmc_lli_desc {
  32. u32 idmalar;
  33. u32 idmabase;
  34. u32 idmasize;
  35. };
  36. struct sdmmc_idma {
  37. dma_addr_t sg_dma;
  38. void *sg_cpu;
  39. };
  40. struct sdmmc_dlyb {
  41. void __iomem *base;
  42. u32 unit;
  43. u32 max;
  44. };
  45. static int sdmmc_idma_validate_data(struct mmci_host *host,
  46. struct mmc_data *data)
  47. {
  48. struct scatterlist *sg;
  49. int i;
  50. /*
  51. * idma has constraints on idmabase & idmasize for each element
  52. * excepted the last element which has no constraint on idmasize
  53. */
  54. for_each_sg(data->sg, sg, data->sg_len - 1, i) {
  55. if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
  56. !IS_ALIGNED(sg->length, SDMMC_IDMA_BURST)) {
  57. dev_err(mmc_dev(host->mmc),
  58. "unaligned scatterlist: ofst:%x length:%d\n",
  59. data->sg->offset, data->sg->length);
  60. return -EINVAL;
  61. }
  62. }
  63. if (!IS_ALIGNED(sg->offset, sizeof(u32))) {
  64. dev_err(mmc_dev(host->mmc),
  65. "unaligned last scatterlist: ofst:%x length:%d\n",
  66. data->sg->offset, data->sg->length);
  67. return -EINVAL;
  68. }
  69. return 0;
  70. }
  71. static int _sdmmc_idma_prep_data(struct mmci_host *host,
  72. struct mmc_data *data)
  73. {
  74. int n_elem;
  75. n_elem = dma_map_sg(mmc_dev(host->mmc),
  76. data->sg,
  77. data->sg_len,
  78. mmc_get_dma_dir(data));
  79. if (!n_elem) {
  80. dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
  81. return -EINVAL;
  82. }
  83. return 0;
  84. }
  85. static int sdmmc_idma_prep_data(struct mmci_host *host,
  86. struct mmc_data *data, bool next)
  87. {
  88. /* Check if job is already prepared. */
  89. if (!next && data->host_cookie == host->next_cookie)
  90. return 0;
  91. return _sdmmc_idma_prep_data(host, data);
  92. }
  93. static void sdmmc_idma_unprep_data(struct mmci_host *host,
  94. struct mmc_data *data, int err)
  95. {
  96. dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  97. mmc_get_dma_dir(data));
  98. }
  99. static int sdmmc_idma_setup(struct mmci_host *host)
  100. {
  101. struct sdmmc_idma *idma;
  102. struct device *dev = mmc_dev(host->mmc);
  103. idma = devm_kzalloc(dev, sizeof(*idma), GFP_KERNEL);
  104. if (!idma)
  105. return -ENOMEM;
  106. host->dma_priv = idma;
  107. if (host->variant->dma_lli) {
  108. idma->sg_cpu = dmam_alloc_coherent(dev, SDMMC_LLI_BUF_LEN,
  109. &idma->sg_dma, GFP_KERNEL);
  110. if (!idma->sg_cpu) {
  111. dev_err(dev, "Failed to alloc IDMA descriptor\n");
  112. return -ENOMEM;
  113. }
  114. host->mmc->max_segs = SDMMC_LLI_BUF_LEN /
  115. sizeof(struct sdmmc_lli_desc);
  116. host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask;
  117. } else {
  118. host->mmc->max_segs = 1;
  119. host->mmc->max_seg_size = host->mmc->max_req_size;
  120. }
  121. return dma_set_max_seg_size(dev, host->mmc->max_seg_size);
  122. }
  123. static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
  124. {
  125. struct sdmmc_idma *idma = host->dma_priv;
  126. struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu;
  127. struct mmc_data *data = host->data;
  128. struct scatterlist *sg;
  129. int i;
  130. if (!host->variant->dma_lli || data->sg_len == 1) {
  131. writel_relaxed(sg_dma_address(data->sg),
  132. host->base + MMCI_STM32_IDMABASE0R);
  133. writel_relaxed(MMCI_STM32_IDMAEN,
  134. host->base + MMCI_STM32_IDMACTRLR);
  135. return 0;
  136. }
  137. for_each_sg(data->sg, sg, data->sg_len, i) {
  138. desc[i].idmalar = (i + 1) * sizeof(struct sdmmc_lli_desc);
  139. desc[i].idmalar |= MMCI_STM32_ULA | MMCI_STM32_ULS
  140. | MMCI_STM32_ABR;
  141. desc[i].idmabase = sg_dma_address(sg);
  142. desc[i].idmasize = sg_dma_len(sg);
  143. }
  144. /* notice the end of link list */
  145. desc[data->sg_len - 1].idmalar &= ~MMCI_STM32_ULA;
  146. dma_wmb();
  147. writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
  148. writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
  149. writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
  150. writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
  151. writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN,
  152. host->base + MMCI_STM32_IDMACTRLR);
  153. return 0;
  154. }
  155. static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data)
  156. {
  157. writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
  158. if (!data->host_cookie)
  159. sdmmc_idma_unprep_data(host, data, 0);
  160. }
  161. static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
  162. {
  163. unsigned int clk = 0, ddr = 0;
  164. if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
  165. host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
  166. ddr = MCI_STM32_CLK_DDR;
  167. /*
  168. * cclk = mclk / (2 * clkdiv)
  169. * clkdiv 0 => bypass
  170. * in ddr mode bypass is not possible
  171. */
  172. if (desired) {
  173. if (desired >= host->mclk && !ddr) {
  174. host->cclk = host->mclk;
  175. } else {
  176. clk = DIV_ROUND_UP(host->mclk, 2 * desired);
  177. if (clk > MCI_STM32_CLK_CLKDIV_MSK)
  178. clk = MCI_STM32_CLK_CLKDIV_MSK;
  179. host->cclk = host->mclk / (2 * clk);
  180. }
  181. } else {
  182. /*
  183. * while power-on phase the clock can't be define to 0,
  184. * Only power-off and power-cyc deactivate the clock.
  185. * if desired clock is 0, set max divider
  186. */
  187. clk = MCI_STM32_CLK_CLKDIV_MSK;
  188. host->cclk = host->mclk / (2 * clk);
  189. }
  190. /* Set actual clock for debug */
  191. if (host->mmc->ios.power_mode == MMC_POWER_ON)
  192. host->mmc->actual_clock = host->cclk;
  193. else
  194. host->mmc->actual_clock = 0;
  195. if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
  196. clk |= MCI_STM32_CLK_WIDEBUS_4;
  197. if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
  198. clk |= MCI_STM32_CLK_WIDEBUS_8;
  199. clk |= MCI_STM32_CLK_HWFCEN;
  200. clk |= host->clk_reg_add;
  201. clk |= ddr;
  202. /*
  203. * SDMMC_FBCK is selected when an external Delay Block is needed
  204. * with SDR104.
  205. */
  206. if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
  207. clk |= MCI_STM32_CLK_BUSSPEED;
  208. if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) {
  209. clk &= ~MCI_STM32_CLK_SEL_MSK;
  210. clk |= MCI_STM32_CLK_SELFBCK;
  211. }
  212. }
  213. mmci_write_clkreg(host, clk);
  214. }
  215. static void sdmmc_dlyb_input_ck(struct sdmmc_dlyb *dlyb)
  216. {
  217. if (!dlyb || !dlyb->base)
  218. return;
  219. /* Output clock = Input clock */
  220. writel_relaxed(0, dlyb->base + DLYB_CR);
  221. }
  222. static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr)
  223. {
  224. struct mmc_ios ios = host->mmc->ios;
  225. struct sdmmc_dlyb *dlyb = host->variant_priv;
  226. /* adds OF options */
  227. pwr = host->pwr_reg_add;
  228. sdmmc_dlyb_input_ck(dlyb);
  229. if (ios.power_mode == MMC_POWER_OFF) {
  230. /* Only a reset could power-off sdmmc */
  231. reset_control_assert(host->rst);
  232. udelay(2);
  233. reset_control_deassert(host->rst);
  234. /*
  235. * Set the SDMMC in Power-cycle state.
  236. * This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK
  237. * are driven low, to prevent the Card from being supplied
  238. * through the signal lines.
  239. */
  240. mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr);
  241. } else if (ios.power_mode == MMC_POWER_ON) {
  242. /*
  243. * After power-off (reset): the irq mask defined in probe
  244. * functionis lost
  245. * ault irq mask (probe) must be activated
  246. */
  247. writel(MCI_IRQENABLE | host->variant->start_err,
  248. host->base + MMCIMASK0);
  249. /* preserves voltage switch bits */
  250. pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN |
  251. MCI_STM32_VSWITCH);
  252. /*
  253. * After a power-cycle state, we must set the SDMMC in
  254. * Power-off. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are
  255. * driven high. Then we can set the SDMMC to Power-on state
  256. */
  257. mmci_write_pwrreg(host, MCI_PWR_OFF | pwr);
  258. mdelay(1);
  259. mmci_write_pwrreg(host, MCI_PWR_ON | pwr);
  260. }
  261. }
  262. static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host)
  263. {
  264. u32 datactrl;
  265. datactrl = mmci_dctrl_blksz(host);
  266. if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
  267. host->data->blocks == 1)
  268. datactrl |= MCI_DPSM_STM32_MODE_SDIO;
  269. else if (host->data->stop && !host->mrq->sbc)
  270. datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP;
  271. else
  272. datactrl |= MCI_DPSM_STM32_MODE_BLOCK;
  273. return datactrl;
  274. }
  275. static bool sdmmc_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
  276. {
  277. void __iomem *base = host->base;
  278. u32 busy_d0, busy_d0end, mask, sdmmc_status;
  279. mask = readl_relaxed(base + MMCIMASK0);
  280. sdmmc_status = readl_relaxed(base + MMCISTATUS);
  281. busy_d0end = sdmmc_status & MCI_STM32_BUSYD0END;
  282. busy_d0 = sdmmc_status & MCI_STM32_BUSYD0;
  283. /* complete if there is an error or busy_d0end */
  284. if ((status & err_msk) || busy_d0end)
  285. goto complete;
  286. /*
  287. * On response the busy signaling is reflected in the BUSYD0 flag.
  288. * if busy_d0 is in-progress we must activate busyd0end interrupt
  289. * to wait this completion. Else this request has no busy step.
  290. */
  291. if (busy_d0) {
  292. if (!host->busy_status) {
  293. writel_relaxed(mask | host->variant->busy_detect_mask,
  294. base + MMCIMASK0);
  295. host->busy_status = status &
  296. (MCI_CMDSENT | MCI_CMDRESPEND);
  297. }
  298. return false;
  299. }
  300. complete:
  301. if (host->busy_status) {
  302. writel_relaxed(mask & ~host->variant->busy_detect_mask,
  303. base + MMCIMASK0);
  304. host->busy_status = 0;
  305. }
  306. writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR);
  307. return true;
  308. }
  309. static void sdmmc_dlyb_set_cfgr(struct sdmmc_dlyb *dlyb,
  310. int unit, int phase, bool sampler)
  311. {
  312. u32 cfgr;
  313. writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR);
  314. cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) |
  315. FIELD_PREP(DLYB_CFGR_SEL_MASK, phase);
  316. writel_relaxed(cfgr, dlyb->base + DLYB_CFGR);
  317. if (!sampler)
  318. writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
  319. }
  320. static int sdmmc_dlyb_lng_tuning(struct mmci_host *host)
  321. {
  322. struct sdmmc_dlyb *dlyb = host->variant_priv;
  323. u32 cfgr;
  324. int i, lng, ret;
  325. for (i = 0; i <= DLYB_CFGR_UNIT_MAX; i++) {
  326. sdmmc_dlyb_set_cfgr(dlyb, i, DLYB_CFGR_SEL_MAX, true);
  327. ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr,
  328. (cfgr & DLYB_CFGR_LNGF),
  329. 1, DLYB_LNG_TIMEOUT_US);
  330. if (ret) {
  331. dev_warn(mmc_dev(host->mmc),
  332. "delay line cfg timeout unit:%d cfgr:%d\n",
  333. i, cfgr);
  334. continue;
  335. }
  336. lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr);
  337. if (lng < BIT(DLYB_NB_DELAY) && lng > 0)
  338. break;
  339. }
  340. if (i > DLYB_CFGR_UNIT_MAX)
  341. return -EINVAL;
  342. dlyb->unit = i;
  343. dlyb->max = __fls(lng);
  344. return 0;
  345. }
  346. static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
  347. {
  348. struct sdmmc_dlyb *dlyb = host->variant_priv;
  349. int cur_len = 0, max_len = 0, end_of_len = 0;
  350. int phase;
  351. for (phase = 0; phase <= dlyb->max; phase++) {
  352. sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
  353. if (mmc_send_tuning(host->mmc, opcode, NULL)) {
  354. cur_len = 0;
  355. } else {
  356. cur_len++;
  357. if (cur_len > max_len) {
  358. max_len = cur_len;
  359. end_of_len = phase;
  360. }
  361. }
  362. }
  363. if (!max_len) {
  364. dev_err(mmc_dev(host->mmc), "no tuning point found\n");
  365. return -EINVAL;
  366. }
  367. writel_relaxed(0, dlyb->base + DLYB_CR);
  368. phase = end_of_len - max_len / 2;
  369. sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
  370. dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n",
  371. dlyb->unit, dlyb->max, phase);
  372. return 0;
  373. }
  374. static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
  375. {
  376. struct mmci_host *host = mmc_priv(mmc);
  377. struct sdmmc_dlyb *dlyb = host->variant_priv;
  378. if (!dlyb || !dlyb->base)
  379. return -EINVAL;
  380. if (sdmmc_dlyb_lng_tuning(host))
  381. return -EINVAL;
  382. return sdmmc_dlyb_phase_tuning(host, opcode);
  383. }
  384. static void sdmmc_pre_sig_volt_vswitch(struct mmci_host *host)
  385. {
  386. /* clear the voltage switch completion flag */
  387. writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR);
  388. /* enable Voltage switch procedure */
  389. mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN);
  390. }
  391. static int sdmmc_post_sig_volt_switch(struct mmci_host *host,
  392. struct mmc_ios *ios)
  393. {
  394. unsigned long flags;
  395. u32 status;
  396. int ret = 0;
  397. spin_lock_irqsave(&host->lock, flags);
  398. if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 &&
  399. host->pwr_reg & MCI_STM32_VSWITCHEN) {
  400. mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH);
  401. spin_unlock_irqrestore(&host->lock, flags);
  402. /* wait voltage switch completion while 10ms */
  403. ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS,
  404. status,
  405. (status & MCI_STM32_VSWEND),
  406. 10, SDMMC_VSWEND_TIMEOUT_US);
  407. writel_relaxed(MCI_STM32_VSWENDC | MCI_STM32_CKSTOPC,
  408. host->base + MMCICLEAR);
  409. spin_lock_irqsave(&host->lock, flags);
  410. mmci_write_pwrreg(host, host->pwr_reg &
  411. ~(MCI_STM32_VSWITCHEN | MCI_STM32_VSWITCH));
  412. }
  413. spin_unlock_irqrestore(&host->lock, flags);
  414. return ret;
  415. }
  416. static struct mmci_host_ops sdmmc_variant_ops = {
  417. .validate_data = sdmmc_idma_validate_data,
  418. .prep_data = sdmmc_idma_prep_data,
  419. .unprep_data = sdmmc_idma_unprep_data,
  420. .get_datactrl_cfg = sdmmc_get_dctrl_cfg,
  421. .dma_setup = sdmmc_idma_setup,
  422. .dma_start = sdmmc_idma_start,
  423. .dma_finalize = sdmmc_idma_finalize,
  424. .set_clkreg = mmci_sdmmc_set_clkreg,
  425. .set_pwrreg = mmci_sdmmc_set_pwrreg,
  426. .busy_complete = sdmmc_busy_complete,
  427. .pre_sig_volt_switch = sdmmc_pre_sig_volt_vswitch,
  428. .post_sig_volt_switch = sdmmc_post_sig_volt_switch,
  429. };
  430. void sdmmc_variant_init(struct mmci_host *host)
  431. {
  432. struct device_node *np = host->mmc->parent->of_node;
  433. void __iomem *base_dlyb;
  434. struct sdmmc_dlyb *dlyb;
  435. host->ops = &sdmmc_variant_ops;
  436. host->pwr_reg = readl_relaxed(host->base + MMCIPOWER);
  437. base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL);
  438. if (IS_ERR(base_dlyb))
  439. return;
  440. dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL);
  441. if (!dlyb)
  442. return;
  443. dlyb->base = base_dlyb;
  444. host->variant_priv = dlyb;
  445. host->mmc_ops->execute_tuning = sdmmc_execute_tuning;
  446. }