jz4740_mmc.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  4. * Copyright (C) 2013, Imagination Technologies
  5. *
  6. * JZ4740 SD/MMC controller driver
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/dmaengine.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/err.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/irq.h>
  17. #include <linux/mmc/host.h>
  18. #include <linux/mmc/slot-gpio.h>
  19. #include <linux/module.h>
  20. #include <linux/of_device.h>
  21. #include <linux/pinctrl/consumer.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/scatterlist.h>
  24. #include <asm/cacheflush.h>
  25. #define JZ_REG_MMC_STRPCL 0x00
  26. #define JZ_REG_MMC_STATUS 0x04
  27. #define JZ_REG_MMC_CLKRT 0x08
  28. #define JZ_REG_MMC_CMDAT 0x0C
  29. #define JZ_REG_MMC_RESTO 0x10
  30. #define JZ_REG_MMC_RDTO 0x14
  31. #define JZ_REG_MMC_BLKLEN 0x18
  32. #define JZ_REG_MMC_NOB 0x1C
  33. #define JZ_REG_MMC_SNOB 0x20
  34. #define JZ_REG_MMC_IMASK 0x24
  35. #define JZ_REG_MMC_IREG 0x28
  36. #define JZ_REG_MMC_CMD 0x2C
  37. #define JZ_REG_MMC_ARG 0x30
  38. #define JZ_REG_MMC_RESP_FIFO 0x34
  39. #define JZ_REG_MMC_RXFIFO 0x38
  40. #define JZ_REG_MMC_TXFIFO 0x3C
  41. #define JZ_REG_MMC_LPM 0x40
  42. #define JZ_REG_MMC_DMAC 0x44
  43. #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
  44. #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
  45. #define JZ_MMC_STRPCL_START_READWAIT BIT(5)
  46. #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
  47. #define JZ_MMC_STRPCL_RESET BIT(3)
  48. #define JZ_MMC_STRPCL_START_OP BIT(2)
  49. #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
  50. #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
  51. #define JZ_MMC_STRPCL_CLOCK_START BIT(1)
  52. #define JZ_MMC_STATUS_IS_RESETTING BIT(15)
  53. #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
  54. #define JZ_MMC_STATUS_PRG_DONE BIT(13)
  55. #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
  56. #define JZ_MMC_STATUS_END_CMD_RES BIT(11)
  57. #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
  58. #define JZ_MMC_STATUS_IS_READWAIT BIT(9)
  59. #define JZ_MMC_STATUS_CLK_EN BIT(8)
  60. #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
  61. #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
  62. #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
  63. #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
  64. #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
  65. #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
  66. #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
  67. #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
  68. #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
  69. #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
  70. #define JZ_MMC_CMDAT_IO_ABORT BIT(11)
  71. #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
  72. #define JZ_MMC_CMDAT_BUS_WIDTH_8BIT (BIT(10) | BIT(9))
  73. #define JZ_MMC_CMDAT_BUS_WIDTH_MASK (BIT(10) | BIT(9))
  74. #define JZ_MMC_CMDAT_DMA_EN BIT(8)
  75. #define JZ_MMC_CMDAT_INIT BIT(7)
  76. #define JZ_MMC_CMDAT_BUSY BIT(6)
  77. #define JZ_MMC_CMDAT_STREAM BIT(5)
  78. #define JZ_MMC_CMDAT_WRITE BIT(4)
  79. #define JZ_MMC_CMDAT_DATA_EN BIT(3)
  80. #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
  81. #define JZ_MMC_CMDAT_RSP_R1 1
  82. #define JZ_MMC_CMDAT_RSP_R2 2
  83. #define JZ_MMC_CMDAT_RSP_R3 3
  84. #define JZ_MMC_IRQ_SDIO BIT(7)
  85. #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
  86. #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
  87. #define JZ_MMC_IRQ_END_CMD_RES BIT(2)
  88. #define JZ_MMC_IRQ_PRG_DONE BIT(1)
  89. #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
  90. #define JZ_MMC_DMAC_DMA_SEL BIT(1)
  91. #define JZ_MMC_DMAC_DMA_EN BIT(0)
  92. #define JZ_MMC_LPM_DRV_RISING BIT(31)
  93. #define JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY BIT(31)
  94. #define JZ_MMC_LPM_DRV_RISING_1NS_DLY BIT(30)
  95. #define JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY BIT(29)
  96. #define JZ_MMC_LPM_LOW_POWER_MODE_EN BIT(0)
  97. #define JZ_MMC_CLK_RATE 24000000
  98. #define JZ_MMC_REQ_TIMEOUT_MS 5000
  99. enum jz4740_mmc_version {
  100. JZ_MMC_JZ4740,
  101. JZ_MMC_JZ4725B,
  102. JZ_MMC_JZ4760,
  103. JZ_MMC_JZ4780,
  104. JZ_MMC_X1000,
  105. };
  106. enum jz4740_mmc_state {
  107. JZ4740_MMC_STATE_READ_RESPONSE,
  108. JZ4740_MMC_STATE_TRANSFER_DATA,
  109. JZ4740_MMC_STATE_SEND_STOP,
  110. JZ4740_MMC_STATE_DONE,
  111. };
  112. /*
  113. * The MMC core allows to prepare a mmc_request while another mmc_request
  114. * is in-flight. This is used via the pre_req/post_req hooks.
  115. * This driver uses the pre_req/post_req hooks to map/unmap the mmc_request.
  116. * Following what other drivers do (sdhci, dw_mmc) we use the following cookie
  117. * flags to keep track of the mmc_request mapping state.
  118. *
  119. * COOKIE_UNMAPPED: the request is not mapped.
  120. * COOKIE_PREMAPPED: the request was mapped in pre_req,
  121. * and should be unmapped in post_req.
  122. * COOKIE_MAPPED: the request was mapped in the irq handler,
  123. * and should be unmapped before mmc_request_done is called..
  124. */
  125. enum jz4780_cookie {
  126. COOKIE_UNMAPPED = 0,
  127. COOKIE_PREMAPPED,
  128. COOKIE_MAPPED,
  129. };
  130. struct jz4740_mmc_host {
  131. struct mmc_host *mmc;
  132. struct platform_device *pdev;
  133. struct clk *clk;
  134. enum jz4740_mmc_version version;
  135. int irq;
  136. int card_detect_irq;
  137. void __iomem *base;
  138. struct resource *mem_res;
  139. struct mmc_request *req;
  140. struct mmc_command *cmd;
  141. unsigned long waiting;
  142. uint32_t cmdat;
  143. uint32_t irq_mask;
  144. spinlock_t lock;
  145. struct timer_list timeout_timer;
  146. struct sg_mapping_iter miter;
  147. enum jz4740_mmc_state state;
  148. /* DMA support */
  149. struct dma_chan *dma_rx;
  150. struct dma_chan *dma_tx;
  151. bool use_dma;
  152. /* The DMA trigger level is 8 words, that is to say, the DMA read
  153. * trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write
  154. * trigger is when data words in MSC_TXFIFO is < 8.
  155. */
  156. #define JZ4740_MMC_FIFO_HALF_SIZE 8
  157. };
  158. static void jz4740_mmc_write_irq_mask(struct jz4740_mmc_host *host,
  159. uint32_t val)
  160. {
  161. if (host->version >= JZ_MMC_JZ4725B)
  162. return writel(val, host->base + JZ_REG_MMC_IMASK);
  163. else
  164. return writew(val, host->base + JZ_REG_MMC_IMASK);
  165. }
  166. static void jz4740_mmc_write_irq_reg(struct jz4740_mmc_host *host,
  167. uint32_t val)
  168. {
  169. if (host->version >= JZ_MMC_JZ4780)
  170. writel(val, host->base + JZ_REG_MMC_IREG);
  171. else
  172. writew(val, host->base + JZ_REG_MMC_IREG);
  173. }
  174. static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host)
  175. {
  176. if (host->version >= JZ_MMC_JZ4780)
  177. return readl(host->base + JZ_REG_MMC_IREG);
  178. else
  179. return readw(host->base + JZ_REG_MMC_IREG);
  180. }
  181. /*----------------------------------------------------------------------------*/
  182. /* DMA infrastructure */
  183. static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host)
  184. {
  185. if (!host->use_dma)
  186. return;
  187. dma_release_channel(host->dma_tx);
  188. dma_release_channel(host->dma_rx);
  189. }
  190. static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host)
  191. {
  192. host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx");
  193. if (IS_ERR(host->dma_tx)) {
  194. dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n");
  195. return PTR_ERR(host->dma_tx);
  196. }
  197. host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx");
  198. if (IS_ERR(host->dma_rx)) {
  199. dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n");
  200. dma_release_channel(host->dma_tx);
  201. return PTR_ERR(host->dma_rx);
  202. }
  203. return 0;
  204. }
  205. static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host,
  206. struct mmc_data *data)
  207. {
  208. return (data->flags & MMC_DATA_READ) ? host->dma_rx : host->dma_tx;
  209. }
  210. static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host,
  211. struct mmc_data *data)
  212. {
  213. struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
  214. enum dma_data_direction dir = mmc_get_dma_dir(data);
  215. dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
  216. data->host_cookie = COOKIE_UNMAPPED;
  217. }
  218. /* Prepares DMA data for current or next transfer.
  219. * A request can be in-flight when this is called.
  220. */
  221. static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host,
  222. struct mmc_data *data,
  223. int cookie)
  224. {
  225. struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
  226. enum dma_data_direction dir = mmc_get_dma_dir(data);
  227. int sg_count;
  228. if (data->host_cookie == COOKIE_PREMAPPED)
  229. return data->sg_count;
  230. sg_count = dma_map_sg(chan->device->dev,
  231. data->sg,
  232. data->sg_len,
  233. dir);
  234. if (sg_count <= 0) {
  235. dev_err(mmc_dev(host->mmc),
  236. "Failed to map scatterlist for DMA operation\n");
  237. return -EINVAL;
  238. }
  239. data->sg_count = sg_count;
  240. data->host_cookie = cookie;
  241. return data->sg_count;
  242. }
  243. static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host,
  244. struct mmc_data *data)
  245. {
  246. struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
  247. struct dma_async_tx_descriptor *desc;
  248. struct dma_slave_config conf = {
  249. .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  250. .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  251. .src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
  252. .dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
  253. };
  254. int sg_count;
  255. if (data->flags & MMC_DATA_WRITE) {
  256. conf.direction = DMA_MEM_TO_DEV;
  257. conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO;
  258. } else {
  259. conf.direction = DMA_DEV_TO_MEM;
  260. conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO;
  261. }
  262. sg_count = jz4740_mmc_prepare_dma_data(host, data, COOKIE_MAPPED);
  263. if (sg_count < 0)
  264. return sg_count;
  265. dmaengine_slave_config(chan, &conf);
  266. desc = dmaengine_prep_slave_sg(chan, data->sg, sg_count,
  267. conf.direction,
  268. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  269. if (!desc) {
  270. dev_err(mmc_dev(host->mmc),
  271. "Failed to allocate DMA %s descriptor",
  272. conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX");
  273. goto dma_unmap;
  274. }
  275. dmaengine_submit(desc);
  276. dma_async_issue_pending(chan);
  277. return 0;
  278. dma_unmap:
  279. if (data->host_cookie == COOKIE_MAPPED)
  280. jz4740_mmc_dma_unmap(host, data);
  281. return -ENOMEM;
  282. }
  283. static void jz4740_mmc_pre_request(struct mmc_host *mmc,
  284. struct mmc_request *mrq)
  285. {
  286. struct jz4740_mmc_host *host = mmc_priv(mmc);
  287. struct mmc_data *data = mrq->data;
  288. if (!host->use_dma)
  289. return;
  290. data->host_cookie = COOKIE_UNMAPPED;
  291. if (jz4740_mmc_prepare_dma_data(host, data, COOKIE_PREMAPPED) < 0)
  292. data->host_cookie = COOKIE_UNMAPPED;
  293. }
  294. static void jz4740_mmc_post_request(struct mmc_host *mmc,
  295. struct mmc_request *mrq,
  296. int err)
  297. {
  298. struct jz4740_mmc_host *host = mmc_priv(mmc);
  299. struct mmc_data *data = mrq->data;
  300. if (data && data->host_cookie != COOKIE_UNMAPPED)
  301. jz4740_mmc_dma_unmap(host, data);
  302. if (err) {
  303. struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
  304. dmaengine_terminate_all(chan);
  305. }
  306. }
  307. /*----------------------------------------------------------------------------*/
  308. static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
  309. unsigned int irq, bool enabled)
  310. {
  311. unsigned long flags;
  312. spin_lock_irqsave(&host->lock, flags);
  313. if (enabled)
  314. host->irq_mask &= ~irq;
  315. else
  316. host->irq_mask |= irq;
  317. jz4740_mmc_write_irq_mask(host, host->irq_mask);
  318. spin_unlock_irqrestore(&host->lock, flags);
  319. }
  320. static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
  321. bool start_transfer)
  322. {
  323. uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
  324. if (start_transfer)
  325. val |= JZ_MMC_STRPCL_START_OP;
  326. writew(val, host->base + JZ_REG_MMC_STRPCL);
  327. }
  328. static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
  329. {
  330. uint32_t status;
  331. unsigned int timeout = 1000;
  332. writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
  333. do {
  334. status = readl(host->base + JZ_REG_MMC_STATUS);
  335. } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
  336. }
  337. static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
  338. {
  339. uint32_t status;
  340. unsigned int timeout = 1000;
  341. writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
  342. udelay(10);
  343. do {
  344. status = readl(host->base + JZ_REG_MMC_STATUS);
  345. } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
  346. }
  347. static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
  348. {
  349. struct mmc_request *req;
  350. struct mmc_data *data;
  351. req = host->req;
  352. data = req->data;
  353. host->req = NULL;
  354. if (data && data->host_cookie == COOKIE_MAPPED)
  355. jz4740_mmc_dma_unmap(host, data);
  356. mmc_request_done(host->mmc, req);
  357. }
  358. static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
  359. unsigned int irq)
  360. {
  361. unsigned int timeout = 0x800;
  362. uint32_t status;
  363. do {
  364. status = jz4740_mmc_read_irq_reg(host);
  365. } while (!(status & irq) && --timeout);
  366. if (timeout == 0) {
  367. set_bit(0, &host->waiting);
  368. mod_timer(&host->timeout_timer,
  369. jiffies + msecs_to_jiffies(JZ_MMC_REQ_TIMEOUT_MS));
  370. jz4740_mmc_set_irq_enabled(host, irq, true);
  371. return true;
  372. }
  373. return false;
  374. }
  375. static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
  376. struct mmc_data *data)
  377. {
  378. int status;
  379. status = readl(host->base + JZ_REG_MMC_STATUS);
  380. if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
  381. if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
  382. host->req->cmd->error = -ETIMEDOUT;
  383. data->error = -ETIMEDOUT;
  384. } else {
  385. host->req->cmd->error = -EIO;
  386. data->error = -EIO;
  387. }
  388. } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) {
  389. if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) {
  390. host->req->cmd->error = -ETIMEDOUT;
  391. data->error = -ETIMEDOUT;
  392. } else {
  393. host->req->cmd->error = -EIO;
  394. data->error = -EIO;
  395. }
  396. }
  397. }
  398. static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
  399. struct mmc_data *data)
  400. {
  401. struct sg_mapping_iter *miter = &host->miter;
  402. void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
  403. uint32_t *buf;
  404. bool timeout;
  405. size_t i, j;
  406. while (sg_miter_next(miter)) {
  407. buf = miter->addr;
  408. i = miter->length / 4;
  409. j = i / 8;
  410. i = i & 0x7;
  411. while (j) {
  412. timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
  413. if (unlikely(timeout))
  414. goto poll_timeout;
  415. writel(buf[0], fifo_addr);
  416. writel(buf[1], fifo_addr);
  417. writel(buf[2], fifo_addr);
  418. writel(buf[3], fifo_addr);
  419. writel(buf[4], fifo_addr);
  420. writel(buf[5], fifo_addr);
  421. writel(buf[6], fifo_addr);
  422. writel(buf[7], fifo_addr);
  423. buf += 8;
  424. --j;
  425. }
  426. if (unlikely(i)) {
  427. timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
  428. if (unlikely(timeout))
  429. goto poll_timeout;
  430. while (i) {
  431. writel(*buf, fifo_addr);
  432. ++buf;
  433. --i;
  434. }
  435. }
  436. data->bytes_xfered += miter->length;
  437. }
  438. sg_miter_stop(miter);
  439. return false;
  440. poll_timeout:
  441. miter->consumed = (void *)buf - miter->addr;
  442. data->bytes_xfered += miter->consumed;
  443. sg_miter_stop(miter);
  444. return true;
  445. }
  446. static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
  447. struct mmc_data *data)
  448. {
  449. struct sg_mapping_iter *miter = &host->miter;
  450. void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
  451. uint32_t *buf;
  452. uint32_t d;
  453. uint32_t status;
  454. size_t i, j;
  455. unsigned int timeout;
  456. while (sg_miter_next(miter)) {
  457. buf = miter->addr;
  458. i = miter->length;
  459. j = i / 32;
  460. i = i & 0x1f;
  461. while (j) {
  462. timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
  463. if (unlikely(timeout))
  464. goto poll_timeout;
  465. buf[0] = readl(fifo_addr);
  466. buf[1] = readl(fifo_addr);
  467. buf[2] = readl(fifo_addr);
  468. buf[3] = readl(fifo_addr);
  469. buf[4] = readl(fifo_addr);
  470. buf[5] = readl(fifo_addr);
  471. buf[6] = readl(fifo_addr);
  472. buf[7] = readl(fifo_addr);
  473. buf += 8;
  474. --j;
  475. }
  476. if (unlikely(i)) {
  477. timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
  478. if (unlikely(timeout))
  479. goto poll_timeout;
  480. while (i >= 4) {
  481. *buf++ = readl(fifo_addr);
  482. i -= 4;
  483. }
  484. if (unlikely(i > 0)) {
  485. d = readl(fifo_addr);
  486. memcpy(buf, &d, i);
  487. }
  488. }
  489. data->bytes_xfered += miter->length;
  490. /* This can go away once MIPS implements
  491. * flush_kernel_dcache_page */
  492. flush_dcache_page(miter->page);
  493. }
  494. sg_miter_stop(miter);
  495. /* For whatever reason there is sometime one word more in the fifo then
  496. * requested */
  497. timeout = 1000;
  498. status = readl(host->base + JZ_REG_MMC_STATUS);
  499. while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
  500. d = readl(fifo_addr);
  501. status = readl(host->base + JZ_REG_MMC_STATUS);
  502. }
  503. return false;
  504. poll_timeout:
  505. miter->consumed = (void *)buf - miter->addr;
  506. data->bytes_xfered += miter->consumed;
  507. sg_miter_stop(miter);
  508. return true;
  509. }
  510. static void jz4740_mmc_timeout(struct timer_list *t)
  511. {
  512. struct jz4740_mmc_host *host = from_timer(host, t, timeout_timer);
  513. if (!test_and_clear_bit(0, &host->waiting))
  514. return;
  515. jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
  516. host->req->cmd->error = -ETIMEDOUT;
  517. jz4740_mmc_request_done(host);
  518. }
  519. static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
  520. struct mmc_command *cmd)
  521. {
  522. int i;
  523. uint16_t tmp;
  524. void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
  525. if (cmd->flags & MMC_RSP_136) {
  526. tmp = readw(fifo_addr);
  527. for (i = 0; i < 4; ++i) {
  528. cmd->resp[i] = tmp << 24;
  529. tmp = readw(fifo_addr);
  530. cmd->resp[i] |= tmp << 8;
  531. tmp = readw(fifo_addr);
  532. cmd->resp[i] |= tmp >> 8;
  533. }
  534. } else {
  535. cmd->resp[0] = readw(fifo_addr) << 24;
  536. cmd->resp[0] |= readw(fifo_addr) << 8;
  537. cmd->resp[0] |= readw(fifo_addr) & 0xff;
  538. }
  539. }
  540. static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
  541. struct mmc_command *cmd)
  542. {
  543. uint32_t cmdat = host->cmdat;
  544. host->cmdat &= ~JZ_MMC_CMDAT_INIT;
  545. jz4740_mmc_clock_disable(host);
  546. host->cmd = cmd;
  547. if (cmd->flags & MMC_RSP_BUSY)
  548. cmdat |= JZ_MMC_CMDAT_BUSY;
  549. switch (mmc_resp_type(cmd)) {
  550. case MMC_RSP_R1B:
  551. case MMC_RSP_R1:
  552. cmdat |= JZ_MMC_CMDAT_RSP_R1;
  553. break;
  554. case MMC_RSP_R2:
  555. cmdat |= JZ_MMC_CMDAT_RSP_R2;
  556. break;
  557. case MMC_RSP_R3:
  558. cmdat |= JZ_MMC_CMDAT_RSP_R3;
  559. break;
  560. default:
  561. break;
  562. }
  563. if (cmd->data) {
  564. cmdat |= JZ_MMC_CMDAT_DATA_EN;
  565. if (cmd->data->flags & MMC_DATA_WRITE)
  566. cmdat |= JZ_MMC_CMDAT_WRITE;
  567. if (host->use_dma) {
  568. /*
  569. * The 4780's MMC controller has integrated DMA ability
  570. * in addition to being able to use the external DMA
  571. * controller. It moves DMA control bits to a separate
  572. * register. The DMA_SEL bit chooses the external
  573. * controller over the integrated one. Earlier SoCs
  574. * can only use the external controller, and have a
  575. * single DMA enable bit in CMDAT.
  576. */
  577. if (host->version >= JZ_MMC_JZ4780) {
  578. writel(JZ_MMC_DMAC_DMA_EN | JZ_MMC_DMAC_DMA_SEL,
  579. host->base + JZ_REG_MMC_DMAC);
  580. } else {
  581. cmdat |= JZ_MMC_CMDAT_DMA_EN;
  582. }
  583. } else if (host->version >= JZ_MMC_JZ4780) {
  584. writel(0, host->base + JZ_REG_MMC_DMAC);
  585. }
  586. writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
  587. writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
  588. }
  589. writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
  590. writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
  591. writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
  592. jz4740_mmc_clock_enable(host, 1);
  593. }
  594. static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
  595. {
  596. struct mmc_command *cmd = host->req->cmd;
  597. struct mmc_data *data = cmd->data;
  598. int direction;
  599. if (data->flags & MMC_DATA_READ)
  600. direction = SG_MITER_TO_SG;
  601. else
  602. direction = SG_MITER_FROM_SG;
  603. sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
  604. }
  605. static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
  606. {
  607. struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
  608. struct mmc_command *cmd = host->req->cmd;
  609. struct mmc_request *req = host->req;
  610. struct mmc_data *data = cmd->data;
  611. bool timeout = false;
  612. if (cmd->error)
  613. host->state = JZ4740_MMC_STATE_DONE;
  614. switch (host->state) {
  615. case JZ4740_MMC_STATE_READ_RESPONSE:
  616. if (cmd->flags & MMC_RSP_PRESENT)
  617. jz4740_mmc_read_response(host, cmd);
  618. if (!data)
  619. break;
  620. jz_mmc_prepare_data_transfer(host);
  621. fallthrough;
  622. case JZ4740_MMC_STATE_TRANSFER_DATA:
  623. if (host->use_dma) {
  624. /* Use DMA if enabled.
  625. * Data transfer direction is defined later by
  626. * relying on data flags in
  627. * jz4740_mmc_prepare_dma_data() and
  628. * jz4740_mmc_start_dma_transfer().
  629. */
  630. timeout = jz4740_mmc_start_dma_transfer(host, data);
  631. data->bytes_xfered = data->blocks * data->blksz;
  632. } else if (data->flags & MMC_DATA_READ)
  633. /* Use PIO if DMA is not enabled.
  634. * Data transfer direction was defined before
  635. * by relying on data flags in
  636. * jz_mmc_prepare_data_transfer().
  637. */
  638. timeout = jz4740_mmc_read_data(host, data);
  639. else
  640. timeout = jz4740_mmc_write_data(host, data);
  641. if (unlikely(timeout)) {
  642. host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
  643. break;
  644. }
  645. jz4740_mmc_transfer_check_state(host, data);
  646. timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
  647. if (unlikely(timeout)) {
  648. host->state = JZ4740_MMC_STATE_SEND_STOP;
  649. break;
  650. }
  651. jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
  652. fallthrough;
  653. case JZ4740_MMC_STATE_SEND_STOP:
  654. if (!req->stop)
  655. break;
  656. jz4740_mmc_send_command(host, req->stop);
  657. if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) {
  658. timeout = jz4740_mmc_poll_irq(host,
  659. JZ_MMC_IRQ_PRG_DONE);
  660. if (timeout) {
  661. host->state = JZ4740_MMC_STATE_DONE;
  662. break;
  663. }
  664. }
  665. case JZ4740_MMC_STATE_DONE:
  666. break;
  667. }
  668. if (!timeout)
  669. jz4740_mmc_request_done(host);
  670. return IRQ_HANDLED;
  671. }
  672. static irqreturn_t jz_mmc_irq(int irq, void *devid)
  673. {
  674. struct jz4740_mmc_host *host = devid;
  675. struct mmc_command *cmd = host->cmd;
  676. uint32_t irq_reg, status, tmp;
  677. status = readl(host->base + JZ_REG_MMC_STATUS);
  678. irq_reg = jz4740_mmc_read_irq_reg(host);
  679. tmp = irq_reg;
  680. irq_reg &= ~host->irq_mask;
  681. tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
  682. JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
  683. if (tmp != irq_reg)
  684. jz4740_mmc_write_irq_reg(host, tmp & ~irq_reg);
  685. if (irq_reg & JZ_MMC_IRQ_SDIO) {
  686. jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_SDIO);
  687. mmc_signal_sdio_irq(host->mmc);
  688. irq_reg &= ~JZ_MMC_IRQ_SDIO;
  689. }
  690. if (host->req && cmd && irq_reg) {
  691. if (test_and_clear_bit(0, &host->waiting)) {
  692. del_timer(&host->timeout_timer);
  693. if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
  694. cmd->error = -ETIMEDOUT;
  695. } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
  696. cmd->error = -EIO;
  697. } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
  698. JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
  699. if (cmd->data)
  700. cmd->data->error = -EIO;
  701. cmd->error = -EIO;
  702. }
  703. jz4740_mmc_set_irq_enabled(host, irq_reg, false);
  704. jz4740_mmc_write_irq_reg(host, irq_reg);
  705. return IRQ_WAKE_THREAD;
  706. }
  707. }
  708. return IRQ_HANDLED;
  709. }
  710. static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
  711. {
  712. int div = 0;
  713. int real_rate;
  714. jz4740_mmc_clock_disable(host);
  715. clk_set_rate(host->clk, host->mmc->f_max);
  716. real_rate = clk_get_rate(host->clk);
  717. while (real_rate > rate && div < 7) {
  718. ++div;
  719. real_rate >>= 1;
  720. }
  721. writew(div, host->base + JZ_REG_MMC_CLKRT);
  722. if (real_rate > 25000000) {
  723. if (host->version >= JZ_MMC_X1000) {
  724. writel(JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY |
  725. JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY |
  726. JZ_MMC_LPM_LOW_POWER_MODE_EN,
  727. host->base + JZ_REG_MMC_LPM);
  728. } else if (host->version >= JZ_MMC_JZ4760) {
  729. writel(JZ_MMC_LPM_DRV_RISING |
  730. JZ_MMC_LPM_LOW_POWER_MODE_EN,
  731. host->base + JZ_REG_MMC_LPM);
  732. } else if (host->version >= JZ_MMC_JZ4725B)
  733. writel(JZ_MMC_LPM_LOW_POWER_MODE_EN,
  734. host->base + JZ_REG_MMC_LPM);
  735. }
  736. return real_rate;
  737. }
  738. static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
  739. {
  740. struct jz4740_mmc_host *host = mmc_priv(mmc);
  741. host->req = req;
  742. jz4740_mmc_write_irq_reg(host, ~0);
  743. jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
  744. host->state = JZ4740_MMC_STATE_READ_RESPONSE;
  745. set_bit(0, &host->waiting);
  746. mod_timer(&host->timeout_timer,
  747. jiffies + msecs_to_jiffies(JZ_MMC_REQ_TIMEOUT_MS));
  748. jz4740_mmc_send_command(host, req->cmd);
  749. }
  750. static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  751. {
  752. struct jz4740_mmc_host *host = mmc_priv(mmc);
  753. if (ios->clock)
  754. jz4740_mmc_set_clock_rate(host, ios->clock);
  755. switch (ios->power_mode) {
  756. case MMC_POWER_UP:
  757. jz4740_mmc_reset(host);
  758. if (!IS_ERR(mmc->supply.vmmc))
  759. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
  760. host->cmdat |= JZ_MMC_CMDAT_INIT;
  761. clk_prepare_enable(host->clk);
  762. break;
  763. case MMC_POWER_ON:
  764. break;
  765. default:
  766. if (!IS_ERR(mmc->supply.vmmc))
  767. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  768. clk_disable_unprepare(host->clk);
  769. break;
  770. }
  771. switch (ios->bus_width) {
  772. case MMC_BUS_WIDTH_1:
  773. host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK;
  774. break;
  775. case MMC_BUS_WIDTH_4:
  776. host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK;
  777. host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
  778. break;
  779. case MMC_BUS_WIDTH_8:
  780. host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK;
  781. host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_8BIT;
  782. break;
  783. default:
  784. break;
  785. }
  786. }
  787. static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
  788. {
  789. struct jz4740_mmc_host *host = mmc_priv(mmc);
  790. jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
  791. }
  792. static const struct mmc_host_ops jz4740_mmc_ops = {
  793. .request = jz4740_mmc_request,
  794. .pre_req = jz4740_mmc_pre_request,
  795. .post_req = jz4740_mmc_post_request,
  796. .set_ios = jz4740_mmc_set_ios,
  797. .get_ro = mmc_gpio_get_ro,
  798. .get_cd = mmc_gpio_get_cd,
  799. .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
  800. };
  801. static const struct of_device_id jz4740_mmc_of_match[] = {
  802. { .compatible = "ingenic,jz4740-mmc", .data = (void *) JZ_MMC_JZ4740 },
  803. { .compatible = "ingenic,jz4725b-mmc", .data = (void *)JZ_MMC_JZ4725B },
  804. { .compatible = "ingenic,jz4760-mmc", .data = (void *) JZ_MMC_JZ4760 },
  805. { .compatible = "ingenic,jz4780-mmc", .data = (void *) JZ_MMC_JZ4780 },
  806. { .compatible = "ingenic,x1000-mmc", .data = (void *) JZ_MMC_X1000 },
  807. {},
  808. };
  809. MODULE_DEVICE_TABLE(of, jz4740_mmc_of_match);
  810. static int jz4740_mmc_probe(struct platform_device* pdev)
  811. {
  812. int ret;
  813. struct mmc_host *mmc;
  814. struct jz4740_mmc_host *host;
  815. const struct of_device_id *match;
  816. mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
  817. if (!mmc) {
  818. dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
  819. return -ENOMEM;
  820. }
  821. host = mmc_priv(mmc);
  822. match = of_match_device(jz4740_mmc_of_match, &pdev->dev);
  823. if (match) {
  824. host->version = (enum jz4740_mmc_version)match->data;
  825. } else {
  826. /* JZ4740 should be the only one using legacy probe */
  827. host->version = JZ_MMC_JZ4740;
  828. }
  829. ret = mmc_of_parse(mmc);
  830. if (ret) {
  831. dev_err_probe(&pdev->dev, ret, "could not parse device properties\n");
  832. goto err_free_host;
  833. }
  834. mmc_regulator_get_supply(mmc);
  835. host->irq = platform_get_irq(pdev, 0);
  836. if (host->irq < 0) {
  837. ret = host->irq;
  838. goto err_free_host;
  839. }
  840. host->clk = devm_clk_get(&pdev->dev, "mmc");
  841. if (IS_ERR(host->clk)) {
  842. ret = PTR_ERR(host->clk);
  843. dev_err(&pdev->dev, "Failed to get mmc clock\n");
  844. goto err_free_host;
  845. }
  846. host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  847. host->base = devm_ioremap_resource(&pdev->dev, host->mem_res);
  848. if (IS_ERR(host->base)) {
  849. ret = PTR_ERR(host->base);
  850. dev_err(&pdev->dev, "Failed to ioremap base memory\n");
  851. goto err_free_host;
  852. }
  853. mmc->ops = &jz4740_mmc_ops;
  854. if (!mmc->f_max)
  855. mmc->f_max = JZ_MMC_CLK_RATE;
  856. mmc->f_min = mmc->f_max / 128;
  857. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  858. /*
  859. * We use a fixed timeout of 5s, hence inform the core about it. A
  860. * future improvement should instead respect the cmd->busy_timeout.
  861. */
  862. mmc->max_busy_timeout = JZ_MMC_REQ_TIMEOUT_MS;
  863. mmc->max_blk_size = (1 << 10) - 1;
  864. mmc->max_blk_count = (1 << 15) - 1;
  865. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  866. mmc->max_segs = 128;
  867. mmc->max_seg_size = mmc->max_req_size;
  868. host->mmc = mmc;
  869. host->pdev = pdev;
  870. spin_lock_init(&host->lock);
  871. host->irq_mask = ~0;
  872. jz4740_mmc_reset(host);
  873. ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
  874. dev_name(&pdev->dev), host);
  875. if (ret) {
  876. dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
  877. goto err_free_host;
  878. }
  879. jz4740_mmc_clock_disable(host);
  880. timer_setup(&host->timeout_timer, jz4740_mmc_timeout, 0);
  881. ret = jz4740_mmc_acquire_dma_channels(host);
  882. if (ret == -EPROBE_DEFER)
  883. goto err_free_irq;
  884. host->use_dma = !ret;
  885. platform_set_drvdata(pdev, host);
  886. ret = mmc_add_host(mmc);
  887. if (ret) {
  888. dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
  889. goto err_release_dma;
  890. }
  891. dev_info(&pdev->dev, "Ingenic SD/MMC card driver registered\n");
  892. dev_info(&pdev->dev, "Using %s, %d-bit mode\n",
  893. host->use_dma ? "DMA" : "PIO",
  894. (mmc->caps & MMC_CAP_8_BIT_DATA) ? 8 :
  895. ((mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1));
  896. return 0;
  897. err_release_dma:
  898. if (host->use_dma)
  899. jz4740_mmc_release_dma_channels(host);
  900. err_free_irq:
  901. free_irq(host->irq, host);
  902. err_free_host:
  903. mmc_free_host(mmc);
  904. return ret;
  905. }
  906. static int jz4740_mmc_remove(struct platform_device *pdev)
  907. {
  908. struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
  909. del_timer_sync(&host->timeout_timer);
  910. jz4740_mmc_set_irq_enabled(host, 0xff, false);
  911. jz4740_mmc_reset(host);
  912. mmc_remove_host(host->mmc);
  913. free_irq(host->irq, host);
  914. if (host->use_dma)
  915. jz4740_mmc_release_dma_channels(host);
  916. mmc_free_host(host->mmc);
  917. return 0;
  918. }
  919. static int __maybe_unused jz4740_mmc_suspend(struct device *dev)
  920. {
  921. return pinctrl_pm_select_sleep_state(dev);
  922. }
  923. static int __maybe_unused jz4740_mmc_resume(struct device *dev)
  924. {
  925. return pinctrl_select_default_state(dev);
  926. }
  927. static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
  928. jz4740_mmc_resume);
  929. static struct platform_driver jz4740_mmc_driver = {
  930. .probe = jz4740_mmc_probe,
  931. .remove = jz4740_mmc_remove,
  932. .driver = {
  933. .name = "jz4740-mmc",
  934. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  935. .of_match_table = of_match_ptr(jz4740_mmc_of_match),
  936. .pm = pm_ptr(&jz4740_mmc_pm_ops),
  937. },
  938. };
  939. module_platform_driver(jz4740_mmc_driver);
  940. MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
  941. MODULE_LICENSE("GPL");
  942. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");