dw_mmc.c 89 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Synopsys DesignWare Multimedia Card Interface driver
  4. * (Based on NXP driver for lpc 31xx)
  5. *
  6. * Copyright (C) 2009 NXP Semiconductors
  7. * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
  8. */
  9. #include <linux/blkdev.h>
  10. #include <linux/clk.h>
  11. #include <linux/debugfs.h>
  12. #include <linux/device.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/err.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/iopoll.h>
  18. #include <linux/ioport.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/slab.h>
  24. #include <linux/stat.h>
  25. #include <linux/delay.h>
  26. #include <linux/irq.h>
  27. #include <linux/mmc/card.h>
  28. #include <linux/mmc/host.h>
  29. #include <linux/mmc/mmc.h>
  30. #include <linux/mmc/sd.h>
  31. #include <linux/mmc/sdio.h>
  32. #include <linux/bitops.h>
  33. #include <linux/regulator/consumer.h>
  34. #include <linux/of.h>
  35. #include <linux/of_gpio.h>
  36. #include <linux/mmc/slot-gpio.h>
  37. #include "dw_mmc.h"
  38. /* Common flag combinations */
  39. #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  40. SDMMC_INT_HTO | SDMMC_INT_SBE | \
  41. SDMMC_INT_EBE | SDMMC_INT_HLE)
  42. #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  43. SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  44. #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
  45. DW_MCI_CMD_ERROR_FLAGS)
  46. #define DW_MCI_SEND_STATUS 1
  47. #define DW_MCI_RECV_STATUS 2
  48. #define DW_MCI_DMA_THRESHOLD 16
  49. #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
  50. #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
  51. #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  52. SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  53. SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  54. SDMMC_IDMAC_INT_TI)
  55. #define DESC_RING_BUF_SZ PAGE_SIZE
  56. struct idmac_desc_64addr {
  57. u32 des0; /* Control Descriptor */
  58. #define IDMAC_OWN_CLR64(x) \
  59. !((x) & cpu_to_le32(IDMAC_DES0_OWN))
  60. u32 des1; /* Reserved */
  61. u32 des2; /*Buffer sizes */
  62. #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  63. ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  64. ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  65. u32 des3; /* Reserved */
  66. u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
  67. u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
  68. u32 des6; /* Lower 32-bits of Next Descriptor Address */
  69. u32 des7; /* Upper 32-bits of Next Descriptor Address */
  70. };
  71. struct idmac_desc {
  72. __le32 des0; /* Control Descriptor */
  73. #define IDMAC_DES0_DIC BIT(1)
  74. #define IDMAC_DES0_LD BIT(2)
  75. #define IDMAC_DES0_FD BIT(3)
  76. #define IDMAC_DES0_CH BIT(4)
  77. #define IDMAC_DES0_ER BIT(5)
  78. #define IDMAC_DES0_CES BIT(30)
  79. #define IDMAC_DES0_OWN BIT(31)
  80. __le32 des1; /* Buffer sizes */
  81. #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  82. ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
  83. __le32 des2; /* buffer 1 physical address */
  84. __le32 des3; /* buffer 2 physical address */
  85. };
  86. /* Each descriptor can transfer up to 4KB of data in chained mode */
  87. #define DW_MCI_DESC_DATA_LENGTH 0x1000
  88. #if defined(CONFIG_DEBUG_FS)
  89. static int dw_mci_req_show(struct seq_file *s, void *v)
  90. {
  91. struct dw_mci_slot *slot = s->private;
  92. struct mmc_request *mrq;
  93. struct mmc_command *cmd;
  94. struct mmc_command *stop;
  95. struct mmc_data *data;
  96. /* Make sure we get a consistent snapshot */
  97. spin_lock_bh(&slot->host->lock);
  98. mrq = slot->mrq;
  99. if (mrq) {
  100. cmd = mrq->cmd;
  101. data = mrq->data;
  102. stop = mrq->stop;
  103. if (cmd)
  104. seq_printf(s,
  105. "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
  106. cmd->opcode, cmd->arg, cmd->flags,
  107. cmd->resp[0], cmd->resp[1], cmd->resp[2],
  108. cmd->resp[2], cmd->error);
  109. if (data)
  110. seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
  111. data->bytes_xfered, data->blocks,
  112. data->blksz, data->flags, data->error);
  113. if (stop)
  114. seq_printf(s,
  115. "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
  116. stop->opcode, stop->arg, stop->flags,
  117. stop->resp[0], stop->resp[1], stop->resp[2],
  118. stop->resp[2], stop->error);
  119. }
  120. spin_unlock_bh(&slot->host->lock);
  121. return 0;
  122. }
  123. DEFINE_SHOW_ATTRIBUTE(dw_mci_req);
  124. static int dw_mci_regs_show(struct seq_file *s, void *v)
  125. {
  126. struct dw_mci *host = s->private;
  127. pm_runtime_get_sync(host->dev);
  128. seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
  129. seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
  130. seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
  131. seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
  132. seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
  133. seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
  134. pm_runtime_put_autosuspend(host->dev);
  135. return 0;
  136. }
  137. DEFINE_SHOW_ATTRIBUTE(dw_mci_regs);
  138. static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
  139. {
  140. struct mmc_host *mmc = slot->mmc;
  141. struct dw_mci *host = slot->host;
  142. struct dentry *root;
  143. root = mmc->debugfs_root;
  144. if (!root)
  145. return;
  146. debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops);
  147. debugfs_create_file("req", S_IRUSR, root, slot, &dw_mci_req_fops);
  148. debugfs_create_u32("state", S_IRUSR, root, &host->state);
  149. debugfs_create_xul("pending_events", S_IRUSR, root,
  150. &host->pending_events);
  151. debugfs_create_xul("completed_events", S_IRUSR, root,
  152. &host->completed_events);
  153. }
  154. #endif /* defined(CONFIG_DEBUG_FS) */
  155. static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
  156. {
  157. u32 ctrl;
  158. ctrl = mci_readl(host, CTRL);
  159. ctrl |= reset;
  160. mci_writel(host, CTRL, ctrl);
  161. /* wait till resets clear */
  162. if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
  163. !(ctrl & reset),
  164. 1, 500 * USEC_PER_MSEC)) {
  165. dev_err(host->dev,
  166. "Timeout resetting block (ctrl reset %#x)\n",
  167. ctrl & reset);
  168. return false;
  169. }
  170. return true;
  171. }
  172. static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
  173. {
  174. u32 status;
  175. /*
  176. * Databook says that before issuing a new data transfer command
  177. * we need to check to see if the card is busy. Data transfer commands
  178. * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
  179. *
  180. * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
  181. * expected.
  182. */
  183. if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
  184. !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
  185. if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
  186. status,
  187. !(status & SDMMC_STATUS_BUSY),
  188. 10, 500 * USEC_PER_MSEC))
  189. dev_err(host->dev, "Busy; trying anyway\n");
  190. }
  191. }
  192. static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
  193. {
  194. struct dw_mci *host = slot->host;
  195. unsigned int cmd_status = 0;
  196. mci_writel(host, CMDARG, arg);
  197. wmb(); /* drain writebuffer */
  198. dw_mci_wait_while_busy(host, cmd);
  199. mci_writel(host, CMD, SDMMC_CMD_START | cmd);
  200. if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
  201. !(cmd_status & SDMMC_CMD_START),
  202. 1, 500 * USEC_PER_MSEC))
  203. dev_err(&slot->mmc->class_dev,
  204. "Timeout sending command (cmd %#x arg %#x status %#x)\n",
  205. cmd, arg, cmd_status);
  206. }
  207. static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
  208. {
  209. struct dw_mci_slot *slot = mmc_priv(mmc);
  210. struct dw_mci *host = slot->host;
  211. u32 cmdr;
  212. cmd->error = -EINPROGRESS;
  213. cmdr = cmd->opcode;
  214. if (cmd->opcode == MMC_STOP_TRANSMISSION ||
  215. cmd->opcode == MMC_GO_IDLE_STATE ||
  216. cmd->opcode == MMC_GO_INACTIVE_STATE ||
  217. (cmd->opcode == SD_IO_RW_DIRECT &&
  218. ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
  219. cmdr |= SDMMC_CMD_STOP;
  220. else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
  221. cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
  222. if (cmd->opcode == SD_SWITCH_VOLTAGE) {
  223. u32 clk_en_a;
  224. /* Special bit makes CMD11 not die */
  225. cmdr |= SDMMC_CMD_VOLT_SWITCH;
  226. /* Change state to continue to handle CMD11 weirdness */
  227. WARN_ON(slot->host->state != STATE_SENDING_CMD);
  228. slot->host->state = STATE_SENDING_CMD11;
  229. /*
  230. * We need to disable low power mode (automatic clock stop)
  231. * while doing voltage switch so we don't confuse the card,
  232. * since stopping the clock is a specific part of the UHS
  233. * voltage change dance.
  234. *
  235. * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
  236. * unconditionally turned back on in dw_mci_setup_bus() if it's
  237. * ever called with a non-zero clock. That shouldn't happen
  238. * until the voltage change is all done.
  239. */
  240. clk_en_a = mci_readl(host, CLKENA);
  241. clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
  242. mci_writel(host, CLKENA, clk_en_a);
  243. mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
  244. SDMMC_CMD_PRV_DAT_WAIT, 0);
  245. }
  246. if (cmd->flags & MMC_RSP_PRESENT) {
  247. /* We expect a response, so set this bit */
  248. cmdr |= SDMMC_CMD_RESP_EXP;
  249. if (cmd->flags & MMC_RSP_136)
  250. cmdr |= SDMMC_CMD_RESP_LONG;
  251. }
  252. if (cmd->flags & MMC_RSP_CRC)
  253. cmdr |= SDMMC_CMD_RESP_CRC;
  254. if (cmd->data) {
  255. cmdr |= SDMMC_CMD_DAT_EXP;
  256. if (cmd->data->flags & MMC_DATA_WRITE)
  257. cmdr |= SDMMC_CMD_DAT_WR;
  258. }
  259. if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
  260. cmdr |= SDMMC_CMD_USE_HOLD_REG;
  261. return cmdr;
  262. }
  263. static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
  264. {
  265. struct mmc_command *stop;
  266. u32 cmdr;
  267. if (!cmd->data)
  268. return 0;
  269. stop = &host->stop_abort;
  270. cmdr = cmd->opcode;
  271. memset(stop, 0, sizeof(struct mmc_command));
  272. if (cmdr == MMC_READ_SINGLE_BLOCK ||
  273. cmdr == MMC_READ_MULTIPLE_BLOCK ||
  274. cmdr == MMC_WRITE_BLOCK ||
  275. cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
  276. cmdr == MMC_SEND_TUNING_BLOCK ||
  277. cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
  278. stop->opcode = MMC_STOP_TRANSMISSION;
  279. stop->arg = 0;
  280. stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
  281. } else if (cmdr == SD_IO_RW_EXTENDED) {
  282. stop->opcode = SD_IO_RW_DIRECT;
  283. stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
  284. ((cmd->arg >> 28) & 0x7);
  285. stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
  286. } else {
  287. return 0;
  288. }
  289. cmdr = stop->opcode | SDMMC_CMD_STOP |
  290. SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
  291. if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
  292. cmdr |= SDMMC_CMD_USE_HOLD_REG;
  293. return cmdr;
  294. }
  295. static inline void dw_mci_set_cto(struct dw_mci *host)
  296. {
  297. unsigned int cto_clks;
  298. unsigned int cto_div;
  299. unsigned int cto_ms;
  300. unsigned long irqflags;
  301. cto_clks = mci_readl(host, TMOUT) & 0xff;
  302. cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
  303. if (cto_div == 0)
  304. cto_div = 1;
  305. cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
  306. host->bus_hz);
  307. /* add a bit spare time */
  308. cto_ms += 10;
  309. /*
  310. * The durations we're working with are fairly short so we have to be
  311. * extra careful about synchronization here. Specifically in hardware a
  312. * command timeout is _at most_ 5.1 ms, so that means we expect an
  313. * interrupt (either command done or timeout) to come rather quickly
  314. * after the mci_writel. ...but just in case we have a long interrupt
  315. * latency let's add a bit of paranoia.
  316. *
  317. * In general we'll assume that at least an interrupt will be asserted
  318. * in hardware by the time the cto_timer runs. ...and if it hasn't
  319. * been asserted in hardware by that time then we'll assume it'll never
  320. * come.
  321. */
  322. spin_lock_irqsave(&host->irq_lock, irqflags);
  323. if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
  324. mod_timer(&host->cto_timer,
  325. jiffies + msecs_to_jiffies(cto_ms) + 1);
  326. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  327. }
  328. static void dw_mci_start_command(struct dw_mci *host,
  329. struct mmc_command *cmd, u32 cmd_flags)
  330. {
  331. host->cmd = cmd;
  332. dev_vdbg(host->dev,
  333. "start command: ARGR=0x%08x CMDR=0x%08x\n",
  334. cmd->arg, cmd_flags);
  335. mci_writel(host, CMDARG, cmd->arg);
  336. wmb(); /* drain writebuffer */
  337. dw_mci_wait_while_busy(host, cmd_flags);
  338. mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
  339. /* response expected command only */
  340. if (cmd_flags & SDMMC_CMD_RESP_EXP)
  341. dw_mci_set_cto(host);
  342. }
  343. static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
  344. {
  345. struct mmc_command *stop = &host->stop_abort;
  346. dw_mci_start_command(host, stop, host->stop_cmdr);
  347. }
  348. /* DMA interface functions */
  349. static void dw_mci_stop_dma(struct dw_mci *host)
  350. {
  351. if (host->using_dma) {
  352. host->dma_ops->stop(host);
  353. host->dma_ops->cleanup(host);
  354. }
  355. /* Data transfer was stopped by the interrupt handler */
  356. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  357. }
  358. static void dw_mci_dma_cleanup(struct dw_mci *host)
  359. {
  360. struct mmc_data *data = host->data;
  361. if (data && data->host_cookie == COOKIE_MAPPED) {
  362. dma_unmap_sg(host->dev,
  363. data->sg,
  364. data->sg_len,
  365. mmc_get_dma_dir(data));
  366. data->host_cookie = COOKIE_UNMAPPED;
  367. }
  368. }
  369. static void dw_mci_idmac_reset(struct dw_mci *host)
  370. {
  371. u32 bmod = mci_readl(host, BMOD);
  372. /* Software reset of DMA */
  373. bmod |= SDMMC_IDMAC_SWRESET;
  374. mci_writel(host, BMOD, bmod);
  375. }
  376. static void dw_mci_idmac_stop_dma(struct dw_mci *host)
  377. {
  378. u32 temp;
  379. /* Disable and reset the IDMAC interface */
  380. temp = mci_readl(host, CTRL);
  381. temp &= ~SDMMC_CTRL_USE_IDMAC;
  382. temp |= SDMMC_CTRL_DMA_RESET;
  383. mci_writel(host, CTRL, temp);
  384. /* Stop the IDMAC running */
  385. temp = mci_readl(host, BMOD);
  386. temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
  387. temp |= SDMMC_IDMAC_SWRESET;
  388. mci_writel(host, BMOD, temp);
  389. }
  390. static void dw_mci_dmac_complete_dma(void *arg)
  391. {
  392. struct dw_mci *host = arg;
  393. struct mmc_data *data = host->data;
  394. dev_vdbg(host->dev, "DMA complete\n");
  395. if ((host->use_dma == TRANS_MODE_EDMAC) &&
  396. data && (data->flags & MMC_DATA_READ))
  397. /* Invalidate cache after read */
  398. dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
  399. data->sg,
  400. data->sg_len,
  401. DMA_FROM_DEVICE);
  402. host->dma_ops->cleanup(host);
  403. /*
  404. * If the card was removed, data will be NULL. No point in trying to
  405. * send the stop command or waiting for NBUSY in this case.
  406. */
  407. if (data) {
  408. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  409. tasklet_schedule(&host->tasklet);
  410. }
  411. }
  412. static int dw_mci_idmac_init(struct dw_mci *host)
  413. {
  414. int i;
  415. if (host->dma_64bit_address == 1) {
  416. struct idmac_desc_64addr *p;
  417. /* Number of descriptors in the ring buffer */
  418. host->ring_size =
  419. DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
  420. /* Forward link the descriptor list */
  421. for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
  422. i++, p++) {
  423. p->des6 = (host->sg_dma +
  424. (sizeof(struct idmac_desc_64addr) *
  425. (i + 1))) & 0xffffffff;
  426. p->des7 = (u64)(host->sg_dma +
  427. (sizeof(struct idmac_desc_64addr) *
  428. (i + 1))) >> 32;
  429. /* Initialize reserved and buffer size fields to "0" */
  430. p->des0 = 0;
  431. p->des1 = 0;
  432. p->des2 = 0;
  433. p->des3 = 0;
  434. }
  435. /* Set the last descriptor as the end-of-ring descriptor */
  436. p->des6 = host->sg_dma & 0xffffffff;
  437. p->des7 = (u64)host->sg_dma >> 32;
  438. p->des0 = IDMAC_DES0_ER;
  439. } else {
  440. struct idmac_desc *p;
  441. /* Number of descriptors in the ring buffer */
  442. host->ring_size =
  443. DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
  444. /* Forward link the descriptor list */
  445. for (i = 0, p = host->sg_cpu;
  446. i < host->ring_size - 1;
  447. i++, p++) {
  448. p->des3 = cpu_to_le32(host->sg_dma +
  449. (sizeof(struct idmac_desc) * (i + 1)));
  450. p->des0 = 0;
  451. p->des1 = 0;
  452. }
  453. /* Set the last descriptor as the end-of-ring descriptor */
  454. p->des3 = cpu_to_le32(host->sg_dma);
  455. p->des0 = cpu_to_le32(IDMAC_DES0_ER);
  456. }
  457. dw_mci_idmac_reset(host);
  458. if (host->dma_64bit_address == 1) {
  459. /* Mask out interrupts - get Tx & Rx complete only */
  460. mci_writel(host, IDSTS64, IDMAC_INT_CLR);
  461. mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
  462. SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
  463. /* Set the descriptor base address */
  464. mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
  465. mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
  466. } else {
  467. /* Mask out interrupts - get Tx & Rx complete only */
  468. mci_writel(host, IDSTS, IDMAC_INT_CLR);
  469. mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
  470. SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
  471. /* Set the descriptor base address */
  472. mci_writel(host, DBADDR, host->sg_dma);
  473. }
  474. return 0;
  475. }
  476. static inline int dw_mci_prepare_desc64(struct dw_mci *host,
  477. struct mmc_data *data,
  478. unsigned int sg_len)
  479. {
  480. unsigned int desc_len;
  481. struct idmac_desc_64addr *desc_first, *desc_last, *desc;
  482. u32 val;
  483. int i;
  484. desc_first = desc_last = desc = host->sg_cpu;
  485. for (i = 0; i < sg_len; i++) {
  486. unsigned int length = sg_dma_len(&data->sg[i]);
  487. u64 mem_addr = sg_dma_address(&data->sg[i]);
  488. for ( ; length ; desc++) {
  489. desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
  490. length : DW_MCI_DESC_DATA_LENGTH;
  491. length -= desc_len;
  492. /*
  493. * Wait for the former clear OWN bit operation
  494. * of IDMAC to make sure that this descriptor
  495. * isn't still owned by IDMAC as IDMAC's write
  496. * ops and CPU's read ops are asynchronous.
  497. */
  498. if (readl_poll_timeout_atomic(&desc->des0, val,
  499. !(val & IDMAC_DES0_OWN),
  500. 10, 100 * USEC_PER_MSEC))
  501. goto err_own_bit;
  502. /*
  503. * Set the OWN bit and disable interrupts
  504. * for this descriptor
  505. */
  506. desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
  507. IDMAC_DES0_CH;
  508. /* Buffer length */
  509. IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
  510. /* Physical address to DMA to/from */
  511. desc->des4 = mem_addr & 0xffffffff;
  512. desc->des5 = mem_addr >> 32;
  513. /* Update physical address for the next desc */
  514. mem_addr += desc_len;
  515. /* Save pointer to the last descriptor */
  516. desc_last = desc;
  517. }
  518. }
  519. /* Set first descriptor */
  520. desc_first->des0 |= IDMAC_DES0_FD;
  521. /* Set last descriptor */
  522. desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
  523. desc_last->des0 |= IDMAC_DES0_LD;
  524. return 0;
  525. err_own_bit:
  526. /* restore the descriptor chain as it's polluted */
  527. dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
  528. memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
  529. dw_mci_idmac_init(host);
  530. return -EINVAL;
  531. }
  532. static inline int dw_mci_prepare_desc32(struct dw_mci *host,
  533. struct mmc_data *data,
  534. unsigned int sg_len)
  535. {
  536. unsigned int desc_len;
  537. struct idmac_desc *desc_first, *desc_last, *desc;
  538. u32 val;
  539. int i;
  540. desc_first = desc_last = desc = host->sg_cpu;
  541. for (i = 0; i < sg_len; i++) {
  542. unsigned int length = sg_dma_len(&data->sg[i]);
  543. u32 mem_addr = sg_dma_address(&data->sg[i]);
  544. for ( ; length ; desc++) {
  545. desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
  546. length : DW_MCI_DESC_DATA_LENGTH;
  547. length -= desc_len;
  548. /*
  549. * Wait for the former clear OWN bit operation
  550. * of IDMAC to make sure that this descriptor
  551. * isn't still owned by IDMAC as IDMAC's write
  552. * ops and CPU's read ops are asynchronous.
  553. */
  554. if (readl_poll_timeout_atomic(&desc->des0, val,
  555. IDMAC_OWN_CLR64(val),
  556. 10,
  557. 100 * USEC_PER_MSEC))
  558. goto err_own_bit;
  559. /*
  560. * Set the OWN bit and disable interrupts
  561. * for this descriptor
  562. */
  563. desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
  564. IDMAC_DES0_DIC |
  565. IDMAC_DES0_CH);
  566. /* Buffer length */
  567. IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
  568. /* Physical address to DMA to/from */
  569. desc->des2 = cpu_to_le32(mem_addr);
  570. /* Update physical address for the next desc */
  571. mem_addr += desc_len;
  572. /* Save pointer to the last descriptor */
  573. desc_last = desc;
  574. }
  575. }
  576. /* Set first descriptor */
  577. desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
  578. /* Set last descriptor */
  579. desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
  580. IDMAC_DES0_DIC));
  581. desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
  582. return 0;
  583. err_own_bit:
  584. /* restore the descriptor chain as it's polluted */
  585. dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
  586. memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
  587. dw_mci_idmac_init(host);
  588. return -EINVAL;
  589. }
  590. static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
  591. {
  592. u32 temp;
  593. int ret;
  594. if (host->dma_64bit_address == 1)
  595. ret = dw_mci_prepare_desc64(host, host->data, sg_len);
  596. else
  597. ret = dw_mci_prepare_desc32(host, host->data, sg_len);
  598. if (ret)
  599. goto out;
  600. /* drain writebuffer */
  601. wmb();
  602. /* Make sure to reset DMA in case we did PIO before this */
  603. dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
  604. dw_mci_idmac_reset(host);
  605. /* Select IDMAC interface */
  606. temp = mci_readl(host, CTRL);
  607. temp |= SDMMC_CTRL_USE_IDMAC;
  608. mci_writel(host, CTRL, temp);
  609. /* drain writebuffer */
  610. wmb();
  611. /* Enable the IDMAC */
  612. temp = mci_readl(host, BMOD);
  613. temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
  614. mci_writel(host, BMOD, temp);
  615. /* Start it running */
  616. mci_writel(host, PLDMND, 1);
  617. out:
  618. return ret;
  619. }
  620. static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
  621. .init = dw_mci_idmac_init,
  622. .start = dw_mci_idmac_start_dma,
  623. .stop = dw_mci_idmac_stop_dma,
  624. .complete = dw_mci_dmac_complete_dma,
  625. .cleanup = dw_mci_dma_cleanup,
  626. };
  627. static void dw_mci_edmac_stop_dma(struct dw_mci *host)
  628. {
  629. dmaengine_terminate_async(host->dms->ch);
  630. }
  631. static int dw_mci_edmac_start_dma(struct dw_mci *host,
  632. unsigned int sg_len)
  633. {
  634. struct dma_slave_config cfg;
  635. struct dma_async_tx_descriptor *desc = NULL;
  636. struct scatterlist *sgl = host->data->sg;
  637. static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
  638. u32 sg_elems = host->data->sg_len;
  639. u32 fifoth_val;
  640. u32 fifo_offset = host->fifo_reg - host->regs;
  641. int ret = 0;
  642. /* Set external dma config: burst size, burst width */
  643. memset(&cfg, 0, sizeof(cfg));
  644. cfg.dst_addr = host->phy_regs + fifo_offset;
  645. cfg.src_addr = cfg.dst_addr;
  646. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  647. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  648. /* Match burst msize with external dma config */
  649. fifoth_val = mci_readl(host, FIFOTH);
  650. cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
  651. cfg.src_maxburst = cfg.dst_maxburst;
  652. if (host->data->flags & MMC_DATA_WRITE)
  653. cfg.direction = DMA_MEM_TO_DEV;
  654. else
  655. cfg.direction = DMA_DEV_TO_MEM;
  656. ret = dmaengine_slave_config(host->dms->ch, &cfg);
  657. if (ret) {
  658. dev_err(host->dev, "Failed to config edmac.\n");
  659. return -EBUSY;
  660. }
  661. desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
  662. sg_len, cfg.direction,
  663. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  664. if (!desc) {
  665. dev_err(host->dev, "Can't prepare slave sg.\n");
  666. return -EBUSY;
  667. }
  668. /* Set dw_mci_dmac_complete_dma as callback */
  669. desc->callback = dw_mci_dmac_complete_dma;
  670. desc->callback_param = (void *)host;
  671. dmaengine_submit(desc);
  672. /* Flush cache before write */
  673. if (host->data->flags & MMC_DATA_WRITE)
  674. dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
  675. sg_elems, DMA_TO_DEVICE);
  676. dma_async_issue_pending(host->dms->ch);
  677. return 0;
  678. }
  679. static int dw_mci_edmac_init(struct dw_mci *host)
  680. {
  681. /* Request external dma channel */
  682. host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
  683. if (!host->dms)
  684. return -ENOMEM;
  685. host->dms->ch = dma_request_chan(host->dev, "rx-tx");
  686. if (IS_ERR(host->dms->ch)) {
  687. int ret = PTR_ERR(host->dms->ch);
  688. dev_err(host->dev, "Failed to get external DMA channel.\n");
  689. kfree(host->dms);
  690. host->dms = NULL;
  691. return ret;
  692. }
  693. return 0;
  694. }
  695. static void dw_mci_edmac_exit(struct dw_mci *host)
  696. {
  697. if (host->dms) {
  698. if (host->dms->ch) {
  699. dma_release_channel(host->dms->ch);
  700. host->dms->ch = NULL;
  701. }
  702. kfree(host->dms);
  703. host->dms = NULL;
  704. }
  705. }
  706. static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
  707. .init = dw_mci_edmac_init,
  708. .exit = dw_mci_edmac_exit,
  709. .start = dw_mci_edmac_start_dma,
  710. .stop = dw_mci_edmac_stop_dma,
  711. .complete = dw_mci_dmac_complete_dma,
  712. .cleanup = dw_mci_dma_cleanup,
  713. };
  714. static int dw_mci_pre_dma_transfer(struct dw_mci *host,
  715. struct mmc_data *data,
  716. int cookie)
  717. {
  718. struct scatterlist *sg;
  719. unsigned int i, sg_len;
  720. if (data->host_cookie == COOKIE_PRE_MAPPED)
  721. return data->sg_len;
  722. /*
  723. * We don't do DMA on "complex" transfers, i.e. with
  724. * non-word-aligned buffers or lengths. Also, we don't bother
  725. * with all the DMA setup overhead for short transfers.
  726. */
  727. if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
  728. return -EINVAL;
  729. if (data->blksz & 3)
  730. return -EINVAL;
  731. for_each_sg(data->sg, sg, data->sg_len, i) {
  732. if (sg->offset & 3 || sg->length & 3)
  733. return -EINVAL;
  734. }
  735. sg_len = dma_map_sg(host->dev,
  736. data->sg,
  737. data->sg_len,
  738. mmc_get_dma_dir(data));
  739. if (sg_len == 0)
  740. return -EINVAL;
  741. data->host_cookie = cookie;
  742. return sg_len;
  743. }
  744. static void dw_mci_pre_req(struct mmc_host *mmc,
  745. struct mmc_request *mrq)
  746. {
  747. struct dw_mci_slot *slot = mmc_priv(mmc);
  748. struct mmc_data *data = mrq->data;
  749. if (!slot->host->use_dma || !data)
  750. return;
  751. /* This data might be unmapped at this time */
  752. data->host_cookie = COOKIE_UNMAPPED;
  753. if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
  754. COOKIE_PRE_MAPPED) < 0)
  755. data->host_cookie = COOKIE_UNMAPPED;
  756. }
  757. static void dw_mci_post_req(struct mmc_host *mmc,
  758. struct mmc_request *mrq,
  759. int err)
  760. {
  761. struct dw_mci_slot *slot = mmc_priv(mmc);
  762. struct mmc_data *data = mrq->data;
  763. if (!slot->host->use_dma || !data)
  764. return;
  765. if (data->host_cookie != COOKIE_UNMAPPED)
  766. dma_unmap_sg(slot->host->dev,
  767. data->sg,
  768. data->sg_len,
  769. mmc_get_dma_dir(data));
  770. data->host_cookie = COOKIE_UNMAPPED;
  771. }
  772. static int dw_mci_get_cd(struct mmc_host *mmc)
  773. {
  774. int present;
  775. struct dw_mci_slot *slot = mmc_priv(mmc);
  776. struct dw_mci *host = slot->host;
  777. int gpio_cd = mmc_gpio_get_cd(mmc);
  778. /* Use platform get_cd function, else try onboard card detect */
  779. if (((mmc->caps & MMC_CAP_NEEDS_POLL)
  780. || !mmc_card_is_removable(mmc))) {
  781. present = 1;
  782. if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
  783. if (mmc->caps & MMC_CAP_NEEDS_POLL) {
  784. dev_info(&mmc->class_dev,
  785. "card is polling.\n");
  786. } else {
  787. dev_info(&mmc->class_dev,
  788. "card is non-removable.\n");
  789. }
  790. set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
  791. }
  792. return present;
  793. } else if (gpio_cd >= 0)
  794. present = gpio_cd;
  795. else
  796. present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
  797. == 0 ? 1 : 0;
  798. spin_lock_bh(&host->lock);
  799. if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
  800. dev_dbg(&mmc->class_dev, "card is present\n");
  801. else if (!present &&
  802. !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
  803. dev_dbg(&mmc->class_dev, "card is not present\n");
  804. spin_unlock_bh(&host->lock);
  805. return present;
  806. }
  807. static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
  808. {
  809. unsigned int blksz = data->blksz;
  810. static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
  811. u32 fifo_width = 1 << host->data_shift;
  812. u32 blksz_depth = blksz / fifo_width, fifoth_val;
  813. u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
  814. int idx = ARRAY_SIZE(mszs) - 1;
  815. /* pio should ship this scenario */
  816. if (!host->use_dma)
  817. return;
  818. tx_wmark = (host->fifo_depth) / 2;
  819. tx_wmark_invers = host->fifo_depth - tx_wmark;
  820. /*
  821. * MSIZE is '1',
  822. * if blksz is not a multiple of the FIFO width
  823. */
  824. if (blksz % fifo_width)
  825. goto done;
  826. do {
  827. if (!((blksz_depth % mszs[idx]) ||
  828. (tx_wmark_invers % mszs[idx]))) {
  829. msize = idx;
  830. rx_wmark = mszs[idx] - 1;
  831. break;
  832. }
  833. } while (--idx > 0);
  834. /*
  835. * If idx is '0', it won't be tried
  836. * Thus, initial values are uesed
  837. */
  838. done:
  839. fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
  840. mci_writel(host, FIFOTH, fifoth_val);
  841. }
  842. static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
  843. {
  844. unsigned int blksz = data->blksz;
  845. u32 blksz_depth, fifo_depth;
  846. u16 thld_size;
  847. u8 enable;
  848. /*
  849. * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
  850. * in the FIFO region, so we really shouldn't access it).
  851. */
  852. if (host->verid < DW_MMC_240A ||
  853. (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
  854. return;
  855. /*
  856. * Card write Threshold is introduced since 2.80a
  857. * It's used when HS400 mode is enabled.
  858. */
  859. if (data->flags & MMC_DATA_WRITE &&
  860. host->timing != MMC_TIMING_MMC_HS400)
  861. goto disable;
  862. if (data->flags & MMC_DATA_WRITE)
  863. enable = SDMMC_CARD_WR_THR_EN;
  864. else
  865. enable = SDMMC_CARD_RD_THR_EN;
  866. if (host->timing != MMC_TIMING_MMC_HS200 &&
  867. host->timing != MMC_TIMING_UHS_SDR104 &&
  868. host->timing != MMC_TIMING_MMC_HS400)
  869. goto disable;
  870. blksz_depth = blksz / (1 << host->data_shift);
  871. fifo_depth = host->fifo_depth;
  872. if (blksz_depth > fifo_depth)
  873. goto disable;
  874. /*
  875. * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
  876. * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
  877. * Currently just choose blksz.
  878. */
  879. thld_size = blksz;
  880. mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
  881. return;
  882. disable:
  883. mci_writel(host, CDTHRCTL, 0);
  884. }
  885. static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
  886. {
  887. unsigned long irqflags;
  888. int sg_len;
  889. u32 temp;
  890. host->using_dma = 0;
  891. /* If we don't have a channel, we can't do DMA */
  892. if (!host->use_dma)
  893. return -ENODEV;
  894. sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
  895. if (sg_len < 0) {
  896. host->dma_ops->stop(host);
  897. return sg_len;
  898. }
  899. host->using_dma = 1;
  900. if (host->use_dma == TRANS_MODE_IDMAC)
  901. dev_vdbg(host->dev,
  902. "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
  903. (unsigned long)host->sg_cpu,
  904. (unsigned long)host->sg_dma,
  905. sg_len);
  906. /*
  907. * Decide the MSIZE and RX/TX Watermark.
  908. * If current block size is same with previous size,
  909. * no need to update fifoth.
  910. */
  911. if (host->prev_blksz != data->blksz)
  912. dw_mci_adjust_fifoth(host, data);
  913. /* Enable the DMA interface */
  914. temp = mci_readl(host, CTRL);
  915. temp |= SDMMC_CTRL_DMA_ENABLE;
  916. mci_writel(host, CTRL, temp);
  917. /* Disable RX/TX IRQs, let DMA handle it */
  918. spin_lock_irqsave(&host->irq_lock, irqflags);
  919. temp = mci_readl(host, INTMASK);
  920. temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
  921. mci_writel(host, INTMASK, temp);
  922. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  923. if (host->dma_ops->start(host, sg_len)) {
  924. host->dma_ops->stop(host);
  925. /* We can't do DMA, try PIO for this one */
  926. dev_dbg(host->dev,
  927. "%s: fall back to PIO mode for current transfer\n",
  928. __func__);
  929. return -ENODEV;
  930. }
  931. return 0;
  932. }
  933. static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
  934. {
  935. unsigned long irqflags;
  936. int flags = SG_MITER_ATOMIC;
  937. u32 temp;
  938. data->error = -EINPROGRESS;
  939. WARN_ON(host->data);
  940. host->sg = NULL;
  941. host->data = data;
  942. if (data->flags & MMC_DATA_READ)
  943. host->dir_status = DW_MCI_RECV_STATUS;
  944. else
  945. host->dir_status = DW_MCI_SEND_STATUS;
  946. dw_mci_ctrl_thld(host, data);
  947. if (dw_mci_submit_data_dma(host, data)) {
  948. if (host->data->flags & MMC_DATA_READ)
  949. flags |= SG_MITER_TO_SG;
  950. else
  951. flags |= SG_MITER_FROM_SG;
  952. sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
  953. host->sg = data->sg;
  954. host->part_buf_start = 0;
  955. host->part_buf_count = 0;
  956. mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
  957. spin_lock_irqsave(&host->irq_lock, irqflags);
  958. temp = mci_readl(host, INTMASK);
  959. temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
  960. mci_writel(host, INTMASK, temp);
  961. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  962. temp = mci_readl(host, CTRL);
  963. temp &= ~SDMMC_CTRL_DMA_ENABLE;
  964. mci_writel(host, CTRL, temp);
  965. /*
  966. * Use the initial fifoth_val for PIO mode. If wm_algined
  967. * is set, we set watermark same as data size.
  968. * If next issued data may be transfered by DMA mode,
  969. * prev_blksz should be invalidated.
  970. */
  971. if (host->wm_aligned)
  972. dw_mci_adjust_fifoth(host, data);
  973. else
  974. mci_writel(host, FIFOTH, host->fifoth_val);
  975. host->prev_blksz = 0;
  976. } else {
  977. /*
  978. * Keep the current block size.
  979. * It will be used to decide whether to update
  980. * fifoth register next time.
  981. */
  982. host->prev_blksz = data->blksz;
  983. }
  984. }
  985. static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
  986. {
  987. struct dw_mci *host = slot->host;
  988. unsigned int clock = slot->clock;
  989. u32 div;
  990. u32 clk_en_a;
  991. u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
  992. /* We must continue to set bit 28 in CMD until the change is complete */
  993. if (host->state == STATE_WAITING_CMD11_DONE)
  994. sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
  995. slot->mmc->actual_clock = 0;
  996. if (!clock) {
  997. mci_writel(host, CLKENA, 0);
  998. mci_send_cmd(slot, sdmmc_cmd_bits, 0);
  999. } else if (clock != host->current_speed || force_clkinit) {
  1000. div = host->bus_hz / clock;
  1001. if (host->bus_hz % clock && host->bus_hz > clock)
  1002. /*
  1003. * move the + 1 after the divide to prevent
  1004. * over-clocking the card.
  1005. */
  1006. div += 1;
  1007. div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
  1008. if ((clock != slot->__clk_old &&
  1009. !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
  1010. force_clkinit) {
  1011. /* Silent the verbose log if calling from PM context */
  1012. if (!force_clkinit)
  1013. dev_info(&slot->mmc->class_dev,
  1014. "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
  1015. slot->id, host->bus_hz, clock,
  1016. div ? ((host->bus_hz / div) >> 1) :
  1017. host->bus_hz, div);
  1018. /*
  1019. * If card is polling, display the message only
  1020. * one time at boot time.
  1021. */
  1022. if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
  1023. slot->mmc->f_min == clock)
  1024. set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
  1025. }
  1026. /* disable clock */
  1027. mci_writel(host, CLKENA, 0);
  1028. mci_writel(host, CLKSRC, 0);
  1029. /* inform CIU */
  1030. mci_send_cmd(slot, sdmmc_cmd_bits, 0);
  1031. /* set clock to desired speed */
  1032. mci_writel(host, CLKDIV, div);
  1033. /* inform CIU */
  1034. mci_send_cmd(slot, sdmmc_cmd_bits, 0);
  1035. /* enable clock; only low power if no SDIO */
  1036. clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
  1037. if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
  1038. clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
  1039. mci_writel(host, CLKENA, clk_en_a);
  1040. /* inform CIU */
  1041. mci_send_cmd(slot, sdmmc_cmd_bits, 0);
  1042. /* keep the last clock value that was requested from core */
  1043. slot->__clk_old = clock;
  1044. slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
  1045. host->bus_hz;
  1046. }
  1047. host->current_speed = clock;
  1048. /* Set the current slot bus width */
  1049. mci_writel(host, CTYPE, (slot->ctype << slot->id));
  1050. }
  1051. static void __dw_mci_start_request(struct dw_mci *host,
  1052. struct dw_mci_slot *slot,
  1053. struct mmc_command *cmd)
  1054. {
  1055. struct mmc_request *mrq;
  1056. struct mmc_data *data;
  1057. u32 cmdflags;
  1058. mrq = slot->mrq;
  1059. host->mrq = mrq;
  1060. host->pending_events = 0;
  1061. host->completed_events = 0;
  1062. host->cmd_status = 0;
  1063. host->data_status = 0;
  1064. host->dir_status = 0;
  1065. data = cmd->data;
  1066. if (data) {
  1067. mci_writel(host, TMOUT, 0xFFFFFFFF);
  1068. mci_writel(host, BYTCNT, data->blksz*data->blocks);
  1069. mci_writel(host, BLKSIZ, data->blksz);
  1070. }
  1071. cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
  1072. /* this is the first command, send the initialization clock */
  1073. if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
  1074. cmdflags |= SDMMC_CMD_INIT;
  1075. if (data) {
  1076. dw_mci_submit_data(host, data);
  1077. wmb(); /* drain writebuffer */
  1078. }
  1079. dw_mci_start_command(host, cmd, cmdflags);
  1080. if (cmd->opcode == SD_SWITCH_VOLTAGE) {
  1081. unsigned long irqflags;
  1082. /*
  1083. * Databook says to fail after 2ms w/ no response, but evidence
  1084. * shows that sometimes the cmd11 interrupt takes over 130ms.
  1085. * We'll set to 500ms, plus an extra jiffy just in case jiffies
  1086. * is just about to roll over.
  1087. *
  1088. * We do this whole thing under spinlock and only if the
  1089. * command hasn't already completed (indicating the the irq
  1090. * already ran so we don't want the timeout).
  1091. */
  1092. spin_lock_irqsave(&host->irq_lock, irqflags);
  1093. if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
  1094. mod_timer(&host->cmd11_timer,
  1095. jiffies + msecs_to_jiffies(500) + 1);
  1096. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  1097. }
  1098. host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
  1099. }
  1100. static void dw_mci_start_request(struct dw_mci *host,
  1101. struct dw_mci_slot *slot)
  1102. {
  1103. struct mmc_request *mrq = slot->mrq;
  1104. struct mmc_command *cmd;
  1105. cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
  1106. __dw_mci_start_request(host, slot, cmd);
  1107. }
  1108. /* must be called with host->lock held */
  1109. static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
  1110. struct mmc_request *mrq)
  1111. {
  1112. dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
  1113. host->state);
  1114. slot->mrq = mrq;
  1115. if (host->state == STATE_WAITING_CMD11_DONE) {
  1116. dev_warn(&slot->mmc->class_dev,
  1117. "Voltage change didn't complete\n");
  1118. /*
  1119. * this case isn't expected to happen, so we can
  1120. * either crash here or just try to continue on
  1121. * in the closest possible state
  1122. */
  1123. host->state = STATE_IDLE;
  1124. }
  1125. if (host->state == STATE_IDLE) {
  1126. host->state = STATE_SENDING_CMD;
  1127. dw_mci_start_request(host, slot);
  1128. } else {
  1129. list_add_tail(&slot->queue_node, &host->queue);
  1130. }
  1131. }
  1132. static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  1133. {
  1134. struct dw_mci_slot *slot = mmc_priv(mmc);
  1135. struct dw_mci *host = slot->host;
  1136. WARN_ON(slot->mrq);
  1137. /*
  1138. * The check for card presence and queueing of the request must be
  1139. * atomic, otherwise the card could be removed in between and the
  1140. * request wouldn't fail until another card was inserted.
  1141. */
  1142. if (!dw_mci_get_cd(mmc)) {
  1143. mrq->cmd->error = -ENOMEDIUM;
  1144. mmc_request_done(mmc, mrq);
  1145. return;
  1146. }
  1147. spin_lock_bh(&host->lock);
  1148. dw_mci_queue_request(host, slot, mrq);
  1149. spin_unlock_bh(&host->lock);
  1150. }
  1151. static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1152. {
  1153. struct dw_mci_slot *slot = mmc_priv(mmc);
  1154. const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
  1155. u32 regs;
  1156. int ret;
  1157. switch (ios->bus_width) {
  1158. case MMC_BUS_WIDTH_4:
  1159. slot->ctype = SDMMC_CTYPE_4BIT;
  1160. break;
  1161. case MMC_BUS_WIDTH_8:
  1162. slot->ctype = SDMMC_CTYPE_8BIT;
  1163. break;
  1164. default:
  1165. /* set default 1 bit mode */
  1166. slot->ctype = SDMMC_CTYPE_1BIT;
  1167. }
  1168. regs = mci_readl(slot->host, UHS_REG);
  1169. /* DDR mode set */
  1170. if (ios->timing == MMC_TIMING_MMC_DDR52 ||
  1171. ios->timing == MMC_TIMING_UHS_DDR50 ||
  1172. ios->timing == MMC_TIMING_MMC_HS400)
  1173. regs |= ((0x1 << slot->id) << 16);
  1174. else
  1175. regs &= ~((0x1 << slot->id) << 16);
  1176. mci_writel(slot->host, UHS_REG, regs);
  1177. slot->host->timing = ios->timing;
  1178. /*
  1179. * Use mirror of ios->clock to prevent race with mmc
  1180. * core ios update when finding the minimum.
  1181. */
  1182. slot->clock = ios->clock;
  1183. if (drv_data && drv_data->set_ios)
  1184. drv_data->set_ios(slot->host, ios);
  1185. switch (ios->power_mode) {
  1186. case MMC_POWER_UP:
  1187. if (!IS_ERR(mmc->supply.vmmc)) {
  1188. ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
  1189. ios->vdd);
  1190. if (ret) {
  1191. dev_err(slot->host->dev,
  1192. "failed to enable vmmc regulator\n");
  1193. /*return, if failed turn on vmmc*/
  1194. return;
  1195. }
  1196. }
  1197. set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
  1198. regs = mci_readl(slot->host, PWREN);
  1199. regs |= (1 << slot->id);
  1200. mci_writel(slot->host, PWREN, regs);
  1201. break;
  1202. case MMC_POWER_ON:
  1203. if (!slot->host->vqmmc_enabled) {
  1204. if (!IS_ERR(mmc->supply.vqmmc)) {
  1205. ret = regulator_enable(mmc->supply.vqmmc);
  1206. if (ret < 0)
  1207. dev_err(slot->host->dev,
  1208. "failed to enable vqmmc\n");
  1209. else
  1210. slot->host->vqmmc_enabled = true;
  1211. } else {
  1212. /* Keep track so we don't reset again */
  1213. slot->host->vqmmc_enabled = true;
  1214. }
  1215. /* Reset our state machine after powering on */
  1216. dw_mci_ctrl_reset(slot->host,
  1217. SDMMC_CTRL_ALL_RESET_FLAGS);
  1218. }
  1219. /* Adjust clock / bus width after power is up */
  1220. dw_mci_setup_bus(slot, false);
  1221. break;
  1222. case MMC_POWER_OFF:
  1223. /* Turn clock off before power goes down */
  1224. dw_mci_setup_bus(slot, false);
  1225. if (!IS_ERR(mmc->supply.vmmc))
  1226. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  1227. if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
  1228. regulator_disable(mmc->supply.vqmmc);
  1229. slot->host->vqmmc_enabled = false;
  1230. regs = mci_readl(slot->host, PWREN);
  1231. regs &= ~(1 << slot->id);
  1232. mci_writel(slot->host, PWREN, regs);
  1233. break;
  1234. default:
  1235. break;
  1236. }
  1237. if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
  1238. slot->host->state = STATE_IDLE;
  1239. }
  1240. static int dw_mci_card_busy(struct mmc_host *mmc)
  1241. {
  1242. struct dw_mci_slot *slot = mmc_priv(mmc);
  1243. u32 status;
  1244. /*
  1245. * Check the busy bit which is low when DAT[3:0]
  1246. * (the data lines) are 0000
  1247. */
  1248. status = mci_readl(slot->host, STATUS);
  1249. return !!(status & SDMMC_STATUS_BUSY);
  1250. }
  1251. static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
  1252. {
  1253. struct dw_mci_slot *slot = mmc_priv(mmc);
  1254. struct dw_mci *host = slot->host;
  1255. const struct dw_mci_drv_data *drv_data = host->drv_data;
  1256. u32 uhs;
  1257. u32 v18 = SDMMC_UHS_18V << slot->id;
  1258. int ret;
  1259. if (drv_data && drv_data->switch_voltage)
  1260. return drv_data->switch_voltage(mmc, ios);
  1261. /*
  1262. * Program the voltage. Note that some instances of dw_mmc may use
  1263. * the UHS_REG for this. For other instances (like exynos) the UHS_REG
  1264. * does no harm but you need to set the regulator directly. Try both.
  1265. */
  1266. uhs = mci_readl(host, UHS_REG);
  1267. if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
  1268. uhs &= ~v18;
  1269. else
  1270. uhs |= v18;
  1271. if (!IS_ERR(mmc->supply.vqmmc)) {
  1272. ret = mmc_regulator_set_vqmmc(mmc, ios);
  1273. if (ret < 0) {
  1274. dev_dbg(&mmc->class_dev,
  1275. "Regulator set error %d - %s V\n",
  1276. ret, uhs & v18 ? "1.8" : "3.3");
  1277. return ret;
  1278. }
  1279. }
  1280. mci_writel(host, UHS_REG, uhs);
  1281. return 0;
  1282. }
  1283. static int dw_mci_get_ro(struct mmc_host *mmc)
  1284. {
  1285. int read_only;
  1286. struct dw_mci_slot *slot = mmc_priv(mmc);
  1287. int gpio_ro = mmc_gpio_get_ro(mmc);
  1288. /* Use platform get_ro function, else try on board write protect */
  1289. if (gpio_ro >= 0)
  1290. read_only = gpio_ro;
  1291. else
  1292. read_only =
  1293. mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
  1294. dev_dbg(&mmc->class_dev, "card is %s\n",
  1295. read_only ? "read-only" : "read-write");
  1296. return read_only;
  1297. }
  1298. static void dw_mci_hw_reset(struct mmc_host *mmc)
  1299. {
  1300. struct dw_mci_slot *slot = mmc_priv(mmc);
  1301. struct dw_mci *host = slot->host;
  1302. int reset;
  1303. if (host->use_dma == TRANS_MODE_IDMAC)
  1304. dw_mci_idmac_reset(host);
  1305. if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
  1306. SDMMC_CTRL_FIFO_RESET))
  1307. return;
  1308. /*
  1309. * According to eMMC spec, card reset procedure:
  1310. * tRstW >= 1us: RST_n pulse width
  1311. * tRSCA >= 200us: RST_n to Command time
  1312. * tRSTH >= 1us: RST_n high period
  1313. */
  1314. reset = mci_readl(host, RST_N);
  1315. reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
  1316. mci_writel(host, RST_N, reset);
  1317. usleep_range(1, 2);
  1318. reset |= SDMMC_RST_HWACTIVE << slot->id;
  1319. mci_writel(host, RST_N, reset);
  1320. usleep_range(200, 300);
  1321. }
  1322. static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
  1323. {
  1324. struct dw_mci_slot *slot = mmc_priv(mmc);
  1325. struct dw_mci *host = slot->host;
  1326. /*
  1327. * Low power mode will stop the card clock when idle. According to the
  1328. * description of the CLKENA register we should disable low power mode
  1329. * for SDIO cards if we need SDIO interrupts to work.
  1330. */
  1331. if (mmc->caps & MMC_CAP_SDIO_IRQ) {
  1332. const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
  1333. u32 clk_en_a_old;
  1334. u32 clk_en_a;
  1335. clk_en_a_old = mci_readl(host, CLKENA);
  1336. if (card->type == MMC_TYPE_SDIO ||
  1337. card->type == MMC_TYPE_SD_COMBO) {
  1338. set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
  1339. clk_en_a = clk_en_a_old & ~clken_low_pwr;
  1340. } else {
  1341. clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
  1342. clk_en_a = clk_en_a_old | clken_low_pwr;
  1343. }
  1344. if (clk_en_a != clk_en_a_old) {
  1345. mci_writel(host, CLKENA, clk_en_a);
  1346. mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
  1347. SDMMC_CMD_PRV_DAT_WAIT, 0);
  1348. }
  1349. }
  1350. }
  1351. static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
  1352. {
  1353. struct dw_mci *host = slot->host;
  1354. unsigned long irqflags;
  1355. u32 int_mask;
  1356. spin_lock_irqsave(&host->irq_lock, irqflags);
  1357. /* Enable/disable Slot Specific SDIO interrupt */
  1358. int_mask = mci_readl(host, INTMASK);
  1359. if (enb)
  1360. int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
  1361. else
  1362. int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
  1363. mci_writel(host, INTMASK, int_mask);
  1364. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  1365. }
  1366. static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
  1367. {
  1368. struct dw_mci_slot *slot = mmc_priv(mmc);
  1369. struct dw_mci *host = slot->host;
  1370. __dw_mci_enable_sdio_irq(slot, enb);
  1371. /* Avoid runtime suspending the device when SDIO IRQ is enabled */
  1372. if (enb)
  1373. pm_runtime_get_noresume(host->dev);
  1374. else
  1375. pm_runtime_put_noidle(host->dev);
  1376. }
  1377. static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
  1378. {
  1379. struct dw_mci_slot *slot = mmc_priv(mmc);
  1380. __dw_mci_enable_sdio_irq(slot, 1);
  1381. }
  1382. static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
  1383. {
  1384. struct dw_mci_slot *slot = mmc_priv(mmc);
  1385. struct dw_mci *host = slot->host;
  1386. const struct dw_mci_drv_data *drv_data = host->drv_data;
  1387. int err = -EINVAL;
  1388. if (drv_data && drv_data->execute_tuning)
  1389. err = drv_data->execute_tuning(slot, opcode);
  1390. return err;
  1391. }
  1392. static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
  1393. struct mmc_ios *ios)
  1394. {
  1395. struct dw_mci_slot *slot = mmc_priv(mmc);
  1396. struct dw_mci *host = slot->host;
  1397. const struct dw_mci_drv_data *drv_data = host->drv_data;
  1398. if (drv_data && drv_data->prepare_hs400_tuning)
  1399. return drv_data->prepare_hs400_tuning(host, ios);
  1400. return 0;
  1401. }
  1402. static bool dw_mci_reset(struct dw_mci *host)
  1403. {
  1404. u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
  1405. bool ret = false;
  1406. u32 status = 0;
  1407. /*
  1408. * Resetting generates a block interrupt, hence setting
  1409. * the scatter-gather pointer to NULL.
  1410. */
  1411. if (host->sg) {
  1412. sg_miter_stop(&host->sg_miter);
  1413. host->sg = NULL;
  1414. }
  1415. if (host->use_dma)
  1416. flags |= SDMMC_CTRL_DMA_RESET;
  1417. if (dw_mci_ctrl_reset(host, flags)) {
  1418. /*
  1419. * In all cases we clear the RAWINTS
  1420. * register to clear any interrupts.
  1421. */
  1422. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  1423. if (!host->use_dma) {
  1424. ret = true;
  1425. goto ciu_out;
  1426. }
  1427. /* Wait for dma_req to be cleared */
  1428. if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
  1429. status,
  1430. !(status & SDMMC_STATUS_DMA_REQ),
  1431. 1, 500 * USEC_PER_MSEC)) {
  1432. dev_err(host->dev,
  1433. "%s: Timeout waiting for dma_req to be cleared\n",
  1434. __func__);
  1435. goto ciu_out;
  1436. }
  1437. /* when using DMA next we reset the fifo again */
  1438. if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
  1439. goto ciu_out;
  1440. } else {
  1441. /* if the controller reset bit did clear, then set clock regs */
  1442. if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
  1443. dev_err(host->dev,
  1444. "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
  1445. __func__);
  1446. goto ciu_out;
  1447. }
  1448. }
  1449. if (host->use_dma == TRANS_MODE_IDMAC)
  1450. /* It is also required that we reinit idmac */
  1451. dw_mci_idmac_init(host);
  1452. ret = true;
  1453. ciu_out:
  1454. /* After a CTRL reset we need to have CIU set clock registers */
  1455. mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
  1456. return ret;
  1457. }
  1458. static const struct mmc_host_ops dw_mci_ops = {
  1459. .request = dw_mci_request,
  1460. .pre_req = dw_mci_pre_req,
  1461. .post_req = dw_mci_post_req,
  1462. .set_ios = dw_mci_set_ios,
  1463. .get_ro = dw_mci_get_ro,
  1464. .get_cd = dw_mci_get_cd,
  1465. .hw_reset = dw_mci_hw_reset,
  1466. .enable_sdio_irq = dw_mci_enable_sdio_irq,
  1467. .ack_sdio_irq = dw_mci_ack_sdio_irq,
  1468. .execute_tuning = dw_mci_execute_tuning,
  1469. .card_busy = dw_mci_card_busy,
  1470. .start_signal_voltage_switch = dw_mci_switch_voltage,
  1471. .init_card = dw_mci_init_card,
  1472. .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
  1473. };
  1474. static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
  1475. __releases(&host->lock)
  1476. __acquires(&host->lock)
  1477. {
  1478. struct dw_mci_slot *slot;
  1479. struct mmc_host *prev_mmc = host->slot->mmc;
  1480. WARN_ON(host->cmd || host->data);
  1481. host->slot->mrq = NULL;
  1482. host->mrq = NULL;
  1483. if (!list_empty(&host->queue)) {
  1484. slot = list_entry(host->queue.next,
  1485. struct dw_mci_slot, queue_node);
  1486. list_del(&slot->queue_node);
  1487. dev_vdbg(host->dev, "list not empty: %s is next\n",
  1488. mmc_hostname(slot->mmc));
  1489. host->state = STATE_SENDING_CMD;
  1490. dw_mci_start_request(host, slot);
  1491. } else {
  1492. dev_vdbg(host->dev, "list empty\n");
  1493. if (host->state == STATE_SENDING_CMD11)
  1494. host->state = STATE_WAITING_CMD11_DONE;
  1495. else
  1496. host->state = STATE_IDLE;
  1497. }
  1498. spin_unlock(&host->lock);
  1499. mmc_request_done(prev_mmc, mrq);
  1500. spin_lock(&host->lock);
  1501. }
  1502. static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
  1503. {
  1504. u32 status = host->cmd_status;
  1505. host->cmd_status = 0;
  1506. /* Read the response from the card (up to 16 bytes) */
  1507. if (cmd->flags & MMC_RSP_PRESENT) {
  1508. if (cmd->flags & MMC_RSP_136) {
  1509. cmd->resp[3] = mci_readl(host, RESP0);
  1510. cmd->resp[2] = mci_readl(host, RESP1);
  1511. cmd->resp[1] = mci_readl(host, RESP2);
  1512. cmd->resp[0] = mci_readl(host, RESP3);
  1513. } else {
  1514. cmd->resp[0] = mci_readl(host, RESP0);
  1515. cmd->resp[1] = 0;
  1516. cmd->resp[2] = 0;
  1517. cmd->resp[3] = 0;
  1518. }
  1519. }
  1520. if (status & SDMMC_INT_RTO)
  1521. cmd->error = -ETIMEDOUT;
  1522. else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
  1523. cmd->error = -EILSEQ;
  1524. else if (status & SDMMC_INT_RESP_ERR)
  1525. cmd->error = -EIO;
  1526. else
  1527. cmd->error = 0;
  1528. return cmd->error;
  1529. }
  1530. static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
  1531. {
  1532. u32 status = host->data_status;
  1533. if (status & DW_MCI_DATA_ERROR_FLAGS) {
  1534. if (status & SDMMC_INT_DRTO) {
  1535. data->error = -ETIMEDOUT;
  1536. } else if (status & SDMMC_INT_DCRC) {
  1537. data->error = -EILSEQ;
  1538. } else if (status & SDMMC_INT_EBE) {
  1539. if (host->dir_status ==
  1540. DW_MCI_SEND_STATUS) {
  1541. /*
  1542. * No data CRC status was returned.
  1543. * The number of bytes transferred
  1544. * will be exaggerated in PIO mode.
  1545. */
  1546. data->bytes_xfered = 0;
  1547. data->error = -ETIMEDOUT;
  1548. } else if (host->dir_status ==
  1549. DW_MCI_RECV_STATUS) {
  1550. data->error = -EILSEQ;
  1551. }
  1552. } else {
  1553. /* SDMMC_INT_SBE is included */
  1554. data->error = -EILSEQ;
  1555. }
  1556. dev_dbg(host->dev, "data error, status 0x%08x\n", status);
  1557. /*
  1558. * After an error, there may be data lingering
  1559. * in the FIFO
  1560. */
  1561. dw_mci_reset(host);
  1562. } else {
  1563. data->bytes_xfered = data->blocks * data->blksz;
  1564. data->error = 0;
  1565. }
  1566. return data->error;
  1567. }
  1568. static void dw_mci_set_drto(struct dw_mci *host)
  1569. {
  1570. unsigned int drto_clks;
  1571. unsigned int drto_div;
  1572. unsigned int drto_ms;
  1573. unsigned long irqflags;
  1574. drto_clks = mci_readl(host, TMOUT) >> 8;
  1575. drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
  1576. if (drto_div == 0)
  1577. drto_div = 1;
  1578. drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
  1579. host->bus_hz);
  1580. /* add a bit spare time */
  1581. drto_ms += 10;
  1582. spin_lock_irqsave(&host->irq_lock, irqflags);
  1583. if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
  1584. mod_timer(&host->dto_timer,
  1585. jiffies + msecs_to_jiffies(drto_ms));
  1586. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  1587. }
  1588. static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
  1589. {
  1590. if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
  1591. return false;
  1592. /*
  1593. * Really be certain that the timer has stopped. This is a bit of
  1594. * paranoia and could only really happen if we had really bad
  1595. * interrupt latency and the interrupt routine and timeout were
  1596. * running concurrently so that the del_timer() in the interrupt
  1597. * handler couldn't run.
  1598. */
  1599. WARN_ON(del_timer_sync(&host->cto_timer));
  1600. clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  1601. return true;
  1602. }
  1603. static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
  1604. {
  1605. if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
  1606. return false;
  1607. /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
  1608. WARN_ON(del_timer_sync(&host->dto_timer));
  1609. clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
  1610. return true;
  1611. }
  1612. static void dw_mci_tasklet_func(unsigned long priv)
  1613. {
  1614. struct dw_mci *host = (struct dw_mci *)priv;
  1615. struct mmc_data *data;
  1616. struct mmc_command *cmd;
  1617. struct mmc_request *mrq;
  1618. enum dw_mci_state state;
  1619. enum dw_mci_state prev_state;
  1620. unsigned int err;
  1621. spin_lock(&host->lock);
  1622. state = host->state;
  1623. data = host->data;
  1624. mrq = host->mrq;
  1625. do {
  1626. prev_state = state;
  1627. switch (state) {
  1628. case STATE_IDLE:
  1629. case STATE_WAITING_CMD11_DONE:
  1630. break;
  1631. case STATE_SENDING_CMD11:
  1632. case STATE_SENDING_CMD:
  1633. if (!dw_mci_clear_pending_cmd_complete(host))
  1634. break;
  1635. cmd = host->cmd;
  1636. host->cmd = NULL;
  1637. set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
  1638. err = dw_mci_command_complete(host, cmd);
  1639. if (cmd == mrq->sbc && !err) {
  1640. __dw_mci_start_request(host, host->slot,
  1641. mrq->cmd);
  1642. goto unlock;
  1643. }
  1644. if (cmd->data && err) {
  1645. /*
  1646. * During UHS tuning sequence, sending the stop
  1647. * command after the response CRC error would
  1648. * throw the system into a confused state
  1649. * causing all future tuning phases to report
  1650. * failure.
  1651. *
  1652. * In such case controller will move into a data
  1653. * transfer state after a response error or
  1654. * response CRC error. Let's let that finish
  1655. * before trying to send a stop, so we'll go to
  1656. * STATE_SENDING_DATA.
  1657. *
  1658. * Although letting the data transfer take place
  1659. * will waste a bit of time (we already know
  1660. * the command was bad), it can't cause any
  1661. * errors since it's possible it would have
  1662. * taken place anyway if this tasklet got
  1663. * delayed. Allowing the transfer to take place
  1664. * avoids races and keeps things simple.
  1665. */
  1666. if (err != -ETIMEDOUT &&
  1667. host->dir_status == DW_MCI_RECV_STATUS) {
  1668. state = STATE_SENDING_DATA;
  1669. continue;
  1670. }
  1671. send_stop_abort(host, data);
  1672. dw_mci_stop_dma(host);
  1673. state = STATE_SENDING_STOP;
  1674. break;
  1675. }
  1676. if (!cmd->data || err) {
  1677. dw_mci_request_end(host, mrq);
  1678. goto unlock;
  1679. }
  1680. prev_state = state = STATE_SENDING_DATA;
  1681. fallthrough;
  1682. case STATE_SENDING_DATA:
  1683. /*
  1684. * We could get a data error and never a transfer
  1685. * complete so we'd better check for it here.
  1686. *
  1687. * Note that we don't really care if we also got a
  1688. * transfer complete; stopping the DMA and sending an
  1689. * abort won't hurt.
  1690. */
  1691. if (test_and_clear_bit(EVENT_DATA_ERROR,
  1692. &host->pending_events)) {
  1693. if (!(host->data_status & (SDMMC_INT_DRTO |
  1694. SDMMC_INT_EBE)))
  1695. send_stop_abort(host, data);
  1696. dw_mci_stop_dma(host);
  1697. state = STATE_DATA_ERROR;
  1698. break;
  1699. }
  1700. if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
  1701. &host->pending_events)) {
  1702. /*
  1703. * If all data-related interrupts don't come
  1704. * within the given time in reading data state.
  1705. */
  1706. if (host->dir_status == DW_MCI_RECV_STATUS)
  1707. dw_mci_set_drto(host);
  1708. break;
  1709. }
  1710. set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
  1711. /*
  1712. * Handle an EVENT_DATA_ERROR that might have shown up
  1713. * before the transfer completed. This might not have
  1714. * been caught by the check above because the interrupt
  1715. * could have gone off between the previous check and
  1716. * the check for transfer complete.
  1717. *
  1718. * Technically this ought not be needed assuming we
  1719. * get a DATA_COMPLETE eventually (we'll notice the
  1720. * error and end the request), but it shouldn't hurt.
  1721. *
  1722. * This has the advantage of sending the stop command.
  1723. */
  1724. if (test_and_clear_bit(EVENT_DATA_ERROR,
  1725. &host->pending_events)) {
  1726. if (!(host->data_status & (SDMMC_INT_DRTO |
  1727. SDMMC_INT_EBE)))
  1728. send_stop_abort(host, data);
  1729. dw_mci_stop_dma(host);
  1730. state = STATE_DATA_ERROR;
  1731. break;
  1732. }
  1733. prev_state = state = STATE_DATA_BUSY;
  1734. fallthrough;
  1735. case STATE_DATA_BUSY:
  1736. if (!dw_mci_clear_pending_data_complete(host)) {
  1737. /*
  1738. * If data error interrupt comes but data over
  1739. * interrupt doesn't come within the given time.
  1740. * in reading data state.
  1741. */
  1742. if (host->dir_status == DW_MCI_RECV_STATUS)
  1743. dw_mci_set_drto(host);
  1744. break;
  1745. }
  1746. host->data = NULL;
  1747. set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
  1748. err = dw_mci_data_complete(host, data);
  1749. if (!err) {
  1750. if (!data->stop || mrq->sbc) {
  1751. if (mrq->sbc && data->stop)
  1752. data->stop->error = 0;
  1753. dw_mci_request_end(host, mrq);
  1754. goto unlock;
  1755. }
  1756. /* stop command for open-ended transfer*/
  1757. if (data->stop)
  1758. send_stop_abort(host, data);
  1759. } else {
  1760. /*
  1761. * If we don't have a command complete now we'll
  1762. * never get one since we just reset everything;
  1763. * better end the request.
  1764. *
  1765. * If we do have a command complete we'll fall
  1766. * through to the SENDING_STOP command and
  1767. * everything will be peachy keen.
  1768. */
  1769. if (!test_bit(EVENT_CMD_COMPLETE,
  1770. &host->pending_events)) {
  1771. host->cmd = NULL;
  1772. dw_mci_request_end(host, mrq);
  1773. goto unlock;
  1774. }
  1775. }
  1776. /*
  1777. * If err has non-zero,
  1778. * stop-abort command has been already issued.
  1779. */
  1780. prev_state = state = STATE_SENDING_STOP;
  1781. fallthrough;
  1782. case STATE_SENDING_STOP:
  1783. if (!dw_mci_clear_pending_cmd_complete(host))
  1784. break;
  1785. /* CMD error in data command */
  1786. if (mrq->cmd->error && mrq->data)
  1787. dw_mci_reset(host);
  1788. host->cmd = NULL;
  1789. host->data = NULL;
  1790. if (!mrq->sbc && mrq->stop)
  1791. dw_mci_command_complete(host, mrq->stop);
  1792. else
  1793. host->cmd_status = 0;
  1794. dw_mci_request_end(host, mrq);
  1795. goto unlock;
  1796. case STATE_DATA_ERROR:
  1797. if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
  1798. &host->pending_events))
  1799. break;
  1800. state = STATE_DATA_BUSY;
  1801. break;
  1802. }
  1803. } while (state != prev_state);
  1804. host->state = state;
  1805. unlock:
  1806. spin_unlock(&host->lock);
  1807. }
  1808. /* push final bytes to part_buf, only use during push */
  1809. static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
  1810. {
  1811. memcpy((void *)&host->part_buf, buf, cnt);
  1812. host->part_buf_count = cnt;
  1813. }
  1814. /* append bytes to part_buf, only use during push */
  1815. static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
  1816. {
  1817. cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
  1818. memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
  1819. host->part_buf_count += cnt;
  1820. return cnt;
  1821. }
  1822. /* pull first bytes from part_buf, only use during pull */
  1823. static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
  1824. {
  1825. cnt = min_t(int, cnt, host->part_buf_count);
  1826. if (cnt) {
  1827. memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
  1828. cnt);
  1829. host->part_buf_count -= cnt;
  1830. host->part_buf_start += cnt;
  1831. }
  1832. return cnt;
  1833. }
  1834. /* pull final bytes from the part_buf, assuming it's just been filled */
  1835. static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
  1836. {
  1837. memcpy(buf, &host->part_buf, cnt);
  1838. host->part_buf_start = cnt;
  1839. host->part_buf_count = (1 << host->data_shift) - cnt;
  1840. }
  1841. static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
  1842. {
  1843. struct mmc_data *data = host->data;
  1844. int init_cnt = cnt;
  1845. /* try and push anything in the part_buf */
  1846. if (unlikely(host->part_buf_count)) {
  1847. int len = dw_mci_push_part_bytes(host, buf, cnt);
  1848. buf += len;
  1849. cnt -= len;
  1850. if (host->part_buf_count == 2) {
  1851. mci_fifo_writew(host->fifo_reg, host->part_buf16);
  1852. host->part_buf_count = 0;
  1853. }
  1854. }
  1855. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1856. if (unlikely((unsigned long)buf & 0x1)) {
  1857. while (cnt >= 2) {
  1858. u16 aligned_buf[64];
  1859. int len = min(cnt & -2, (int)sizeof(aligned_buf));
  1860. int items = len >> 1;
  1861. int i;
  1862. /* memcpy from input buffer into aligned buffer */
  1863. memcpy(aligned_buf, buf, len);
  1864. buf += len;
  1865. cnt -= len;
  1866. /* push data from aligned buffer into fifo */
  1867. for (i = 0; i < items; ++i)
  1868. mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
  1869. }
  1870. } else
  1871. #endif
  1872. {
  1873. u16 *pdata = buf;
  1874. for (; cnt >= 2; cnt -= 2)
  1875. mci_fifo_writew(host->fifo_reg, *pdata++);
  1876. buf = pdata;
  1877. }
  1878. /* put anything remaining in the part_buf */
  1879. if (cnt) {
  1880. dw_mci_set_part_bytes(host, buf, cnt);
  1881. /* Push data if we have reached the expected data length */
  1882. if ((data->bytes_xfered + init_cnt) ==
  1883. (data->blksz * data->blocks))
  1884. mci_fifo_writew(host->fifo_reg, host->part_buf16);
  1885. }
  1886. }
  1887. static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
  1888. {
  1889. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1890. if (unlikely((unsigned long)buf & 0x1)) {
  1891. while (cnt >= 2) {
  1892. /* pull data from fifo into aligned buffer */
  1893. u16 aligned_buf[64];
  1894. int len = min(cnt & -2, (int)sizeof(aligned_buf));
  1895. int items = len >> 1;
  1896. int i;
  1897. for (i = 0; i < items; ++i)
  1898. aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
  1899. /* memcpy from aligned buffer into output buffer */
  1900. memcpy(buf, aligned_buf, len);
  1901. buf += len;
  1902. cnt -= len;
  1903. }
  1904. } else
  1905. #endif
  1906. {
  1907. u16 *pdata = buf;
  1908. for (; cnt >= 2; cnt -= 2)
  1909. *pdata++ = mci_fifo_readw(host->fifo_reg);
  1910. buf = pdata;
  1911. }
  1912. if (cnt) {
  1913. host->part_buf16 = mci_fifo_readw(host->fifo_reg);
  1914. dw_mci_pull_final_bytes(host, buf, cnt);
  1915. }
  1916. }
  1917. static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
  1918. {
  1919. struct mmc_data *data = host->data;
  1920. int init_cnt = cnt;
  1921. /* try and push anything in the part_buf */
  1922. if (unlikely(host->part_buf_count)) {
  1923. int len = dw_mci_push_part_bytes(host, buf, cnt);
  1924. buf += len;
  1925. cnt -= len;
  1926. if (host->part_buf_count == 4) {
  1927. mci_fifo_writel(host->fifo_reg, host->part_buf32);
  1928. host->part_buf_count = 0;
  1929. }
  1930. }
  1931. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1932. if (unlikely((unsigned long)buf & 0x3)) {
  1933. while (cnt >= 4) {
  1934. u32 aligned_buf[32];
  1935. int len = min(cnt & -4, (int)sizeof(aligned_buf));
  1936. int items = len >> 2;
  1937. int i;
  1938. /* memcpy from input buffer into aligned buffer */
  1939. memcpy(aligned_buf, buf, len);
  1940. buf += len;
  1941. cnt -= len;
  1942. /* push data from aligned buffer into fifo */
  1943. for (i = 0; i < items; ++i)
  1944. mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
  1945. }
  1946. } else
  1947. #endif
  1948. {
  1949. u32 *pdata = buf;
  1950. for (; cnt >= 4; cnt -= 4)
  1951. mci_fifo_writel(host->fifo_reg, *pdata++);
  1952. buf = pdata;
  1953. }
  1954. /* put anything remaining in the part_buf */
  1955. if (cnt) {
  1956. dw_mci_set_part_bytes(host, buf, cnt);
  1957. /* Push data if we have reached the expected data length */
  1958. if ((data->bytes_xfered + init_cnt) ==
  1959. (data->blksz * data->blocks))
  1960. mci_fifo_writel(host->fifo_reg, host->part_buf32);
  1961. }
  1962. }
  1963. static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
  1964. {
  1965. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1966. if (unlikely((unsigned long)buf & 0x3)) {
  1967. while (cnt >= 4) {
  1968. /* pull data from fifo into aligned buffer */
  1969. u32 aligned_buf[32];
  1970. int len = min(cnt & -4, (int)sizeof(aligned_buf));
  1971. int items = len >> 2;
  1972. int i;
  1973. for (i = 0; i < items; ++i)
  1974. aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
  1975. /* memcpy from aligned buffer into output buffer */
  1976. memcpy(buf, aligned_buf, len);
  1977. buf += len;
  1978. cnt -= len;
  1979. }
  1980. } else
  1981. #endif
  1982. {
  1983. u32 *pdata = buf;
  1984. for (; cnt >= 4; cnt -= 4)
  1985. *pdata++ = mci_fifo_readl(host->fifo_reg);
  1986. buf = pdata;
  1987. }
  1988. if (cnt) {
  1989. host->part_buf32 = mci_fifo_readl(host->fifo_reg);
  1990. dw_mci_pull_final_bytes(host, buf, cnt);
  1991. }
  1992. }
  1993. static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
  1994. {
  1995. struct mmc_data *data = host->data;
  1996. int init_cnt = cnt;
  1997. /* try and push anything in the part_buf */
  1998. if (unlikely(host->part_buf_count)) {
  1999. int len = dw_mci_push_part_bytes(host, buf, cnt);
  2000. buf += len;
  2001. cnt -= len;
  2002. if (host->part_buf_count == 8) {
  2003. mci_fifo_writeq(host->fifo_reg, host->part_buf);
  2004. host->part_buf_count = 0;
  2005. }
  2006. }
  2007. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  2008. if (unlikely((unsigned long)buf & 0x7)) {
  2009. while (cnt >= 8) {
  2010. u64 aligned_buf[16];
  2011. int len = min(cnt & -8, (int)sizeof(aligned_buf));
  2012. int items = len >> 3;
  2013. int i;
  2014. /* memcpy from input buffer into aligned buffer */
  2015. memcpy(aligned_buf, buf, len);
  2016. buf += len;
  2017. cnt -= len;
  2018. /* push data from aligned buffer into fifo */
  2019. for (i = 0; i < items; ++i)
  2020. mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
  2021. }
  2022. } else
  2023. #endif
  2024. {
  2025. u64 *pdata = buf;
  2026. for (; cnt >= 8; cnt -= 8)
  2027. mci_fifo_writeq(host->fifo_reg, *pdata++);
  2028. buf = pdata;
  2029. }
  2030. /* put anything remaining in the part_buf */
  2031. if (cnt) {
  2032. dw_mci_set_part_bytes(host, buf, cnt);
  2033. /* Push data if we have reached the expected data length */
  2034. if ((data->bytes_xfered + init_cnt) ==
  2035. (data->blksz * data->blocks))
  2036. mci_fifo_writeq(host->fifo_reg, host->part_buf);
  2037. }
  2038. }
  2039. static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
  2040. {
  2041. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  2042. if (unlikely((unsigned long)buf & 0x7)) {
  2043. while (cnt >= 8) {
  2044. /* pull data from fifo into aligned buffer */
  2045. u64 aligned_buf[16];
  2046. int len = min(cnt & -8, (int)sizeof(aligned_buf));
  2047. int items = len >> 3;
  2048. int i;
  2049. for (i = 0; i < items; ++i)
  2050. aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
  2051. /* memcpy from aligned buffer into output buffer */
  2052. memcpy(buf, aligned_buf, len);
  2053. buf += len;
  2054. cnt -= len;
  2055. }
  2056. } else
  2057. #endif
  2058. {
  2059. u64 *pdata = buf;
  2060. for (; cnt >= 8; cnt -= 8)
  2061. *pdata++ = mci_fifo_readq(host->fifo_reg);
  2062. buf = pdata;
  2063. }
  2064. if (cnt) {
  2065. host->part_buf = mci_fifo_readq(host->fifo_reg);
  2066. dw_mci_pull_final_bytes(host, buf, cnt);
  2067. }
  2068. }
  2069. static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
  2070. {
  2071. int len;
  2072. /* get remaining partial bytes */
  2073. len = dw_mci_pull_part_bytes(host, buf, cnt);
  2074. if (unlikely(len == cnt))
  2075. return;
  2076. buf += len;
  2077. cnt -= len;
  2078. /* get the rest of the data */
  2079. host->pull_data(host, buf, cnt);
  2080. }
  2081. static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
  2082. {
  2083. struct sg_mapping_iter *sg_miter = &host->sg_miter;
  2084. void *buf;
  2085. unsigned int offset;
  2086. struct mmc_data *data = host->data;
  2087. int shift = host->data_shift;
  2088. u32 status;
  2089. unsigned int len;
  2090. unsigned int remain, fcnt;
  2091. do {
  2092. if (!sg_miter_next(sg_miter))
  2093. goto done;
  2094. host->sg = sg_miter->piter.sg;
  2095. buf = sg_miter->addr;
  2096. remain = sg_miter->length;
  2097. offset = 0;
  2098. do {
  2099. fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
  2100. << shift) + host->part_buf_count;
  2101. len = min(remain, fcnt);
  2102. if (!len)
  2103. break;
  2104. dw_mci_pull_data(host, (void *)(buf + offset), len);
  2105. data->bytes_xfered += len;
  2106. offset += len;
  2107. remain -= len;
  2108. } while (remain);
  2109. sg_miter->consumed = offset;
  2110. status = mci_readl(host, MINTSTS);
  2111. mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
  2112. /* if the RXDR is ready read again */
  2113. } while ((status & SDMMC_INT_RXDR) ||
  2114. (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
  2115. if (!remain) {
  2116. if (!sg_miter_next(sg_miter))
  2117. goto done;
  2118. sg_miter->consumed = 0;
  2119. }
  2120. sg_miter_stop(sg_miter);
  2121. return;
  2122. done:
  2123. sg_miter_stop(sg_miter);
  2124. host->sg = NULL;
  2125. smp_wmb(); /* drain writebuffer */
  2126. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  2127. }
  2128. static void dw_mci_write_data_pio(struct dw_mci *host)
  2129. {
  2130. struct sg_mapping_iter *sg_miter = &host->sg_miter;
  2131. void *buf;
  2132. unsigned int offset;
  2133. struct mmc_data *data = host->data;
  2134. int shift = host->data_shift;
  2135. u32 status;
  2136. unsigned int len;
  2137. unsigned int fifo_depth = host->fifo_depth;
  2138. unsigned int remain, fcnt;
  2139. do {
  2140. if (!sg_miter_next(sg_miter))
  2141. goto done;
  2142. host->sg = sg_miter->piter.sg;
  2143. buf = sg_miter->addr;
  2144. remain = sg_miter->length;
  2145. offset = 0;
  2146. do {
  2147. fcnt = ((fifo_depth -
  2148. SDMMC_GET_FCNT(mci_readl(host, STATUS)))
  2149. << shift) - host->part_buf_count;
  2150. len = min(remain, fcnt);
  2151. if (!len)
  2152. break;
  2153. host->push_data(host, (void *)(buf + offset), len);
  2154. data->bytes_xfered += len;
  2155. offset += len;
  2156. remain -= len;
  2157. } while (remain);
  2158. sg_miter->consumed = offset;
  2159. status = mci_readl(host, MINTSTS);
  2160. mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
  2161. } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
  2162. if (!remain) {
  2163. if (!sg_miter_next(sg_miter))
  2164. goto done;
  2165. sg_miter->consumed = 0;
  2166. }
  2167. sg_miter_stop(sg_miter);
  2168. return;
  2169. done:
  2170. sg_miter_stop(sg_miter);
  2171. host->sg = NULL;
  2172. smp_wmb(); /* drain writebuffer */
  2173. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  2174. }
  2175. static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
  2176. {
  2177. del_timer(&host->cto_timer);
  2178. if (!host->cmd_status)
  2179. host->cmd_status = status;
  2180. smp_wmb(); /* drain writebuffer */
  2181. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  2182. tasklet_schedule(&host->tasklet);
  2183. }
  2184. static void dw_mci_handle_cd(struct dw_mci *host)
  2185. {
  2186. struct dw_mci_slot *slot = host->slot;
  2187. if (slot->mmc->ops->card_event)
  2188. slot->mmc->ops->card_event(slot->mmc);
  2189. mmc_detect_change(slot->mmc,
  2190. msecs_to_jiffies(host->pdata->detect_delay_ms));
  2191. }
  2192. static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
  2193. {
  2194. struct dw_mci *host = dev_id;
  2195. u32 pending;
  2196. struct dw_mci_slot *slot = host->slot;
  2197. unsigned long irqflags;
  2198. pending = mci_readl(host, MINTSTS); /* read-only mask reg */
  2199. if (pending) {
  2200. /* Check volt switch first, since it can look like an error */
  2201. if ((host->state == STATE_SENDING_CMD11) &&
  2202. (pending & SDMMC_INT_VOLT_SWITCH)) {
  2203. mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
  2204. pending &= ~SDMMC_INT_VOLT_SWITCH;
  2205. /*
  2206. * Hold the lock; we know cmd11_timer can't be kicked
  2207. * off after the lock is released, so safe to delete.
  2208. */
  2209. spin_lock_irqsave(&host->irq_lock, irqflags);
  2210. dw_mci_cmd_interrupt(host, pending);
  2211. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2212. del_timer(&host->cmd11_timer);
  2213. }
  2214. if (pending & DW_MCI_CMD_ERROR_FLAGS) {
  2215. spin_lock_irqsave(&host->irq_lock, irqflags);
  2216. del_timer(&host->cto_timer);
  2217. mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
  2218. host->cmd_status = pending;
  2219. smp_wmb(); /* drain writebuffer */
  2220. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  2221. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2222. }
  2223. if (pending & DW_MCI_DATA_ERROR_FLAGS) {
  2224. /* if there is an error report DATA_ERROR */
  2225. mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
  2226. host->data_status = pending;
  2227. smp_wmb(); /* drain writebuffer */
  2228. set_bit(EVENT_DATA_ERROR, &host->pending_events);
  2229. tasklet_schedule(&host->tasklet);
  2230. }
  2231. if (pending & SDMMC_INT_DATA_OVER) {
  2232. spin_lock_irqsave(&host->irq_lock, irqflags);
  2233. del_timer(&host->dto_timer);
  2234. mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
  2235. if (!host->data_status)
  2236. host->data_status = pending;
  2237. smp_wmb(); /* drain writebuffer */
  2238. if (host->dir_status == DW_MCI_RECV_STATUS) {
  2239. if (host->sg != NULL)
  2240. dw_mci_read_data_pio(host, true);
  2241. }
  2242. set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
  2243. tasklet_schedule(&host->tasklet);
  2244. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2245. }
  2246. if (pending & SDMMC_INT_RXDR) {
  2247. mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
  2248. if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
  2249. dw_mci_read_data_pio(host, false);
  2250. }
  2251. if (pending & SDMMC_INT_TXDR) {
  2252. mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
  2253. if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
  2254. dw_mci_write_data_pio(host);
  2255. }
  2256. if (pending & SDMMC_INT_CMD_DONE) {
  2257. spin_lock_irqsave(&host->irq_lock, irqflags);
  2258. mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
  2259. dw_mci_cmd_interrupt(host, pending);
  2260. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2261. }
  2262. if (pending & SDMMC_INT_CD) {
  2263. mci_writel(host, RINTSTS, SDMMC_INT_CD);
  2264. dw_mci_handle_cd(host);
  2265. }
  2266. if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
  2267. mci_writel(host, RINTSTS,
  2268. SDMMC_INT_SDIO(slot->sdio_id));
  2269. __dw_mci_enable_sdio_irq(slot, 0);
  2270. sdio_signal_irq(slot->mmc);
  2271. }
  2272. }
  2273. if (host->use_dma != TRANS_MODE_IDMAC)
  2274. return IRQ_HANDLED;
  2275. /* Handle IDMA interrupts */
  2276. if (host->dma_64bit_address == 1) {
  2277. pending = mci_readl(host, IDSTS64);
  2278. if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
  2279. mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
  2280. SDMMC_IDMAC_INT_RI);
  2281. mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
  2282. if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
  2283. host->dma_ops->complete((void *)host);
  2284. }
  2285. } else {
  2286. pending = mci_readl(host, IDSTS);
  2287. if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
  2288. mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
  2289. SDMMC_IDMAC_INT_RI);
  2290. mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
  2291. if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
  2292. host->dma_ops->complete((void *)host);
  2293. }
  2294. }
  2295. return IRQ_HANDLED;
  2296. }
  2297. static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
  2298. {
  2299. struct dw_mci *host = slot->host;
  2300. const struct dw_mci_drv_data *drv_data = host->drv_data;
  2301. struct mmc_host *mmc = slot->mmc;
  2302. int ctrl_id;
  2303. if (host->pdata->caps)
  2304. mmc->caps = host->pdata->caps;
  2305. if (host->pdata->pm_caps)
  2306. mmc->pm_caps = host->pdata->pm_caps;
  2307. if (host->dev->of_node) {
  2308. ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
  2309. if (ctrl_id < 0)
  2310. ctrl_id = 0;
  2311. } else {
  2312. ctrl_id = to_platform_device(host->dev)->id;
  2313. }
  2314. if (drv_data && drv_data->caps) {
  2315. if (ctrl_id >= drv_data->num_caps) {
  2316. dev_err(host->dev, "invalid controller id %d\n",
  2317. ctrl_id);
  2318. return -EINVAL;
  2319. }
  2320. mmc->caps |= drv_data->caps[ctrl_id];
  2321. }
  2322. if (host->pdata->caps2)
  2323. mmc->caps2 = host->pdata->caps2;
  2324. mmc->f_min = DW_MCI_FREQ_MIN;
  2325. if (!mmc->f_max)
  2326. mmc->f_max = DW_MCI_FREQ_MAX;
  2327. /* Process SDIO IRQs through the sdio_irq_work. */
  2328. if (mmc->caps & MMC_CAP_SDIO_IRQ)
  2329. mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
  2330. return 0;
  2331. }
  2332. static int dw_mci_init_slot(struct dw_mci *host)
  2333. {
  2334. struct mmc_host *mmc;
  2335. struct dw_mci_slot *slot;
  2336. int ret;
  2337. mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
  2338. if (!mmc)
  2339. return -ENOMEM;
  2340. slot = mmc_priv(mmc);
  2341. slot->id = 0;
  2342. slot->sdio_id = host->sdio_id0 + slot->id;
  2343. slot->mmc = mmc;
  2344. slot->host = host;
  2345. host->slot = slot;
  2346. mmc->ops = &dw_mci_ops;
  2347. /*if there are external regulators, get them*/
  2348. ret = mmc_regulator_get_supply(mmc);
  2349. if (ret)
  2350. goto err_host_allocated;
  2351. if (!mmc->ocr_avail)
  2352. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  2353. ret = mmc_of_parse(mmc);
  2354. if (ret)
  2355. goto err_host_allocated;
  2356. ret = dw_mci_init_slot_caps(slot);
  2357. if (ret)
  2358. goto err_host_allocated;
  2359. /* Useful defaults if platform data is unset. */
  2360. if (host->use_dma == TRANS_MODE_IDMAC) {
  2361. mmc->max_segs = host->ring_size;
  2362. mmc->max_blk_size = 65535;
  2363. mmc->max_seg_size = 0x1000;
  2364. mmc->max_req_size = mmc->max_seg_size * host->ring_size;
  2365. mmc->max_blk_count = mmc->max_req_size / 512;
  2366. } else if (host->use_dma == TRANS_MODE_EDMAC) {
  2367. mmc->max_segs = 64;
  2368. mmc->max_blk_size = 65535;
  2369. mmc->max_blk_count = 65535;
  2370. mmc->max_req_size =
  2371. mmc->max_blk_size * mmc->max_blk_count;
  2372. mmc->max_seg_size = mmc->max_req_size;
  2373. } else {
  2374. /* TRANS_MODE_PIO */
  2375. mmc->max_segs = 64;
  2376. mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
  2377. mmc->max_blk_count = 512;
  2378. mmc->max_req_size = mmc->max_blk_size *
  2379. mmc->max_blk_count;
  2380. mmc->max_seg_size = mmc->max_req_size;
  2381. }
  2382. dw_mci_get_cd(mmc);
  2383. ret = mmc_add_host(mmc);
  2384. if (ret)
  2385. goto err_host_allocated;
  2386. #if defined(CONFIG_DEBUG_FS)
  2387. dw_mci_init_debugfs(slot);
  2388. #endif
  2389. return 0;
  2390. err_host_allocated:
  2391. mmc_free_host(mmc);
  2392. return ret;
  2393. }
  2394. static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
  2395. {
  2396. /* Debugfs stuff is cleaned up by mmc core */
  2397. mmc_remove_host(slot->mmc);
  2398. slot->host->slot = NULL;
  2399. mmc_free_host(slot->mmc);
  2400. }
  2401. static void dw_mci_init_dma(struct dw_mci *host)
  2402. {
  2403. int addr_config;
  2404. struct device *dev = host->dev;
  2405. /*
  2406. * Check tansfer mode from HCON[17:16]
  2407. * Clear the ambiguous description of dw_mmc databook:
  2408. * 2b'00: No DMA Interface -> Actually means using Internal DMA block
  2409. * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
  2410. * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
  2411. * 2b'11: Non DW DMA Interface -> pio only
  2412. * Compared to DesignWare DMA Interface, Generic DMA Interface has a
  2413. * simpler request/acknowledge handshake mechanism and both of them
  2414. * are regarded as external dma master for dw_mmc.
  2415. */
  2416. host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
  2417. if (host->use_dma == DMA_INTERFACE_IDMA) {
  2418. host->use_dma = TRANS_MODE_IDMAC;
  2419. } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
  2420. host->use_dma == DMA_INTERFACE_GDMA) {
  2421. host->use_dma = TRANS_MODE_EDMAC;
  2422. } else {
  2423. goto no_dma;
  2424. }
  2425. /* Determine which DMA interface to use */
  2426. if (host->use_dma == TRANS_MODE_IDMAC) {
  2427. /*
  2428. * Check ADDR_CONFIG bit in HCON to find
  2429. * IDMAC address bus width
  2430. */
  2431. addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
  2432. if (addr_config == 1) {
  2433. /* host supports IDMAC in 64-bit address mode */
  2434. host->dma_64bit_address = 1;
  2435. dev_info(host->dev,
  2436. "IDMAC supports 64-bit address mode.\n");
  2437. if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
  2438. dma_set_coherent_mask(host->dev,
  2439. DMA_BIT_MASK(64));
  2440. } else {
  2441. /* host supports IDMAC in 32-bit address mode */
  2442. host->dma_64bit_address = 0;
  2443. dev_info(host->dev,
  2444. "IDMAC supports 32-bit address mode.\n");
  2445. }
  2446. /* Alloc memory for sg translation */
  2447. host->sg_cpu = dmam_alloc_coherent(host->dev,
  2448. DESC_RING_BUF_SZ,
  2449. &host->sg_dma, GFP_KERNEL);
  2450. if (!host->sg_cpu) {
  2451. dev_err(host->dev,
  2452. "%s: could not alloc DMA memory\n",
  2453. __func__);
  2454. goto no_dma;
  2455. }
  2456. host->dma_ops = &dw_mci_idmac_ops;
  2457. dev_info(host->dev, "Using internal DMA controller.\n");
  2458. } else {
  2459. /* TRANS_MODE_EDMAC: check dma bindings again */
  2460. if ((device_property_read_string_array(dev, "dma-names",
  2461. NULL, 0) < 0) ||
  2462. !device_property_present(dev, "dmas")) {
  2463. goto no_dma;
  2464. }
  2465. host->dma_ops = &dw_mci_edmac_ops;
  2466. dev_info(host->dev, "Using external DMA controller.\n");
  2467. }
  2468. if (host->dma_ops->init && host->dma_ops->start &&
  2469. host->dma_ops->stop && host->dma_ops->cleanup) {
  2470. if (host->dma_ops->init(host)) {
  2471. dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
  2472. __func__);
  2473. goto no_dma;
  2474. }
  2475. } else {
  2476. dev_err(host->dev, "DMA initialization not found.\n");
  2477. goto no_dma;
  2478. }
  2479. return;
  2480. no_dma:
  2481. dev_info(host->dev, "Using PIO mode.\n");
  2482. host->use_dma = TRANS_MODE_PIO;
  2483. }
  2484. static void dw_mci_cmd11_timer(struct timer_list *t)
  2485. {
  2486. struct dw_mci *host = from_timer(host, t, cmd11_timer);
  2487. if (host->state != STATE_SENDING_CMD11) {
  2488. dev_warn(host->dev, "Unexpected CMD11 timeout\n");
  2489. return;
  2490. }
  2491. host->cmd_status = SDMMC_INT_RTO;
  2492. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  2493. tasklet_schedule(&host->tasklet);
  2494. }
  2495. static void dw_mci_cto_timer(struct timer_list *t)
  2496. {
  2497. struct dw_mci *host = from_timer(host, t, cto_timer);
  2498. unsigned long irqflags;
  2499. u32 pending;
  2500. spin_lock_irqsave(&host->irq_lock, irqflags);
  2501. /*
  2502. * If somehow we have very bad interrupt latency it's remotely possible
  2503. * that the timer could fire while the interrupt is still pending or
  2504. * while the interrupt is midway through running. Let's be paranoid
  2505. * and detect those two cases. Note that this is paranoia is somewhat
  2506. * justified because in this function we don't actually cancel the
  2507. * pending command in the controller--we just assume it will never come.
  2508. */
  2509. pending = mci_readl(host, MINTSTS); /* read-only mask reg */
  2510. if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
  2511. /* The interrupt should fire; no need to act but we can warn */
  2512. dev_warn(host->dev, "Unexpected interrupt latency\n");
  2513. goto exit;
  2514. }
  2515. if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
  2516. /* Presumably interrupt handler couldn't delete the timer */
  2517. dev_warn(host->dev, "CTO timeout when already completed\n");
  2518. goto exit;
  2519. }
  2520. /*
  2521. * Continued paranoia to make sure we're in the state we expect.
  2522. * This paranoia isn't really justified but it seems good to be safe.
  2523. */
  2524. switch (host->state) {
  2525. case STATE_SENDING_CMD11:
  2526. case STATE_SENDING_CMD:
  2527. case STATE_SENDING_STOP:
  2528. /*
  2529. * If CMD_DONE interrupt does NOT come in sending command
  2530. * state, we should notify the driver to terminate current
  2531. * transfer and report a command timeout to the core.
  2532. */
  2533. host->cmd_status = SDMMC_INT_RTO;
  2534. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  2535. tasklet_schedule(&host->tasklet);
  2536. break;
  2537. default:
  2538. dev_warn(host->dev, "Unexpected command timeout, state %d\n",
  2539. host->state);
  2540. break;
  2541. }
  2542. exit:
  2543. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2544. }
  2545. static void dw_mci_dto_timer(struct timer_list *t)
  2546. {
  2547. struct dw_mci *host = from_timer(host, t, dto_timer);
  2548. unsigned long irqflags;
  2549. u32 pending;
  2550. spin_lock_irqsave(&host->irq_lock, irqflags);
  2551. /*
  2552. * The DTO timer is much longer than the CTO timer, so it's even less
  2553. * likely that we'll these cases, but it pays to be paranoid.
  2554. */
  2555. pending = mci_readl(host, MINTSTS); /* read-only mask reg */
  2556. if (pending & SDMMC_INT_DATA_OVER) {
  2557. /* The interrupt should fire; no need to act but we can warn */
  2558. dev_warn(host->dev, "Unexpected data interrupt latency\n");
  2559. goto exit;
  2560. }
  2561. if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
  2562. /* Presumably interrupt handler couldn't delete the timer */
  2563. dev_warn(host->dev, "DTO timeout when already completed\n");
  2564. goto exit;
  2565. }
  2566. /*
  2567. * Continued paranoia to make sure we're in the state we expect.
  2568. * This paranoia isn't really justified but it seems good to be safe.
  2569. */
  2570. switch (host->state) {
  2571. case STATE_SENDING_DATA:
  2572. case STATE_DATA_BUSY:
  2573. /*
  2574. * If DTO interrupt does NOT come in sending data state,
  2575. * we should notify the driver to terminate current transfer
  2576. * and report a data timeout to the core.
  2577. */
  2578. host->data_status = SDMMC_INT_DRTO;
  2579. set_bit(EVENT_DATA_ERROR, &host->pending_events);
  2580. set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
  2581. tasklet_schedule(&host->tasklet);
  2582. break;
  2583. default:
  2584. dev_warn(host->dev, "Unexpected data timeout, state %d\n",
  2585. host->state);
  2586. break;
  2587. }
  2588. exit:
  2589. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2590. }
  2591. #ifdef CONFIG_OF
  2592. static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
  2593. {
  2594. struct dw_mci_board *pdata;
  2595. struct device *dev = host->dev;
  2596. const struct dw_mci_drv_data *drv_data = host->drv_data;
  2597. int ret;
  2598. u32 clock_frequency;
  2599. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  2600. if (!pdata)
  2601. return ERR_PTR(-ENOMEM);
  2602. /* find reset controller when exist */
  2603. pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
  2604. if (IS_ERR(pdata->rstc)) {
  2605. if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
  2606. return ERR_PTR(-EPROBE_DEFER);
  2607. }
  2608. if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
  2609. dev_info(dev,
  2610. "fifo-depth property not found, using value of FIFOTH register as default\n");
  2611. device_property_read_u32(dev, "card-detect-delay",
  2612. &pdata->detect_delay_ms);
  2613. device_property_read_u32(dev, "data-addr", &host->data_addr_override);
  2614. if (device_property_present(dev, "fifo-watermark-aligned"))
  2615. host->wm_aligned = true;
  2616. if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
  2617. pdata->bus_hz = clock_frequency;
  2618. if (drv_data && drv_data->parse_dt) {
  2619. ret = drv_data->parse_dt(host);
  2620. if (ret)
  2621. return ERR_PTR(ret);
  2622. }
  2623. return pdata;
  2624. }
  2625. #else /* CONFIG_OF */
  2626. static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
  2627. {
  2628. return ERR_PTR(-EINVAL);
  2629. }
  2630. #endif /* CONFIG_OF */
  2631. static void dw_mci_enable_cd(struct dw_mci *host)
  2632. {
  2633. unsigned long irqflags;
  2634. u32 temp;
  2635. /*
  2636. * No need for CD if all slots have a non-error GPIO
  2637. * as well as broken card detection is found.
  2638. */
  2639. if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
  2640. return;
  2641. if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
  2642. spin_lock_irqsave(&host->irq_lock, irqflags);
  2643. temp = mci_readl(host, INTMASK);
  2644. temp |= SDMMC_INT_CD;
  2645. mci_writel(host, INTMASK, temp);
  2646. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2647. }
  2648. }
  2649. int dw_mci_probe(struct dw_mci *host)
  2650. {
  2651. const struct dw_mci_drv_data *drv_data = host->drv_data;
  2652. int width, i, ret = 0;
  2653. u32 fifo_size;
  2654. if (!host->pdata) {
  2655. host->pdata = dw_mci_parse_dt(host);
  2656. if (IS_ERR(host->pdata))
  2657. return dev_err_probe(host->dev, PTR_ERR(host->pdata),
  2658. "platform data not available\n");
  2659. }
  2660. host->biu_clk = devm_clk_get(host->dev, "biu");
  2661. if (IS_ERR(host->biu_clk)) {
  2662. dev_dbg(host->dev, "biu clock not available\n");
  2663. } else {
  2664. ret = clk_prepare_enable(host->biu_clk);
  2665. if (ret) {
  2666. dev_err(host->dev, "failed to enable biu clock\n");
  2667. return ret;
  2668. }
  2669. }
  2670. host->ciu_clk = devm_clk_get(host->dev, "ciu");
  2671. if (IS_ERR(host->ciu_clk)) {
  2672. dev_dbg(host->dev, "ciu clock not available\n");
  2673. host->bus_hz = host->pdata->bus_hz;
  2674. } else {
  2675. ret = clk_prepare_enable(host->ciu_clk);
  2676. if (ret) {
  2677. dev_err(host->dev, "failed to enable ciu clock\n");
  2678. goto err_clk_biu;
  2679. }
  2680. if (host->pdata->bus_hz) {
  2681. ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
  2682. if (ret)
  2683. dev_warn(host->dev,
  2684. "Unable to set bus rate to %uHz\n",
  2685. host->pdata->bus_hz);
  2686. }
  2687. host->bus_hz = clk_get_rate(host->ciu_clk);
  2688. }
  2689. if (!host->bus_hz) {
  2690. dev_err(host->dev,
  2691. "Platform data must supply bus speed\n");
  2692. ret = -ENODEV;
  2693. goto err_clk_ciu;
  2694. }
  2695. if (!IS_ERR(host->pdata->rstc)) {
  2696. reset_control_assert(host->pdata->rstc);
  2697. usleep_range(10, 50);
  2698. reset_control_deassert(host->pdata->rstc);
  2699. }
  2700. if (drv_data && drv_data->init) {
  2701. ret = drv_data->init(host);
  2702. if (ret) {
  2703. dev_err(host->dev,
  2704. "implementation specific init failed\n");
  2705. goto err_clk_ciu;
  2706. }
  2707. }
  2708. timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
  2709. timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
  2710. timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
  2711. spin_lock_init(&host->lock);
  2712. spin_lock_init(&host->irq_lock);
  2713. INIT_LIST_HEAD(&host->queue);
  2714. /*
  2715. * Get the host data width - this assumes that HCON has been set with
  2716. * the correct values.
  2717. */
  2718. i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
  2719. if (!i) {
  2720. host->push_data = dw_mci_push_data16;
  2721. host->pull_data = dw_mci_pull_data16;
  2722. width = 16;
  2723. host->data_shift = 1;
  2724. } else if (i == 2) {
  2725. host->push_data = dw_mci_push_data64;
  2726. host->pull_data = dw_mci_pull_data64;
  2727. width = 64;
  2728. host->data_shift = 3;
  2729. } else {
  2730. /* Check for a reserved value, and warn if it is */
  2731. WARN((i != 1),
  2732. "HCON reports a reserved host data width!\n"
  2733. "Defaulting to 32-bit access.\n");
  2734. host->push_data = dw_mci_push_data32;
  2735. host->pull_data = dw_mci_pull_data32;
  2736. width = 32;
  2737. host->data_shift = 2;
  2738. }
  2739. /* Reset all blocks */
  2740. if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
  2741. ret = -ENODEV;
  2742. goto err_clk_ciu;
  2743. }
  2744. host->dma_ops = host->pdata->dma_ops;
  2745. dw_mci_init_dma(host);
  2746. /* Clear the interrupts for the host controller */
  2747. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2748. mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
  2749. /* Put in max timeout */
  2750. mci_writel(host, TMOUT, 0xFFFFFFFF);
  2751. /*
  2752. * FIFO threshold settings RxMark = fifo_size / 2 - 1,
  2753. * Tx Mark = fifo_size / 2 DMA Size = 8
  2754. */
  2755. if (!host->pdata->fifo_depth) {
  2756. /*
  2757. * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
  2758. * have been overwritten by the bootloader, just like we're
  2759. * about to do, so if you know the value for your hardware, you
  2760. * should put it in the platform data.
  2761. */
  2762. fifo_size = mci_readl(host, FIFOTH);
  2763. fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
  2764. } else {
  2765. fifo_size = host->pdata->fifo_depth;
  2766. }
  2767. host->fifo_depth = fifo_size;
  2768. host->fifoth_val =
  2769. SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
  2770. mci_writel(host, FIFOTH, host->fifoth_val);
  2771. /* disable clock to CIU */
  2772. mci_writel(host, CLKENA, 0);
  2773. mci_writel(host, CLKSRC, 0);
  2774. /*
  2775. * In 2.40a spec, Data offset is changed.
  2776. * Need to check the version-id and set data-offset for DATA register.
  2777. */
  2778. host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
  2779. dev_info(host->dev, "Version ID is %04x\n", host->verid);
  2780. if (host->data_addr_override)
  2781. host->fifo_reg = host->regs + host->data_addr_override;
  2782. else if (host->verid < DW_MMC_240A)
  2783. host->fifo_reg = host->regs + DATA_OFFSET;
  2784. else
  2785. host->fifo_reg = host->regs + DATA_240A_OFFSET;
  2786. tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
  2787. ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
  2788. host->irq_flags, "dw-mci", host);
  2789. if (ret)
  2790. goto err_dmaunmap;
  2791. /*
  2792. * Enable interrupts for command done, data over, data empty,
  2793. * receive ready and error such as transmit, receive timeout, crc error
  2794. */
  2795. mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
  2796. SDMMC_INT_TXDR | SDMMC_INT_RXDR |
  2797. DW_MCI_ERROR_FLAGS);
  2798. /* Enable mci interrupt */
  2799. mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
  2800. dev_info(host->dev,
  2801. "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
  2802. host->irq, width, fifo_size);
  2803. /* We need at least one slot to succeed */
  2804. ret = dw_mci_init_slot(host);
  2805. if (ret) {
  2806. dev_dbg(host->dev, "slot %d init failed\n", i);
  2807. goto err_dmaunmap;
  2808. }
  2809. /* Now that slots are all setup, we can enable card detect */
  2810. dw_mci_enable_cd(host);
  2811. return 0;
  2812. err_dmaunmap:
  2813. if (host->use_dma && host->dma_ops->exit)
  2814. host->dma_ops->exit(host);
  2815. if (!IS_ERR(host->pdata->rstc))
  2816. reset_control_assert(host->pdata->rstc);
  2817. err_clk_ciu:
  2818. clk_disable_unprepare(host->ciu_clk);
  2819. err_clk_biu:
  2820. clk_disable_unprepare(host->biu_clk);
  2821. return ret;
  2822. }
  2823. EXPORT_SYMBOL(dw_mci_probe);
  2824. void dw_mci_remove(struct dw_mci *host)
  2825. {
  2826. dev_dbg(host->dev, "remove slot\n");
  2827. if (host->slot)
  2828. dw_mci_cleanup_slot(host->slot);
  2829. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2830. mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
  2831. /* disable clock to CIU */
  2832. mci_writel(host, CLKENA, 0);
  2833. mci_writel(host, CLKSRC, 0);
  2834. if (host->use_dma && host->dma_ops->exit)
  2835. host->dma_ops->exit(host);
  2836. if (!IS_ERR(host->pdata->rstc))
  2837. reset_control_assert(host->pdata->rstc);
  2838. clk_disable_unprepare(host->ciu_clk);
  2839. clk_disable_unprepare(host->biu_clk);
  2840. }
  2841. EXPORT_SYMBOL(dw_mci_remove);
  2842. #ifdef CONFIG_PM
  2843. int dw_mci_runtime_suspend(struct device *dev)
  2844. {
  2845. struct dw_mci *host = dev_get_drvdata(dev);
  2846. if (host->use_dma && host->dma_ops->exit)
  2847. host->dma_ops->exit(host);
  2848. clk_disable_unprepare(host->ciu_clk);
  2849. if (host->slot &&
  2850. (mmc_can_gpio_cd(host->slot->mmc) ||
  2851. !mmc_card_is_removable(host->slot->mmc)))
  2852. clk_disable_unprepare(host->biu_clk);
  2853. return 0;
  2854. }
  2855. EXPORT_SYMBOL(dw_mci_runtime_suspend);
  2856. int dw_mci_runtime_resume(struct device *dev)
  2857. {
  2858. int ret = 0;
  2859. struct dw_mci *host = dev_get_drvdata(dev);
  2860. if (host->slot &&
  2861. (mmc_can_gpio_cd(host->slot->mmc) ||
  2862. !mmc_card_is_removable(host->slot->mmc))) {
  2863. ret = clk_prepare_enable(host->biu_clk);
  2864. if (ret)
  2865. return ret;
  2866. }
  2867. ret = clk_prepare_enable(host->ciu_clk);
  2868. if (ret)
  2869. goto err;
  2870. if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
  2871. clk_disable_unprepare(host->ciu_clk);
  2872. ret = -ENODEV;
  2873. goto err;
  2874. }
  2875. if (host->use_dma && host->dma_ops->init)
  2876. host->dma_ops->init(host);
  2877. /*
  2878. * Restore the initial value at FIFOTH register
  2879. * And Invalidate the prev_blksz with zero
  2880. */
  2881. mci_writel(host, FIFOTH, host->fifoth_val);
  2882. host->prev_blksz = 0;
  2883. /* Put in max timeout */
  2884. mci_writel(host, TMOUT, 0xFFFFFFFF);
  2885. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2886. mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
  2887. SDMMC_INT_TXDR | SDMMC_INT_RXDR |
  2888. DW_MCI_ERROR_FLAGS);
  2889. mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
  2890. if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
  2891. dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
  2892. /* Force setup bus to guarantee available clock output */
  2893. dw_mci_setup_bus(host->slot, true);
  2894. /* Re-enable SDIO interrupts. */
  2895. if (sdio_irq_claimed(host->slot->mmc))
  2896. __dw_mci_enable_sdio_irq(host->slot, 1);
  2897. /* Now that slots are all setup, we can enable card detect */
  2898. dw_mci_enable_cd(host);
  2899. return 0;
  2900. err:
  2901. if (host->slot &&
  2902. (mmc_can_gpio_cd(host->slot->mmc) ||
  2903. !mmc_card_is_removable(host->slot->mmc)))
  2904. clk_disable_unprepare(host->biu_clk);
  2905. return ret;
  2906. }
  2907. EXPORT_SYMBOL(dw_mci_runtime_resume);
  2908. #endif /* CONFIG_PM */
  2909. static int __init dw_mci_init(void)
  2910. {
  2911. pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
  2912. return 0;
  2913. }
  2914. static void __exit dw_mci_exit(void)
  2915. {
  2916. }
  2917. module_init(dw_mci_init);
  2918. module_exit(dw_mci_exit);
  2919. MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
  2920. MODULE_AUTHOR("NXP Semiconductor VietNam");
  2921. MODULE_AUTHOR("Imagination Technologies Ltd");
  2922. MODULE_LICENSE("GPL v2");