dw_mmc-zx.h 1018 B

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _DW_MMC_ZX_H_
  3. #define _DW_MMC_ZX_H_
  4. /* ZX296718 SoC specific DLL register offset. */
  5. #define LB_AON_EMMC_CFG_REG0 0x1B0
  6. #define LB_AON_EMMC_CFG_REG1 0x1B4
  7. #define LB_AON_EMMC_CFG_REG2 0x1B8
  8. /* LB_AON_EMMC_CFG_REG0 register defines */
  9. #define PARA_DLL_START(x) ((x) & 0xFF)
  10. #define PARA_DLL_START_MASK 0xFF
  11. #define DLL_REG_SET BIT(8)
  12. #define PARA_DLL_LOCK_NUM(x) (((x) & 7) << 16)
  13. #define PARA_DLL_LOCK_NUM_MASK (7 << 16)
  14. #define PARA_PHASE_DET_SEL(x) (((x) & 7) << 20)
  15. #define PARA_PHASE_DET_SEL_MASK (7 << 20)
  16. #define PARA_DLL_BYPASS_MODE BIT(23)
  17. #define PARA_HALF_CLK_MODE BIT(24)
  18. /* LB_AON_EMMC_CFG_REG1 register defines */
  19. #define READ_DQS_DELAY(x) ((x) & 0x7F)
  20. #define READ_DQS_DELAY_MASK (0x7F)
  21. #define READ_DQS_BYPASS_MODE BIT(7)
  22. #define CLK_SAMP_DELAY(x) (((x) & 0x7F) << 8)
  23. #define CLK_SAMP_DELAY_MASK (0x7F << 8)
  24. #define CLK_SAMP_BYPASS_MODE BIT(15)
  25. /* LB_AON_EMMC_CFG_REG2 register defines */
  26. #define ZX_DLL_LOCKED BIT(2)
  27. #endif /* _DW_MMC_ZX_H_ */