dw_mmc-rockchip.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
  4. */
  5. #include <linux/module.h>
  6. #include <linux/platform_device.h>
  7. #include <linux/clk.h>
  8. #include <linux/mmc/host.h>
  9. #include <linux/of_address.h>
  10. #include <linux/mmc/slot-gpio.h>
  11. #include <linux/pm_runtime.h>
  12. #include <linux/slab.h>
  13. #include "dw_mmc.h"
  14. #include "dw_mmc-pltfm.h"
  15. #define RK3288_CLKGEN_DIV 2
  16. struct dw_mci_rockchip_priv_data {
  17. struct clk *drv_clk;
  18. struct clk *sample_clk;
  19. int default_sample_phase;
  20. int num_phases;
  21. };
  22. static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
  23. {
  24. struct dw_mci_rockchip_priv_data *priv = host->priv;
  25. int ret;
  26. unsigned int cclkin;
  27. u32 bus_hz;
  28. if (ios->clock == 0)
  29. return;
  30. /*
  31. * cclkin: source clock of mmc controller
  32. * bus_hz: card interface clock generated by CLKGEN
  33. * bus_hz = cclkin / RK3288_CLKGEN_DIV
  34. * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
  35. *
  36. * Note: div can only be 0 or 1, but div must be set to 1 for eMMC
  37. * DDR52 8-bit mode.
  38. */
  39. if (ios->bus_width == MMC_BUS_WIDTH_8 &&
  40. ios->timing == MMC_TIMING_MMC_DDR52)
  41. cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
  42. else
  43. cclkin = ios->clock * RK3288_CLKGEN_DIV;
  44. ret = clk_set_rate(host->ciu_clk, cclkin);
  45. if (ret)
  46. dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
  47. bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
  48. if (bus_hz != host->bus_hz) {
  49. host->bus_hz = bus_hz;
  50. /* force dw_mci_setup_bus() */
  51. host->current_speed = 0;
  52. }
  53. /* Make sure we use phases which we can enumerate with */
  54. if (!IS_ERR(priv->sample_clk))
  55. clk_set_phase(priv->sample_clk, priv->default_sample_phase);
  56. /*
  57. * Set the drive phase offset based on speed mode to achieve hold times.
  58. *
  59. * NOTE: this is _not_ a value that is dynamically tuned and is also
  60. * _not_ a value that will vary from board to board. It is a value
  61. * that could vary between different SoC models if they had massively
  62. * different output clock delays inside their dw_mmc IP block (delay_o),
  63. * but since it's OK to overshoot a little we don't need to do complex
  64. * calculations and can pick values that will just work for everyone.
  65. *
  66. * When picking values we'll stick with picking 0/90/180/270 since
  67. * those can be made very accurately on all known Rockchip SoCs.
  68. *
  69. * Note that these values match values from the DesignWare Databook
  70. * tables for the most part except for SDR12 and "ID mode". For those
  71. * two modes the databook calculations assume a clock in of 50MHz. As
  72. * seen above, we always use a clock in rate that is exactly the
  73. * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
  74. * back out before the controller sees it).
  75. *
  76. * From measurement of a single device, it appears that delay_o is
  77. * about .5 ns. Since we try to leave a bit of margin, it's expected
  78. * that numbers here will be fine even with much larger delay_o
  79. * (the 1.4 ns assumed by the DesignWare Databook would result in the
  80. * same results, for instance).
  81. */
  82. if (!IS_ERR(priv->drv_clk)) {
  83. int phase;
  84. /*
  85. * In almost all cases a 90 degree phase offset will provide
  86. * sufficient hold times across all valid input clock rates
  87. * assuming delay_o is not absurd for a given SoC. We'll use
  88. * that as a default.
  89. */
  90. phase = 90;
  91. switch (ios->timing) {
  92. case MMC_TIMING_MMC_DDR52:
  93. /*
  94. * Since clock in rate with MMC_DDR52 is doubled when
  95. * bus width is 8 we need to double the phase offset
  96. * to get the same timings.
  97. */
  98. if (ios->bus_width == MMC_BUS_WIDTH_8)
  99. phase = 180;
  100. break;
  101. case MMC_TIMING_UHS_SDR104:
  102. case MMC_TIMING_MMC_HS200:
  103. /*
  104. * In the case of 150 MHz clock (typical max for
  105. * Rockchip SoCs), 90 degree offset will add a delay
  106. * of 1.67 ns. That will meet min hold time of .8 ns
  107. * as long as clock output delay is < .87 ns. On
  108. * SoCs measured this seems to be OK, but it doesn't
  109. * hurt to give margin here, so we use 180.
  110. */
  111. phase = 180;
  112. break;
  113. }
  114. clk_set_phase(priv->drv_clk, phase);
  115. }
  116. }
  117. #define TUNING_ITERATION_TO_PHASE(i, num_phases) \
  118. (DIV_ROUND_UP((i) * 360, num_phases))
  119. static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
  120. {
  121. struct dw_mci *host = slot->host;
  122. struct dw_mci_rockchip_priv_data *priv = host->priv;
  123. struct mmc_host *mmc = slot->mmc;
  124. int ret = 0;
  125. int i;
  126. bool v, prev_v = 0, first_v;
  127. struct range_t {
  128. int start;
  129. int end; /* inclusive */
  130. };
  131. struct range_t *ranges;
  132. unsigned int range_count = 0;
  133. int longest_range_len = -1;
  134. int longest_range = -1;
  135. int middle_phase;
  136. if (IS_ERR(priv->sample_clk)) {
  137. dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
  138. return -EIO;
  139. }
  140. ranges = kmalloc_array(priv->num_phases / 2 + 1,
  141. sizeof(*ranges), GFP_KERNEL);
  142. if (!ranges)
  143. return -ENOMEM;
  144. /* Try each phase and extract good ranges */
  145. for (i = 0; i < priv->num_phases; ) {
  146. clk_set_phase(priv->sample_clk,
  147. TUNING_ITERATION_TO_PHASE(i, priv->num_phases));
  148. v = !mmc_send_tuning(mmc, opcode, NULL);
  149. if (i == 0)
  150. first_v = v;
  151. if ((!prev_v) && v) {
  152. range_count++;
  153. ranges[range_count-1].start = i;
  154. }
  155. if (v) {
  156. ranges[range_count-1].end = i;
  157. i++;
  158. } else if (i == priv->num_phases - 1) {
  159. /* No extra skipping rules if we're at the end */
  160. i++;
  161. } else {
  162. /*
  163. * No need to check too close to an invalid
  164. * one since testing bad phases is slow. Skip
  165. * 20 degrees.
  166. */
  167. i += DIV_ROUND_UP(20 * priv->num_phases, 360);
  168. /* Always test the last one */
  169. if (i >= priv->num_phases)
  170. i = priv->num_phases - 1;
  171. }
  172. prev_v = v;
  173. }
  174. if (range_count == 0) {
  175. dev_warn(host->dev, "All phases bad!");
  176. ret = -EIO;
  177. goto free;
  178. }
  179. /* wrap around case, merge the end points */
  180. if ((range_count > 1) && first_v && v) {
  181. ranges[0].start = ranges[range_count-1].start;
  182. range_count--;
  183. }
  184. if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) {
  185. clk_set_phase(priv->sample_clk, priv->default_sample_phase);
  186. dev_info(host->dev, "All phases work, using default phase %d.",
  187. priv->default_sample_phase);
  188. goto free;
  189. }
  190. /* Find the longest range */
  191. for (i = 0; i < range_count; i++) {
  192. int len = (ranges[i].end - ranges[i].start + 1);
  193. if (len < 0)
  194. len += priv->num_phases;
  195. if (longest_range_len < len) {
  196. longest_range_len = len;
  197. longest_range = i;
  198. }
  199. dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
  200. TUNING_ITERATION_TO_PHASE(ranges[i].start,
  201. priv->num_phases),
  202. TUNING_ITERATION_TO_PHASE(ranges[i].end,
  203. priv->num_phases),
  204. len
  205. );
  206. }
  207. dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
  208. TUNING_ITERATION_TO_PHASE(ranges[longest_range].start,
  209. priv->num_phases),
  210. TUNING_ITERATION_TO_PHASE(ranges[longest_range].end,
  211. priv->num_phases),
  212. longest_range_len
  213. );
  214. middle_phase = ranges[longest_range].start + longest_range_len / 2;
  215. middle_phase %= priv->num_phases;
  216. dev_info(host->dev, "Successfully tuned phase to %d\n",
  217. TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases));
  218. clk_set_phase(priv->sample_clk,
  219. TUNING_ITERATION_TO_PHASE(middle_phase,
  220. priv->num_phases));
  221. free:
  222. kfree(ranges);
  223. return ret;
  224. }
  225. static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
  226. {
  227. struct device_node *np = host->dev->of_node;
  228. struct dw_mci_rockchip_priv_data *priv;
  229. priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
  230. if (!priv)
  231. return -ENOMEM;
  232. if (of_property_read_u32(np, "rockchip,desired-num-phases",
  233. &priv->num_phases))
  234. priv->num_phases = 360;
  235. if (of_property_read_u32(np, "rockchip,default-sample-phase",
  236. &priv->default_sample_phase))
  237. priv->default_sample_phase = 0;
  238. priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
  239. if (IS_ERR(priv->drv_clk))
  240. dev_dbg(host->dev, "ciu-drive not available\n");
  241. priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
  242. if (IS_ERR(priv->sample_clk))
  243. dev_dbg(host->dev, "ciu-sample not available\n");
  244. host->priv = priv;
  245. return 0;
  246. }
  247. static int dw_mci_rockchip_init(struct dw_mci *host)
  248. {
  249. /* It is slot 8 on Rockchip SoCs */
  250. host->sdio_id0 = 8;
  251. if (of_device_is_compatible(host->dev->of_node,
  252. "rockchip,rk3288-dw-mshc"))
  253. host->bus_hz /= RK3288_CLKGEN_DIV;
  254. return 0;
  255. }
  256. /* Common capabilities of RK3288 SoC */
  257. static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
  258. MMC_CAP_CMD23,
  259. MMC_CAP_CMD23,
  260. MMC_CAP_CMD23,
  261. MMC_CAP_CMD23,
  262. };
  263. static const struct dw_mci_drv_data rk2928_drv_data = {
  264. .init = dw_mci_rockchip_init,
  265. };
  266. static const struct dw_mci_drv_data rk3288_drv_data = {
  267. .caps = dw_mci_rk3288_dwmmc_caps,
  268. .num_caps = ARRAY_SIZE(dw_mci_rk3288_dwmmc_caps),
  269. .set_ios = dw_mci_rk3288_set_ios,
  270. .execute_tuning = dw_mci_rk3288_execute_tuning,
  271. .parse_dt = dw_mci_rk3288_parse_dt,
  272. .init = dw_mci_rockchip_init,
  273. };
  274. static const struct of_device_id dw_mci_rockchip_match[] = {
  275. { .compatible = "rockchip,rk2928-dw-mshc",
  276. .data = &rk2928_drv_data },
  277. { .compatible = "rockchip,rk3288-dw-mshc",
  278. .data = &rk3288_drv_data },
  279. {},
  280. };
  281. MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
  282. static int dw_mci_rockchip_probe(struct platform_device *pdev)
  283. {
  284. const struct dw_mci_drv_data *drv_data;
  285. const struct of_device_id *match;
  286. int ret;
  287. if (!pdev->dev.of_node)
  288. return -ENODEV;
  289. match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
  290. drv_data = match->data;
  291. pm_runtime_get_noresume(&pdev->dev);
  292. pm_runtime_set_active(&pdev->dev);
  293. pm_runtime_enable(&pdev->dev);
  294. pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
  295. pm_runtime_use_autosuspend(&pdev->dev);
  296. ret = dw_mci_pltfm_register(pdev, drv_data);
  297. if (ret) {
  298. pm_runtime_disable(&pdev->dev);
  299. pm_runtime_set_suspended(&pdev->dev);
  300. pm_runtime_put_noidle(&pdev->dev);
  301. return ret;
  302. }
  303. pm_runtime_put_autosuspend(&pdev->dev);
  304. return 0;
  305. }
  306. static int dw_mci_rockchip_remove(struct platform_device *pdev)
  307. {
  308. pm_runtime_get_sync(&pdev->dev);
  309. pm_runtime_disable(&pdev->dev);
  310. pm_runtime_put_noidle(&pdev->dev);
  311. return dw_mci_pltfm_remove(pdev);
  312. }
  313. static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
  314. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  315. pm_runtime_force_resume)
  316. SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
  317. dw_mci_runtime_resume,
  318. NULL)
  319. };
  320. static struct platform_driver dw_mci_rockchip_pltfm_driver = {
  321. .probe = dw_mci_rockchip_probe,
  322. .remove = dw_mci_rockchip_remove,
  323. .driver = {
  324. .name = "dwmmc_rockchip",
  325. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  326. .of_match_table = dw_mci_rockchip_match,
  327. .pm = &dw_mci_rockchip_dev_pm_ops,
  328. },
  329. };
  330. module_platform_driver(dw_mci_rockchip_pltfm_driver);
  331. MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
  332. MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
  333. MODULE_ALIAS("platform:dwmmc_rockchip");
  334. MODULE_LICENSE("GPL v2");