dw_mmc-exynos.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
  4. *
  5. * Copyright (C) 2012, Samsung Electronics Co., Ltd.
  6. */
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/clk.h>
  10. #include <linux/mmc/host.h>
  11. #include <linux/mmc/mmc.h>
  12. #include <linux/of.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/slab.h>
  16. #include "dw_mmc.h"
  17. #include "dw_mmc-pltfm.h"
  18. #include "dw_mmc-exynos.h"
  19. /* Variations in Exynos specific dw-mshc controller */
  20. enum dw_mci_exynos_type {
  21. DW_MCI_TYPE_EXYNOS4210,
  22. DW_MCI_TYPE_EXYNOS4412,
  23. DW_MCI_TYPE_EXYNOS5250,
  24. DW_MCI_TYPE_EXYNOS5420,
  25. DW_MCI_TYPE_EXYNOS5420_SMU,
  26. DW_MCI_TYPE_EXYNOS7,
  27. DW_MCI_TYPE_EXYNOS7_SMU,
  28. };
  29. /* Exynos implementation specific driver private data */
  30. struct dw_mci_exynos_priv_data {
  31. enum dw_mci_exynos_type ctrl_type;
  32. u8 ciu_div;
  33. u32 sdr_timing;
  34. u32 ddr_timing;
  35. u32 hs400_timing;
  36. u32 tuned_sample;
  37. u32 cur_speed;
  38. u32 dqs_delay;
  39. u32 saved_dqs_en;
  40. u32 saved_strobe_ctrl;
  41. };
  42. static struct dw_mci_exynos_compatible {
  43. char *compatible;
  44. enum dw_mci_exynos_type ctrl_type;
  45. } exynos_compat[] = {
  46. {
  47. .compatible = "samsung,exynos4210-dw-mshc",
  48. .ctrl_type = DW_MCI_TYPE_EXYNOS4210,
  49. }, {
  50. .compatible = "samsung,exynos4412-dw-mshc",
  51. .ctrl_type = DW_MCI_TYPE_EXYNOS4412,
  52. }, {
  53. .compatible = "samsung,exynos5250-dw-mshc",
  54. .ctrl_type = DW_MCI_TYPE_EXYNOS5250,
  55. }, {
  56. .compatible = "samsung,exynos5420-dw-mshc",
  57. .ctrl_type = DW_MCI_TYPE_EXYNOS5420,
  58. }, {
  59. .compatible = "samsung,exynos5420-dw-mshc-smu",
  60. .ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
  61. }, {
  62. .compatible = "samsung,exynos7-dw-mshc",
  63. .ctrl_type = DW_MCI_TYPE_EXYNOS7,
  64. }, {
  65. .compatible = "samsung,exynos7-dw-mshc-smu",
  66. .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
  67. },
  68. };
  69. static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
  70. {
  71. struct dw_mci_exynos_priv_data *priv = host->priv;
  72. if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
  73. return EXYNOS4412_FIXED_CIU_CLK_DIV;
  74. else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
  75. return EXYNOS4210_FIXED_CIU_CLK_DIV;
  76. else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
  77. priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
  78. return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
  79. else
  80. return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
  81. }
  82. static void dw_mci_exynos_config_smu(struct dw_mci *host)
  83. {
  84. struct dw_mci_exynos_priv_data *priv = host->priv;
  85. /*
  86. * If Exynos is provided the Security management,
  87. * set for non-ecryption mode at this time.
  88. */
  89. if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
  90. priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
  91. mci_writel(host, MPSBEGIN0, 0);
  92. mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
  93. mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
  94. SDMMC_MPSCTRL_NON_SECURE_READ_BIT |
  95. SDMMC_MPSCTRL_VALID |
  96. SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
  97. }
  98. }
  99. static int dw_mci_exynos_priv_init(struct dw_mci *host)
  100. {
  101. struct dw_mci_exynos_priv_data *priv = host->priv;
  102. dw_mci_exynos_config_smu(host);
  103. if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) {
  104. priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
  105. priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
  106. priv->saved_dqs_en |= AXI_NON_BLOCKING_WR;
  107. mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
  108. if (!priv->dqs_delay)
  109. priv->dqs_delay =
  110. DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
  111. }
  112. host->bus_hz /= (priv->ciu_div + 1);
  113. return 0;
  114. }
  115. static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
  116. {
  117. struct dw_mci_exynos_priv_data *priv = host->priv;
  118. u32 clksel;
  119. if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
  120. priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
  121. clksel = mci_readl(host, CLKSEL64);
  122. else
  123. clksel = mci_readl(host, CLKSEL);
  124. clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;
  125. if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
  126. priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
  127. mci_writel(host, CLKSEL64, clksel);
  128. else
  129. mci_writel(host, CLKSEL, clksel);
  130. /*
  131. * Exynos4412 and Exynos5250 extends the use of CMD register with the
  132. * use of bit 29 (which is reserved on standard MSHC controllers) for
  133. * optionally bypassing the HOLD register for command and data. The
  134. * HOLD register should be bypassed in case there is no phase shift
  135. * applied on CMD/DATA that is sent to the card.
  136. */
  137. if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot)
  138. set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags);
  139. }
  140. #ifdef CONFIG_PM
  141. static int dw_mci_exynos_runtime_resume(struct device *dev)
  142. {
  143. struct dw_mci *host = dev_get_drvdata(dev);
  144. int ret;
  145. ret = dw_mci_runtime_resume(dev);
  146. if (ret)
  147. return ret;
  148. dw_mci_exynos_config_smu(host);
  149. return ret;
  150. }
  151. #endif /* CONFIG_PM */
  152. #ifdef CONFIG_PM_SLEEP
  153. /**
  154. * dw_mci_exynos_suspend_noirq - Exynos-specific suspend code
  155. * @dev: Device to suspend (this device)
  156. *
  157. * This ensures that device will be in runtime active state in
  158. * dw_mci_exynos_resume_noirq after calling pm_runtime_force_resume()
  159. */
  160. static int dw_mci_exynos_suspend_noirq(struct device *dev)
  161. {
  162. pm_runtime_get_noresume(dev);
  163. return pm_runtime_force_suspend(dev);
  164. }
  165. /**
  166. * dw_mci_exynos_resume_noirq - Exynos-specific resume code
  167. * @dev: Device to resume (this device)
  168. *
  169. * On exynos5420 there is a silicon errata that will sometimes leave the
  170. * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
  171. * that it fired and we can clear it by writing a 1 back. Clear it to prevent
  172. * interrupts from going off constantly.
  173. *
  174. * We run this code on all exynos variants because it doesn't hurt.
  175. */
  176. static int dw_mci_exynos_resume_noirq(struct device *dev)
  177. {
  178. struct dw_mci *host = dev_get_drvdata(dev);
  179. struct dw_mci_exynos_priv_data *priv = host->priv;
  180. u32 clksel;
  181. int ret;
  182. ret = pm_runtime_force_resume(dev);
  183. if (ret)
  184. return ret;
  185. if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
  186. priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
  187. clksel = mci_readl(host, CLKSEL64);
  188. else
  189. clksel = mci_readl(host, CLKSEL);
  190. if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
  191. if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
  192. priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
  193. mci_writel(host, CLKSEL64, clksel);
  194. else
  195. mci_writel(host, CLKSEL, clksel);
  196. }
  197. pm_runtime_put(dev);
  198. return 0;
  199. }
  200. #endif /* CONFIG_PM_SLEEP */
  201. static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
  202. {
  203. struct dw_mci_exynos_priv_data *priv = host->priv;
  204. u32 dqs, strobe;
  205. /*
  206. * Not supported to configure register
  207. * related to HS400
  208. */
  209. if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) {
  210. if (timing == MMC_TIMING_MMC_HS400)
  211. dev_warn(host->dev,
  212. "cannot configure HS400, unsupported chipset\n");
  213. return;
  214. }
  215. dqs = priv->saved_dqs_en;
  216. strobe = priv->saved_strobe_ctrl;
  217. if (timing == MMC_TIMING_MMC_HS400) {
  218. dqs |= DATA_STROBE_EN;
  219. strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
  220. } else if (timing == MMC_TIMING_UHS_SDR104) {
  221. dqs &= 0xffffff00;
  222. } else {
  223. dqs &= ~DATA_STROBE_EN;
  224. }
  225. mci_writel(host, HS400_DQS_EN, dqs);
  226. mci_writel(host, HS400_DLINE_CTRL, strobe);
  227. }
  228. static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted)
  229. {
  230. struct dw_mci_exynos_priv_data *priv = host->priv;
  231. unsigned long actual;
  232. u8 div;
  233. int ret;
  234. /*
  235. * Don't care if wanted clock is zero or
  236. * ciu clock is unavailable
  237. */
  238. if (!wanted || IS_ERR(host->ciu_clk))
  239. return;
  240. /* Guaranteed minimum frequency for cclkin */
  241. if (wanted < EXYNOS_CCLKIN_MIN)
  242. wanted = EXYNOS_CCLKIN_MIN;
  243. if (wanted == priv->cur_speed)
  244. return;
  245. div = dw_mci_exynos_get_ciu_div(host);
  246. ret = clk_set_rate(host->ciu_clk, wanted * div);
  247. if (ret)
  248. dev_warn(host->dev,
  249. "failed to set clk-rate %u error: %d\n",
  250. wanted * div, ret);
  251. actual = clk_get_rate(host->ciu_clk);
  252. host->bus_hz = actual / div;
  253. priv->cur_speed = wanted;
  254. host->current_speed = 0;
  255. }
  256. static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
  257. {
  258. struct dw_mci_exynos_priv_data *priv = host->priv;
  259. unsigned int wanted = ios->clock;
  260. u32 timing = ios->timing, clksel;
  261. switch (timing) {
  262. case MMC_TIMING_MMC_HS400:
  263. /* Update tuned sample timing */
  264. clksel = SDMMC_CLKSEL_UP_SAMPLE(
  265. priv->hs400_timing, priv->tuned_sample);
  266. wanted <<= 1;
  267. break;
  268. case MMC_TIMING_MMC_DDR52:
  269. clksel = priv->ddr_timing;
  270. /* Should be double rate for DDR mode */
  271. if (ios->bus_width == MMC_BUS_WIDTH_8)
  272. wanted <<= 1;
  273. break;
  274. case MMC_TIMING_UHS_SDR104:
  275. case MMC_TIMING_UHS_SDR50:
  276. clksel = (priv->sdr_timing & 0xfff8ffff) |
  277. (priv->ciu_div << 16);
  278. break;
  279. case MMC_TIMING_UHS_DDR50:
  280. clksel = (priv->ddr_timing & 0xfff8ffff) |
  281. (priv->ciu_div << 16);
  282. break;
  283. default:
  284. clksel = priv->sdr_timing;
  285. }
  286. /* Set clock timing for the requested speed mode*/
  287. dw_mci_exynos_set_clksel_timing(host, clksel);
  288. /* Configure setting for HS400 */
  289. dw_mci_exynos_config_hs400(host, timing);
  290. /* Configure clock rate */
  291. dw_mci_exynos_adjust_clock(host, wanted);
  292. }
  293. static int dw_mci_exynos_parse_dt(struct dw_mci *host)
  294. {
  295. struct dw_mci_exynos_priv_data *priv;
  296. struct device_node *np = host->dev->of_node;
  297. u32 timing[2];
  298. u32 div = 0;
  299. int idx;
  300. int ret;
  301. priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
  302. if (!priv)
  303. return -ENOMEM;
  304. for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
  305. if (of_device_is_compatible(np, exynos_compat[idx].compatible))
  306. priv->ctrl_type = exynos_compat[idx].ctrl_type;
  307. }
  308. if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
  309. priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
  310. else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
  311. priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
  312. else {
  313. of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
  314. priv->ciu_div = div;
  315. }
  316. ret = of_property_read_u32_array(np,
  317. "samsung,dw-mshc-sdr-timing", timing, 2);
  318. if (ret)
  319. return ret;
  320. priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
  321. ret = of_property_read_u32_array(np,
  322. "samsung,dw-mshc-ddr-timing", timing, 2);
  323. if (ret)
  324. return ret;
  325. priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
  326. ret = of_property_read_u32_array(np,
  327. "samsung,dw-mshc-hs400-timing", timing, 2);
  328. if (!ret && of_property_read_u32(np,
  329. "samsung,read-strobe-delay", &priv->dqs_delay))
  330. dev_dbg(host->dev,
  331. "read-strobe-delay is not found, assuming usage of default value\n");
  332. priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
  333. HS400_FIXED_CIU_CLK_DIV);
  334. host->priv = priv;
  335. return 0;
  336. }
  337. static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
  338. {
  339. struct dw_mci_exynos_priv_data *priv = host->priv;
  340. if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
  341. priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
  342. return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
  343. else
  344. return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
  345. }
  346. static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
  347. {
  348. u32 clksel;
  349. struct dw_mci_exynos_priv_data *priv = host->priv;
  350. if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
  351. priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
  352. clksel = mci_readl(host, CLKSEL64);
  353. else
  354. clksel = mci_readl(host, CLKSEL);
  355. clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
  356. if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
  357. priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
  358. mci_writel(host, CLKSEL64, clksel);
  359. else
  360. mci_writel(host, CLKSEL, clksel);
  361. }
  362. static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
  363. {
  364. struct dw_mci_exynos_priv_data *priv = host->priv;
  365. u32 clksel;
  366. u8 sample;
  367. if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
  368. priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
  369. clksel = mci_readl(host, CLKSEL64);
  370. else
  371. clksel = mci_readl(host, CLKSEL);
  372. sample = (clksel + 1) & 0x7;
  373. clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
  374. if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
  375. priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
  376. mci_writel(host, CLKSEL64, clksel);
  377. else
  378. mci_writel(host, CLKSEL, clksel);
  379. return sample;
  380. }
  381. static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
  382. {
  383. const u8 iter = 8;
  384. u8 __c;
  385. s8 i, loc = -1;
  386. for (i = 0; i < iter; i++) {
  387. __c = ror8(candiates, i);
  388. if ((__c & 0xc7) == 0xc7) {
  389. loc = i;
  390. goto out;
  391. }
  392. }
  393. for (i = 0; i < iter; i++) {
  394. __c = ror8(candiates, i);
  395. if ((__c & 0x83) == 0x83) {
  396. loc = i;
  397. goto out;
  398. }
  399. }
  400. /*
  401. * If there is no cadiates value, then it needs to return -EIO.
  402. * If there are candiates values and don't find bset clk sample value,
  403. * then use a first candiates clock sample value.
  404. */
  405. for (i = 0; i < iter; i++) {
  406. __c = ror8(candiates, i);
  407. if ((__c & 0x1) == 0x1) {
  408. loc = i;
  409. goto out;
  410. }
  411. }
  412. out:
  413. return loc;
  414. }
  415. static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
  416. {
  417. struct dw_mci *host = slot->host;
  418. struct dw_mci_exynos_priv_data *priv = host->priv;
  419. struct mmc_host *mmc = slot->mmc;
  420. u8 start_smpl, smpl, candiates = 0;
  421. s8 found;
  422. int ret = 0;
  423. start_smpl = dw_mci_exynos_get_clksmpl(host);
  424. do {
  425. mci_writel(host, TMOUT, ~0);
  426. smpl = dw_mci_exynos_move_next_clksmpl(host);
  427. if (!mmc_send_tuning(mmc, opcode, NULL))
  428. candiates |= (1 << smpl);
  429. } while (start_smpl != smpl);
  430. found = dw_mci_exynos_get_best_clksmpl(candiates);
  431. if (found >= 0) {
  432. dw_mci_exynos_set_clksmpl(host, found);
  433. priv->tuned_sample = found;
  434. } else {
  435. ret = -EIO;
  436. dev_warn(&mmc->class_dev,
  437. "There is no candiates value about clksmpl!\n");
  438. }
  439. return ret;
  440. }
  441. static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
  442. struct mmc_ios *ios)
  443. {
  444. struct dw_mci_exynos_priv_data *priv = host->priv;
  445. dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing);
  446. dw_mci_exynos_adjust_clock(host, (ios->clock) << 1);
  447. return 0;
  448. }
  449. /* Common capabilities of Exynos4/Exynos5 SoC */
  450. static unsigned long exynos_dwmmc_caps[4] = {
  451. MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
  452. MMC_CAP_CMD23,
  453. MMC_CAP_CMD23,
  454. MMC_CAP_CMD23,
  455. };
  456. static const struct dw_mci_drv_data exynos_drv_data = {
  457. .caps = exynos_dwmmc_caps,
  458. .num_caps = ARRAY_SIZE(exynos_dwmmc_caps),
  459. .init = dw_mci_exynos_priv_init,
  460. .set_ios = dw_mci_exynos_set_ios,
  461. .parse_dt = dw_mci_exynos_parse_dt,
  462. .execute_tuning = dw_mci_exynos_execute_tuning,
  463. .prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning,
  464. };
  465. static const struct of_device_id dw_mci_exynos_match[] = {
  466. { .compatible = "samsung,exynos4412-dw-mshc",
  467. .data = &exynos_drv_data, },
  468. { .compatible = "samsung,exynos5250-dw-mshc",
  469. .data = &exynos_drv_data, },
  470. { .compatible = "samsung,exynos5420-dw-mshc",
  471. .data = &exynos_drv_data, },
  472. { .compatible = "samsung,exynos5420-dw-mshc-smu",
  473. .data = &exynos_drv_data, },
  474. { .compatible = "samsung,exynos7-dw-mshc",
  475. .data = &exynos_drv_data, },
  476. { .compatible = "samsung,exynos7-dw-mshc-smu",
  477. .data = &exynos_drv_data, },
  478. {},
  479. };
  480. MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
  481. static int dw_mci_exynos_probe(struct platform_device *pdev)
  482. {
  483. const struct dw_mci_drv_data *drv_data;
  484. const struct of_device_id *match;
  485. int ret;
  486. match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
  487. drv_data = match->data;
  488. pm_runtime_get_noresume(&pdev->dev);
  489. pm_runtime_set_active(&pdev->dev);
  490. pm_runtime_enable(&pdev->dev);
  491. ret = dw_mci_pltfm_register(pdev, drv_data);
  492. if (ret) {
  493. pm_runtime_disable(&pdev->dev);
  494. pm_runtime_set_suspended(&pdev->dev);
  495. pm_runtime_put_noidle(&pdev->dev);
  496. return ret;
  497. }
  498. return 0;
  499. }
  500. static int dw_mci_exynos_remove(struct platform_device *pdev)
  501. {
  502. pm_runtime_disable(&pdev->dev);
  503. pm_runtime_set_suspended(&pdev->dev);
  504. pm_runtime_put_noidle(&pdev->dev);
  505. return dw_mci_pltfm_remove(pdev);
  506. }
  507. static const struct dev_pm_ops dw_mci_exynos_pmops = {
  508. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend_noirq,
  509. dw_mci_exynos_resume_noirq)
  510. SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
  511. dw_mci_exynos_runtime_resume,
  512. NULL)
  513. };
  514. static struct platform_driver dw_mci_exynos_pltfm_driver = {
  515. .probe = dw_mci_exynos_probe,
  516. .remove = dw_mci_exynos_remove,
  517. .driver = {
  518. .name = "dwmmc_exynos",
  519. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  520. .of_match_table = dw_mci_exynos_match,
  521. .pm = &dw_mci_exynos_pmops,
  522. },
  523. };
  524. module_platform_driver(dw_mci_exynos_pltfm_driver);
  525. MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
  526. MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
  527. MODULE_LICENSE("GPL v2");
  528. MODULE_ALIAS("platform:dwmmc_exynos");