cqhci.h 8.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
  3. */
  4. #ifndef LINUX_MMC_CQHCI_H
  5. #define LINUX_MMC_CQHCI_H
  6. #include <linux/compiler.h>
  7. #include <linux/bitops.h>
  8. #include <linux/spinlock_types.h>
  9. #include <linux/types.h>
  10. #include <linux/completion.h>
  11. #include <linux/wait.h>
  12. #include <linux/irqreturn.h>
  13. #include <asm/io.h>
  14. /* registers */
  15. /* version */
  16. #define CQHCI_VER 0x00
  17. #define CQHCI_VER_MAJOR(x) (((x) & GENMASK(11, 8)) >> 8)
  18. #define CQHCI_VER_MINOR1(x) (((x) & GENMASK(7, 4)) >> 4)
  19. #define CQHCI_VER_MINOR2(x) ((x) & GENMASK(3, 0))
  20. /* capabilities */
  21. #define CQHCI_CAP 0x04
  22. #define CQHCI_CAP_CS 0x10000000 /* Crypto Support */
  23. /* configuration */
  24. #define CQHCI_CFG 0x08
  25. #define CQHCI_DCMD 0x00001000
  26. #define CQHCI_TASK_DESC_SZ 0x00000100
  27. #define CQHCI_CRYPTO_GENERAL_ENABLE 0x00000002
  28. #define CQHCI_ENABLE 0x00000001
  29. /* control */
  30. #define CQHCI_CTL 0x0C
  31. #define CQHCI_CLEAR_ALL_TASKS 0x00000100
  32. #define CQHCI_HALT 0x00000001
  33. /* interrupt status */
  34. #define CQHCI_IS 0x10
  35. #define CQHCI_IS_HAC BIT(0)
  36. #define CQHCI_IS_TCC BIT(1)
  37. #define CQHCI_IS_RED BIT(2)
  38. #define CQHCI_IS_TCL BIT(3)
  39. #define CQHCI_IS_GCE BIT(4) /* General Crypto Error */
  40. #define CQHCI_IS_ICCE BIT(5) /* Invalid Crypto Config Error */
  41. #define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED | \
  42. CQHCI_IS_GCE | CQHCI_IS_ICCE)
  43. /* interrupt status enable */
  44. #define CQHCI_ISTE 0x14
  45. /* interrupt signal enable */
  46. #define CQHCI_ISGE 0x18
  47. /* interrupt coalescing */
  48. #define CQHCI_IC 0x1C
  49. #define CQHCI_IC_ENABLE BIT(31)
  50. #define CQHCI_IC_RESET BIT(16)
  51. #define CQHCI_IC_ICCTHWEN BIT(15)
  52. #define CQHCI_IC_ICCTH(x) (((x) & 0x1F) << 8)
  53. #define CQHCI_IC_ICTOVALWEN BIT(7)
  54. #define CQHCI_IC_ICTOVAL(x) ((x) & 0x7F)
  55. /* task list base address */
  56. #define CQHCI_TDLBA 0x20
  57. /* task list base address upper */
  58. #define CQHCI_TDLBAU 0x24
  59. /* door-bell */
  60. #define CQHCI_TDBR 0x28
  61. /* task completion notification */
  62. #define CQHCI_TCN 0x2C
  63. /* device queue status */
  64. #define CQHCI_DQS 0x30
  65. /* device pending tasks */
  66. #define CQHCI_DPT 0x34
  67. /* task clear */
  68. #define CQHCI_TCLR 0x38
  69. /* task descriptor processing error */
  70. #define CQHCI_TDPE 0x3c
  71. /* send status config 1 */
  72. #define CQHCI_SSC1 0x40
  73. #define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)
  74. /* send status config 2 */
  75. #define CQHCI_SSC2 0x44
  76. /* response for dcmd */
  77. #define CQHCI_CRDCT 0x48
  78. /* response mode error mask */
  79. #define CQHCI_RMEM 0x50
  80. /* task error info */
  81. #define CQHCI_TERRI 0x54
  82. #define CQHCI_TERRI_C_INDEX(x) ((x) & GENMASK(5, 0))
  83. #define CQHCI_TERRI_C_TASK(x) (((x) & GENMASK(12, 8)) >> 8)
  84. #define CQHCI_TERRI_C_VALID(x) ((x) & BIT(15))
  85. #define CQHCI_TERRI_D_INDEX(x) (((x) & GENMASK(21, 16)) >> 16)
  86. #define CQHCI_TERRI_D_TASK(x) (((x) & GENMASK(28, 24)) >> 24)
  87. #define CQHCI_TERRI_D_VALID(x) ((x) & BIT(31))
  88. /* command response index */
  89. #define CQHCI_CRI 0x58
  90. /* command response argument */
  91. #define CQHCI_CRA 0x5C
  92. /* crypto capabilities */
  93. #define CQHCI_CCAP 0x100
  94. #define CQHCI_CRYPTOCAP 0x104
  95. #define CQHCI_INT_ALL 0xF
  96. #define CQHCI_IC_DEFAULT_ICCTH 31
  97. #define CQHCI_IC_DEFAULT_ICTOVAL 1
  98. /* attribute fields */
  99. #define CQHCI_VALID(x) (((x) & 1) << 0)
  100. #define CQHCI_END(x) (((x) & 1) << 1)
  101. #define CQHCI_INT(x) (((x) & 1) << 2)
  102. #define CQHCI_ACT(x) (((x) & 0x7) << 3)
  103. /* data command task descriptor fields */
  104. #define CQHCI_FORCED_PROG(x) (((x) & 1) << 6)
  105. #define CQHCI_CONTEXT(x) (((x) & 0xF) << 7)
  106. #define CQHCI_DATA_TAG(x) (((x) & 1) << 11)
  107. #define CQHCI_DATA_DIR(x) (((x) & 1) << 12)
  108. #define CQHCI_PRIORITY(x) (((x) & 1) << 13)
  109. #define CQHCI_QBAR(x) (((x) & 1) << 14)
  110. #define CQHCI_REL_WRITE(x) (((x) & 1) << 15)
  111. #define CQHCI_BLK_COUNT(x) (((x) & 0xFFFF) << 16)
  112. #define CQHCI_BLK_ADDR(x) (((x) & 0xFFFFFFFF) << 32)
  113. /* direct command task descriptor fields */
  114. #define CQHCI_CMD_INDEX(x) (((x) & 0x3F) << 16)
  115. #define CQHCI_CMD_TIMING(x) (((x) & 1) << 22)
  116. #define CQHCI_RESP_TYPE(x) (((x) & 0x3) << 23)
  117. /* crypto task descriptor fields (for bits 64-127 of task descriptor) */
  118. #define CQHCI_CRYPTO_ENABLE_BIT (1ULL << 47)
  119. #define CQHCI_CRYPTO_KEYSLOT(x) ((u64)(x) << 32)
  120. /* transfer descriptor fields */
  121. #define CQHCI_DAT_LENGTH(x) (((x) & 0xFFFF) << 16)
  122. #define CQHCI_DAT_ADDR_LO(x) (((x) & 0xFFFFFFFF) << 32)
  123. #define CQHCI_DAT_ADDR_HI(x) (((x) & 0xFFFFFFFF) << 0)
  124. /* CCAP - Crypto Capability 100h */
  125. union cqhci_crypto_capabilities {
  126. __le32 reg_val;
  127. struct {
  128. u8 num_crypto_cap;
  129. u8 config_count;
  130. u8 reserved;
  131. u8 config_array_ptr;
  132. };
  133. };
  134. enum cqhci_crypto_key_size {
  135. CQHCI_CRYPTO_KEY_SIZE_INVALID = 0,
  136. CQHCI_CRYPTO_KEY_SIZE_128 = 1,
  137. CQHCI_CRYPTO_KEY_SIZE_192 = 2,
  138. CQHCI_CRYPTO_KEY_SIZE_256 = 3,
  139. CQHCI_CRYPTO_KEY_SIZE_512 = 4,
  140. };
  141. enum cqhci_crypto_alg {
  142. CQHCI_CRYPTO_ALG_AES_XTS = 0,
  143. CQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC = 1,
  144. CQHCI_CRYPTO_ALG_AES_ECB = 2,
  145. CQHCI_CRYPTO_ALG_ESSIV_AES_CBC = 3,
  146. };
  147. /* x-CRYPTOCAP - Crypto Capability X */
  148. union cqhci_crypto_cap_entry {
  149. __le32 reg_val;
  150. struct {
  151. u8 algorithm_id;
  152. u8 sdus_mask; /* Supported data unit size mask */
  153. u8 key_size;
  154. u8 reserved;
  155. };
  156. };
  157. #define CQHCI_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
  158. #define CQHCI_CRYPTO_KEY_MAX_SIZE 64
  159. /* x-CRYPTOCFG - Crypto Configuration X */
  160. union cqhci_crypto_cfg_entry {
  161. __le32 reg_val[32];
  162. struct {
  163. u8 crypto_key[CQHCI_CRYPTO_KEY_MAX_SIZE];
  164. u8 data_unit_size;
  165. u8 crypto_cap_idx;
  166. u8 reserved_1;
  167. u8 config_enable;
  168. u8 reserved_multi_host;
  169. u8 reserved_2;
  170. u8 vsb[2];
  171. u8 reserved_3[56];
  172. };
  173. };
  174. struct cqhci_host_ops;
  175. struct mmc_host;
  176. struct mmc_request;
  177. struct cqhci_slot;
  178. struct cqhci_host {
  179. const struct cqhci_host_ops *ops;
  180. void __iomem *mmio;
  181. struct mmc_host *mmc;
  182. spinlock_t lock;
  183. /* relative card address of device */
  184. unsigned int rca;
  185. /* 64 bit DMA */
  186. bool dma64;
  187. int num_slots;
  188. int qcnt;
  189. u32 dcmd_slot;
  190. u32 caps;
  191. #define CQHCI_TASK_DESC_SZ_128 0x1
  192. u32 quirks;
  193. #define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1
  194. bool enabled;
  195. bool halted;
  196. bool init_done;
  197. bool activated;
  198. bool waiting_for_idle;
  199. bool recovery_halt;
  200. size_t desc_size;
  201. size_t data_size;
  202. u8 *desc_base;
  203. /* total descriptor size */
  204. u8 slot_sz;
  205. /* 64/128 bit depends on CQHCI_CFG */
  206. u8 task_desc_len;
  207. /* 64 bit on 32-bit arch, 128 bit on 64-bit */
  208. u8 link_desc_len;
  209. u8 *trans_desc_base;
  210. /* same length as transfer descriptor */
  211. u8 trans_desc_len;
  212. dma_addr_t desc_dma_base;
  213. dma_addr_t trans_desc_dma_base;
  214. struct completion halt_comp;
  215. wait_queue_head_t wait_queue;
  216. struct cqhci_slot *slot;
  217. #ifdef CONFIG_MMC_CRYPTO
  218. union cqhci_crypto_capabilities crypto_capabilities;
  219. union cqhci_crypto_cap_entry *crypto_cap_array;
  220. u32 crypto_cfg_register;
  221. #endif
  222. };
  223. struct cqhci_host_ops {
  224. void (*dumpregs)(struct mmc_host *mmc);
  225. void (*write_l)(struct cqhci_host *host, u32 val, int reg);
  226. u32 (*read_l)(struct cqhci_host *host, int reg);
  227. void (*enable)(struct mmc_host *mmc);
  228. void (*disable)(struct mmc_host *mmc, bool recovery);
  229. void (*update_dcmd_desc)(struct mmc_host *mmc, struct mmc_request *mrq,
  230. u64 *data);
  231. void (*pre_enable)(struct mmc_host *mmc);
  232. void (*post_disable)(struct mmc_host *mmc);
  233. #ifdef CONFIG_MMC_CRYPTO
  234. int (*program_key)(struct cqhci_host *cq_host,
  235. const union cqhci_crypto_cfg_entry *cfg, int slot);
  236. #endif
  237. };
  238. static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
  239. {
  240. if (unlikely(host->ops->write_l))
  241. host->ops->write_l(host, val, reg);
  242. else
  243. writel_relaxed(val, host->mmio + reg);
  244. }
  245. static inline u32 cqhci_readl(struct cqhci_host *host, int reg)
  246. {
  247. if (unlikely(host->ops->read_l))
  248. return host->ops->read_l(host, reg);
  249. else
  250. return readl_relaxed(host->mmio + reg);
  251. }
  252. struct platform_device;
  253. irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
  254. int data_error);
  255. int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
  256. struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev);
  257. int cqhci_deactivate(struct mmc_host *mmc);
  258. static inline int cqhci_suspend(struct mmc_host *mmc)
  259. {
  260. return cqhci_deactivate(mmc);
  261. }
  262. int cqhci_resume(struct mmc_host *mmc);
  263. #endif