cqhci-crypto.c 7.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * CQHCI crypto engine (inline encryption) support
  4. *
  5. * Copyright 2020 Google LLC
  6. */
  7. #include <linux/blk-crypto.h>
  8. #include <linux/keyslot-manager.h>
  9. #include <linux/mmc/host.h>
  10. #include "cqhci-crypto.h"
  11. /* Map from blk-crypto modes to CQHCI crypto algorithm IDs and key sizes */
  12. static const struct cqhci_crypto_alg_entry {
  13. enum cqhci_crypto_alg alg;
  14. enum cqhci_crypto_key_size key_size;
  15. } cqhci_crypto_algs[BLK_ENCRYPTION_MODE_MAX] = {
  16. [BLK_ENCRYPTION_MODE_AES_256_XTS] = {
  17. .alg = CQHCI_CRYPTO_ALG_AES_XTS,
  18. .key_size = CQHCI_CRYPTO_KEY_SIZE_256,
  19. },
  20. };
  21. static inline struct cqhci_host *
  22. cqhci_host_from_ksm(struct blk_keyslot_manager *ksm)
  23. {
  24. struct mmc_host *mmc = container_of(ksm, struct mmc_host, ksm);
  25. return mmc->cqe_private;
  26. }
  27. static int cqhci_crypto_program_key(struct cqhci_host *cq_host,
  28. const union cqhci_crypto_cfg_entry *cfg,
  29. int slot)
  30. {
  31. u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg);
  32. int i;
  33. if (cq_host->ops->program_key)
  34. return cq_host->ops->program_key(cq_host, cfg, slot);
  35. /* Clear CFGE */
  36. cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
  37. /* Write the key */
  38. for (i = 0; i < 16; i++) {
  39. cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[i]),
  40. slot_offset + i * sizeof(cfg->reg_val[0]));
  41. }
  42. /* Write dword 17 */
  43. cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[17]),
  44. slot_offset + 17 * sizeof(cfg->reg_val[0]));
  45. /* Write dword 16, which includes the new value of CFGE */
  46. cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]),
  47. slot_offset + 16 * sizeof(cfg->reg_val[0]));
  48. return 0;
  49. }
  50. static int cqhci_crypto_keyslot_program(struct blk_keyslot_manager *ksm,
  51. const struct blk_crypto_key *key,
  52. unsigned int slot)
  53. {
  54. struct cqhci_host *cq_host = cqhci_host_from_ksm(ksm);
  55. const union cqhci_crypto_cap_entry *ccap_array =
  56. cq_host->crypto_cap_array;
  57. const struct cqhci_crypto_alg_entry *alg =
  58. &cqhci_crypto_algs[key->crypto_cfg.crypto_mode];
  59. u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512;
  60. int i;
  61. int cap_idx = -1;
  62. union cqhci_crypto_cfg_entry cfg = {};
  63. int err;
  64. BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0);
  65. for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) {
  66. if (ccap_array[i].algorithm_id == alg->alg &&
  67. ccap_array[i].key_size == alg->key_size &&
  68. (ccap_array[i].sdus_mask & data_unit_mask)) {
  69. cap_idx = i;
  70. break;
  71. }
  72. }
  73. if (WARN_ON(cap_idx < 0))
  74. return -EOPNOTSUPP;
  75. cfg.data_unit_size = data_unit_mask;
  76. cfg.crypto_cap_idx = cap_idx;
  77. cfg.config_enable = CQHCI_CRYPTO_CONFIGURATION_ENABLE;
  78. if (ccap_array[cap_idx].algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS) {
  79. /* In XTS mode, the blk_crypto_key's size is already doubled */
  80. memcpy(cfg.crypto_key, key->raw, key->size/2);
  81. memcpy(cfg.crypto_key + CQHCI_CRYPTO_KEY_MAX_SIZE/2,
  82. key->raw + key->size/2, key->size/2);
  83. } else {
  84. memcpy(cfg.crypto_key, key->raw, key->size);
  85. }
  86. err = cqhci_crypto_program_key(cq_host, &cfg, slot);
  87. memzero_explicit(&cfg, sizeof(cfg));
  88. return err;
  89. }
  90. static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)
  91. {
  92. /*
  93. * Clear the crypto cfg on the device. Clearing CFGE
  94. * might not be sufficient, so just clear the entire cfg.
  95. */
  96. union cqhci_crypto_cfg_entry cfg = {};
  97. return cqhci_crypto_program_key(cq_host, &cfg, slot);
  98. }
  99. static int cqhci_crypto_keyslot_evict(struct blk_keyslot_manager *ksm,
  100. const struct blk_crypto_key *key,
  101. unsigned int slot)
  102. {
  103. struct cqhci_host *cq_host = cqhci_host_from_ksm(ksm);
  104. return cqhci_crypto_clear_keyslot(cq_host, slot);
  105. }
  106. /*
  107. * The keyslot management operations for CQHCI crypto.
  108. *
  109. * Note that the block layer ensures that these are never called while the host
  110. * controller is runtime-suspended. However, the CQE won't necessarily be
  111. * "enabled" when these are called, i.e. CQHCI_ENABLE might not be set in the
  112. * CQHCI_CFG register. But the hardware allows that.
  113. */
  114. static const struct blk_ksm_ll_ops cqhci_ksm_ops = {
  115. .keyslot_program = cqhci_crypto_keyslot_program,
  116. .keyslot_evict = cqhci_crypto_keyslot_evict,
  117. };
  118. static enum blk_crypto_mode_num
  119. cqhci_find_blk_crypto_mode(union cqhci_crypto_cap_entry cap)
  120. {
  121. int i;
  122. for (i = 0; i < ARRAY_SIZE(cqhci_crypto_algs); i++) {
  123. BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0);
  124. if (cqhci_crypto_algs[i].alg == cap.algorithm_id &&
  125. cqhci_crypto_algs[i].key_size == cap.key_size)
  126. return i;
  127. }
  128. return BLK_ENCRYPTION_MODE_INVALID;
  129. }
  130. /**
  131. * cqhci_crypto_init - initialize CQHCI crypto support
  132. * @cq_host: a cqhci host
  133. *
  134. * If the driver previously set MMC_CAP2_CRYPTO and the CQE declares
  135. * CQHCI_CAP_CS, initialize the crypto support. This involves reading the
  136. * crypto capability registers, initializing the keyslot manager, clearing all
  137. * keyslots, and enabling 128-bit task descriptors.
  138. *
  139. * Return: 0 if crypto was initialized or isn't supported; whether
  140. * MMC_CAP2_CRYPTO remains set indicates which one of those cases it is.
  141. * Also can return a negative errno value on unexpected error.
  142. */
  143. int cqhci_crypto_init(struct cqhci_host *cq_host)
  144. {
  145. struct mmc_host *mmc = cq_host->mmc;
  146. struct device *dev = mmc_dev(mmc);
  147. struct blk_keyslot_manager *ksm = &mmc->ksm;
  148. unsigned int num_keyslots;
  149. unsigned int cap_idx;
  150. enum blk_crypto_mode_num blk_mode_num;
  151. unsigned int slot;
  152. int err = 0;
  153. if (!(mmc->caps2 & MMC_CAP2_CRYPTO) ||
  154. !(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
  155. goto out;
  156. cq_host->crypto_capabilities.reg_val =
  157. cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP));
  158. cq_host->crypto_cfg_register =
  159. (u32)cq_host->crypto_capabilities.config_array_ptr * 0x100;
  160. cq_host->crypto_cap_array =
  161. devm_kcalloc(dev, cq_host->crypto_capabilities.num_crypto_cap,
  162. sizeof(cq_host->crypto_cap_array[0]), GFP_KERNEL);
  163. if (!cq_host->crypto_cap_array) {
  164. err = -ENOMEM;
  165. goto out;
  166. }
  167. /*
  168. * CCAP.CFGC is off by one, so the actual number of crypto
  169. * configurations (a.k.a. keyslots) is CCAP.CFGC + 1.
  170. */
  171. num_keyslots = cq_host->crypto_capabilities.config_count + 1;
  172. err = devm_blk_ksm_init(dev, ksm, num_keyslots);
  173. if (err)
  174. goto out;
  175. ksm->ksm_ll_ops = cqhci_ksm_ops;
  176. ksm->dev = dev;
  177. /* Unfortunately, CQHCI crypto only supports 32 DUN bits. */
  178. ksm->max_dun_bytes_supported = 4;
  179. ksm->features = BLK_CRYPTO_FEATURE_STANDARD_KEYS;
  180. /*
  181. * Cache all the crypto capabilities and advertise the supported crypto
  182. * modes and data unit sizes to the block layer.
  183. */
  184. for (cap_idx = 0; cap_idx < cq_host->crypto_capabilities.num_crypto_cap;
  185. cap_idx++) {
  186. cq_host->crypto_cap_array[cap_idx].reg_val =
  187. cpu_to_le32(cqhci_readl(cq_host,
  188. CQHCI_CRYPTOCAP +
  189. cap_idx * sizeof(__le32)));
  190. blk_mode_num = cqhci_find_blk_crypto_mode(
  191. cq_host->crypto_cap_array[cap_idx]);
  192. if (blk_mode_num == BLK_ENCRYPTION_MODE_INVALID)
  193. continue;
  194. ksm->crypto_modes_supported[blk_mode_num] |=
  195. cq_host->crypto_cap_array[cap_idx].sdus_mask * 512;
  196. }
  197. /* Clear all the keyslots so that we start in a known state. */
  198. for (slot = 0; slot < num_keyslots; slot++)
  199. cqhci_crypto_clear_keyslot(cq_host, slot);
  200. /* CQHCI crypto requires the use of 128-bit task descriptors. */
  201. cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
  202. return 0;
  203. out:
  204. mmc->caps2 &= ~MMC_CAP2_CRYPTO;
  205. return err;
  206. }