cqhci-core.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/delay.h>
  5. #include <linux/highmem.h>
  6. #include <linux/io.h>
  7. #include <linux/iopoll.h>
  8. #include <linux/module.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/slab.h>
  11. #include <linux/scatterlist.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/ktime.h>
  14. #include <linux/mmc/mmc.h>
  15. #include <linux/mmc/host.h>
  16. #include <linux/mmc/card.h>
  17. #include "cqhci.h"
  18. #include "cqhci-crypto.h"
  19. #define DCMD_SLOT 31
  20. #define NUM_SLOTS 32
  21. struct cqhci_slot {
  22. struct mmc_request *mrq;
  23. unsigned int flags;
  24. #define CQHCI_EXTERNAL_TIMEOUT BIT(0)
  25. #define CQHCI_COMPLETED BIT(1)
  26. #define CQHCI_HOST_CRC BIT(2)
  27. #define CQHCI_HOST_TIMEOUT BIT(3)
  28. #define CQHCI_HOST_OTHER BIT(4)
  29. };
  30. static inline u8 *get_desc(struct cqhci_host *cq_host, u8 tag)
  31. {
  32. return cq_host->desc_base + (tag * cq_host->slot_sz);
  33. }
  34. static inline u8 *get_link_desc(struct cqhci_host *cq_host, u8 tag)
  35. {
  36. u8 *desc = get_desc(cq_host, tag);
  37. return desc + cq_host->task_desc_len;
  38. }
  39. static inline dma_addr_t get_trans_desc_dma(struct cqhci_host *cq_host, u8 tag)
  40. {
  41. return cq_host->trans_desc_dma_base +
  42. (cq_host->mmc->max_segs * tag *
  43. cq_host->trans_desc_len);
  44. }
  45. static inline u8 *get_trans_desc(struct cqhci_host *cq_host, u8 tag)
  46. {
  47. return cq_host->trans_desc_base +
  48. (cq_host->trans_desc_len * cq_host->mmc->max_segs * tag);
  49. }
  50. static void setup_trans_desc(struct cqhci_host *cq_host, u8 tag)
  51. {
  52. u8 *link_temp;
  53. dma_addr_t trans_temp;
  54. link_temp = get_link_desc(cq_host, tag);
  55. trans_temp = get_trans_desc_dma(cq_host, tag);
  56. memset(link_temp, 0, cq_host->link_desc_len);
  57. if (cq_host->link_desc_len > 8)
  58. *(link_temp + 8) = 0;
  59. if (tag == DCMD_SLOT && (cq_host->mmc->caps2 & MMC_CAP2_CQE_DCMD)) {
  60. *link_temp = CQHCI_VALID(0) | CQHCI_ACT(0) | CQHCI_END(1);
  61. return;
  62. }
  63. *link_temp = CQHCI_VALID(1) | CQHCI_ACT(0x6) | CQHCI_END(0);
  64. if (cq_host->dma64) {
  65. __le64 *data_addr = (__le64 __force *)(link_temp + 4);
  66. data_addr[0] = cpu_to_le64(trans_temp);
  67. } else {
  68. __le32 *data_addr = (__le32 __force *)(link_temp + 4);
  69. data_addr[0] = cpu_to_le32(trans_temp);
  70. }
  71. }
  72. static void cqhci_set_irqs(struct cqhci_host *cq_host, u32 set)
  73. {
  74. cqhci_writel(cq_host, set, CQHCI_ISTE);
  75. cqhci_writel(cq_host, set, CQHCI_ISGE);
  76. }
  77. #define DRV_NAME "cqhci"
  78. #define CQHCI_DUMP(f, x...) \
  79. pr_err("%s: " DRV_NAME ": " f, mmc_hostname(mmc), ## x)
  80. static void cqhci_dumpregs(struct cqhci_host *cq_host)
  81. {
  82. struct mmc_host *mmc = cq_host->mmc;
  83. CQHCI_DUMP("============ CQHCI REGISTER DUMP ===========\n");
  84. CQHCI_DUMP("Caps: 0x%08x | Version: 0x%08x\n",
  85. cqhci_readl(cq_host, CQHCI_CAP),
  86. cqhci_readl(cq_host, CQHCI_VER));
  87. CQHCI_DUMP("Config: 0x%08x | Control: 0x%08x\n",
  88. cqhci_readl(cq_host, CQHCI_CFG),
  89. cqhci_readl(cq_host, CQHCI_CTL));
  90. CQHCI_DUMP("Int stat: 0x%08x | Int enab: 0x%08x\n",
  91. cqhci_readl(cq_host, CQHCI_IS),
  92. cqhci_readl(cq_host, CQHCI_ISTE));
  93. CQHCI_DUMP("Int sig: 0x%08x | Int Coal: 0x%08x\n",
  94. cqhci_readl(cq_host, CQHCI_ISGE),
  95. cqhci_readl(cq_host, CQHCI_IC));
  96. CQHCI_DUMP("TDL base: 0x%08x | TDL up32: 0x%08x\n",
  97. cqhci_readl(cq_host, CQHCI_TDLBA),
  98. cqhci_readl(cq_host, CQHCI_TDLBAU));
  99. CQHCI_DUMP("Doorbell: 0x%08x | TCN: 0x%08x\n",
  100. cqhci_readl(cq_host, CQHCI_TDBR),
  101. cqhci_readl(cq_host, CQHCI_TCN));
  102. CQHCI_DUMP("Dev queue: 0x%08x | Dev Pend: 0x%08x\n",
  103. cqhci_readl(cq_host, CQHCI_DQS),
  104. cqhci_readl(cq_host, CQHCI_DPT));
  105. CQHCI_DUMP("Task clr: 0x%08x | SSC1: 0x%08x\n",
  106. cqhci_readl(cq_host, CQHCI_TCLR),
  107. cqhci_readl(cq_host, CQHCI_SSC1));
  108. CQHCI_DUMP("SSC2: 0x%08x | DCMD rsp: 0x%08x\n",
  109. cqhci_readl(cq_host, CQHCI_SSC2),
  110. cqhci_readl(cq_host, CQHCI_CRDCT));
  111. CQHCI_DUMP("RED mask: 0x%08x | TERRI: 0x%08x\n",
  112. cqhci_readl(cq_host, CQHCI_RMEM),
  113. cqhci_readl(cq_host, CQHCI_TERRI));
  114. CQHCI_DUMP("Resp idx: 0x%08x | Resp arg: 0x%08x\n",
  115. cqhci_readl(cq_host, CQHCI_CRI),
  116. cqhci_readl(cq_host, CQHCI_CRA));
  117. if (cq_host->ops->dumpregs)
  118. cq_host->ops->dumpregs(mmc);
  119. else
  120. CQHCI_DUMP(": ===========================================\n");
  121. }
  122. /*
  123. * The allocated descriptor table for task, link & transfer descritors
  124. * looks like:
  125. * |----------|
  126. * |task desc | |->|----------|
  127. * |----------| | |trans desc|
  128. * |link desc-|->| |----------|
  129. * |----------| .
  130. * . .
  131. * no. of slots max-segs
  132. * . |----------|
  133. * |----------|
  134. * The idea here is to create the [task+trans] table and mark & point the
  135. * link desc to the transfer desc table on a per slot basis.
  136. */
  137. static int cqhci_host_alloc_tdl(struct cqhci_host *cq_host)
  138. {
  139. int i = 0;
  140. /* task descriptor can be 64/128 bit irrespective of arch */
  141. if (cq_host->caps & CQHCI_TASK_DESC_SZ_128) {
  142. cqhci_writel(cq_host, cqhci_readl(cq_host, CQHCI_CFG) |
  143. CQHCI_TASK_DESC_SZ, CQHCI_CFG);
  144. cq_host->task_desc_len = 16;
  145. } else {
  146. cq_host->task_desc_len = 8;
  147. }
  148. /*
  149. * 96 bits length of transfer desc instead of 128 bits which means
  150. * ADMA would expect next valid descriptor at the 96th bit
  151. * or 128th bit
  152. */
  153. if (cq_host->dma64) {
  154. if (cq_host->quirks & CQHCI_QUIRK_SHORT_TXFR_DESC_SZ)
  155. cq_host->trans_desc_len = 12;
  156. else
  157. cq_host->trans_desc_len = 16;
  158. cq_host->link_desc_len = 16;
  159. } else {
  160. cq_host->trans_desc_len = 8;
  161. cq_host->link_desc_len = 8;
  162. }
  163. /* total size of a slot: 1 task & 1 transfer (link) */
  164. cq_host->slot_sz = cq_host->task_desc_len + cq_host->link_desc_len;
  165. cq_host->desc_size = cq_host->slot_sz * cq_host->num_slots;
  166. cq_host->data_size = cq_host->trans_desc_len * cq_host->mmc->max_segs *
  167. cq_host->mmc->cqe_qdepth;
  168. pr_debug("%s: cqhci: desc_size: %zu data_sz: %zu slot-sz: %d\n",
  169. mmc_hostname(cq_host->mmc), cq_host->desc_size, cq_host->data_size,
  170. cq_host->slot_sz);
  171. /*
  172. * allocate a dma-mapped chunk of memory for the descriptors
  173. * allocate a dma-mapped chunk of memory for link descriptors
  174. * setup each link-desc memory offset per slot-number to
  175. * the descriptor table.
  176. */
  177. cq_host->desc_base = dmam_alloc_coherent(mmc_dev(cq_host->mmc),
  178. cq_host->desc_size,
  179. &cq_host->desc_dma_base,
  180. GFP_KERNEL);
  181. if (!cq_host->desc_base)
  182. return -ENOMEM;
  183. cq_host->trans_desc_base = dmam_alloc_coherent(mmc_dev(cq_host->mmc),
  184. cq_host->data_size,
  185. &cq_host->trans_desc_dma_base,
  186. GFP_KERNEL);
  187. if (!cq_host->trans_desc_base) {
  188. dmam_free_coherent(mmc_dev(cq_host->mmc), cq_host->desc_size,
  189. cq_host->desc_base,
  190. cq_host->desc_dma_base);
  191. cq_host->desc_base = NULL;
  192. cq_host->desc_dma_base = 0;
  193. return -ENOMEM;
  194. }
  195. pr_debug("%s: cqhci: desc-base: 0x%p trans-base: 0x%p\n desc_dma 0x%llx trans_dma: 0x%llx\n",
  196. mmc_hostname(cq_host->mmc), cq_host->desc_base, cq_host->trans_desc_base,
  197. (unsigned long long)cq_host->desc_dma_base,
  198. (unsigned long long)cq_host->trans_desc_dma_base);
  199. for (; i < (cq_host->num_slots); i++)
  200. setup_trans_desc(cq_host, i);
  201. return 0;
  202. }
  203. static void __cqhci_enable(struct cqhci_host *cq_host)
  204. {
  205. struct mmc_host *mmc = cq_host->mmc;
  206. u32 cqcfg;
  207. cqcfg = cqhci_readl(cq_host, CQHCI_CFG);
  208. /* Configuration must not be changed while enabled */
  209. if (cqcfg & CQHCI_ENABLE) {
  210. cqcfg &= ~CQHCI_ENABLE;
  211. cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
  212. }
  213. cqcfg &= ~(CQHCI_DCMD | CQHCI_TASK_DESC_SZ);
  214. if (mmc->caps2 & MMC_CAP2_CQE_DCMD)
  215. cqcfg |= CQHCI_DCMD;
  216. if (cq_host->caps & CQHCI_TASK_DESC_SZ_128)
  217. cqcfg |= CQHCI_TASK_DESC_SZ;
  218. if (mmc->caps2 & MMC_CAP2_CRYPTO)
  219. cqcfg |= CQHCI_CRYPTO_GENERAL_ENABLE;
  220. cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
  221. cqhci_writel(cq_host, lower_32_bits(cq_host->desc_dma_base),
  222. CQHCI_TDLBA);
  223. cqhci_writel(cq_host, upper_32_bits(cq_host->desc_dma_base),
  224. CQHCI_TDLBAU);
  225. cqhci_writel(cq_host, cq_host->rca, CQHCI_SSC2);
  226. cqhci_set_irqs(cq_host, 0);
  227. cqcfg |= CQHCI_ENABLE;
  228. cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
  229. if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT)
  230. cqhci_writel(cq_host, 0, CQHCI_CTL);
  231. mmc->cqe_on = true;
  232. if (cq_host->ops->enable)
  233. cq_host->ops->enable(mmc);
  234. /* Ensure all writes are done before interrupts are enabled */
  235. wmb();
  236. cqhci_set_irqs(cq_host, CQHCI_IS_MASK);
  237. cq_host->activated = true;
  238. }
  239. static void __cqhci_disable(struct cqhci_host *cq_host)
  240. {
  241. u32 cqcfg;
  242. cqcfg = cqhci_readl(cq_host, CQHCI_CFG);
  243. cqcfg &= ~CQHCI_ENABLE;
  244. cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
  245. cq_host->mmc->cqe_on = false;
  246. cq_host->activated = false;
  247. }
  248. int cqhci_deactivate(struct mmc_host *mmc)
  249. {
  250. struct cqhci_host *cq_host = mmc->cqe_private;
  251. if (cq_host->enabled && cq_host->activated)
  252. __cqhci_disable(cq_host);
  253. return 0;
  254. }
  255. EXPORT_SYMBOL(cqhci_deactivate);
  256. int cqhci_resume(struct mmc_host *mmc)
  257. {
  258. /* Re-enable is done upon first request */
  259. return 0;
  260. }
  261. EXPORT_SYMBOL(cqhci_resume);
  262. static int cqhci_enable(struct mmc_host *mmc, struct mmc_card *card)
  263. {
  264. struct cqhci_host *cq_host = mmc->cqe_private;
  265. int err;
  266. if (!card->ext_csd.cmdq_en)
  267. return -EINVAL;
  268. if (cq_host->enabled)
  269. return 0;
  270. cq_host->rca = card->rca;
  271. err = cqhci_host_alloc_tdl(cq_host);
  272. if (err) {
  273. pr_err("%s: Failed to enable CQE, error %d\n",
  274. mmc_hostname(mmc), err);
  275. return err;
  276. }
  277. __cqhci_enable(cq_host);
  278. cq_host->enabled = true;
  279. #ifdef DEBUG
  280. cqhci_dumpregs(cq_host);
  281. #endif
  282. return 0;
  283. }
  284. /* CQHCI is idle and should halt immediately, so set a small timeout */
  285. #define CQHCI_OFF_TIMEOUT 100
  286. static u32 cqhci_read_ctl(struct cqhci_host *cq_host)
  287. {
  288. return cqhci_readl(cq_host, CQHCI_CTL);
  289. }
  290. static void cqhci_off(struct mmc_host *mmc)
  291. {
  292. struct cqhci_host *cq_host = mmc->cqe_private;
  293. u32 reg;
  294. int err;
  295. if (!cq_host->enabled || !mmc->cqe_on || cq_host->recovery_halt)
  296. return;
  297. if (cq_host->ops->disable)
  298. cq_host->ops->disable(mmc, false);
  299. cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
  300. err = readx_poll_timeout(cqhci_read_ctl, cq_host, reg,
  301. reg & CQHCI_HALT, 0, CQHCI_OFF_TIMEOUT);
  302. if (err < 0)
  303. pr_err("%s: cqhci: CQE stuck on\n", mmc_hostname(mmc));
  304. else
  305. pr_debug("%s: cqhci: CQE off\n", mmc_hostname(mmc));
  306. if (cq_host->ops->post_disable)
  307. cq_host->ops->post_disable(mmc);
  308. mmc->cqe_on = false;
  309. }
  310. static void cqhci_disable(struct mmc_host *mmc)
  311. {
  312. struct cqhci_host *cq_host = mmc->cqe_private;
  313. if (!cq_host->enabled)
  314. return;
  315. cqhci_off(mmc);
  316. __cqhci_disable(cq_host);
  317. dmam_free_coherent(mmc_dev(mmc), cq_host->data_size,
  318. cq_host->trans_desc_base,
  319. cq_host->trans_desc_dma_base);
  320. dmam_free_coherent(mmc_dev(mmc), cq_host->desc_size,
  321. cq_host->desc_base,
  322. cq_host->desc_dma_base);
  323. cq_host->trans_desc_base = NULL;
  324. cq_host->desc_base = NULL;
  325. cq_host->enabled = false;
  326. }
  327. static void cqhci_prep_task_desc(struct mmc_request *mrq,
  328. struct cqhci_host *cq_host, int tag)
  329. {
  330. __le64 *task_desc = (__le64 __force *)get_desc(cq_host, tag);
  331. u32 req_flags = mrq->data->flags;
  332. u64 desc0;
  333. desc0 = CQHCI_VALID(1) |
  334. CQHCI_END(1) |
  335. CQHCI_INT(1) |
  336. CQHCI_ACT(0x5) |
  337. CQHCI_FORCED_PROG(!!(req_flags & MMC_DATA_FORCED_PRG)) |
  338. CQHCI_DATA_TAG(!!(req_flags & MMC_DATA_DAT_TAG)) |
  339. CQHCI_DATA_DIR(!!(req_flags & MMC_DATA_READ)) |
  340. CQHCI_PRIORITY(!!(req_flags & MMC_DATA_PRIO)) |
  341. CQHCI_QBAR(!!(req_flags & MMC_DATA_QBR)) |
  342. CQHCI_REL_WRITE(!!(req_flags & MMC_DATA_REL_WR)) |
  343. CQHCI_BLK_COUNT(mrq->data->blocks) |
  344. CQHCI_BLK_ADDR((u64)mrq->data->blk_addr);
  345. task_desc[0] = cpu_to_le64(desc0);
  346. if (cq_host->caps & CQHCI_TASK_DESC_SZ_128) {
  347. u64 desc1 = cqhci_crypto_prep_task_desc(mrq);
  348. task_desc[1] = cpu_to_le64(desc1);
  349. pr_debug("%s: cqhci: tag %d task descriptor 0x%016llx%016llx\n",
  350. mmc_hostname(mrq->host), mrq->tag, desc1, desc0);
  351. } else {
  352. pr_debug("%s: cqhci: tag %d task descriptor 0x%016llx\n",
  353. mmc_hostname(mrq->host), mrq->tag, desc0);
  354. }
  355. }
  356. static int cqhci_dma_map(struct mmc_host *host, struct mmc_request *mrq)
  357. {
  358. int sg_count;
  359. struct mmc_data *data = mrq->data;
  360. if (!data)
  361. return -EINVAL;
  362. sg_count = dma_map_sg(mmc_dev(host), data->sg,
  363. data->sg_len,
  364. (data->flags & MMC_DATA_WRITE) ?
  365. DMA_TO_DEVICE : DMA_FROM_DEVICE);
  366. if (!sg_count) {
  367. pr_err("%s: sg-len: %d\n", __func__, data->sg_len);
  368. return -ENOMEM;
  369. }
  370. return sg_count;
  371. }
  372. static void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end,
  373. bool dma64)
  374. {
  375. __le32 *attr = (__le32 __force *)desc;
  376. *attr = (CQHCI_VALID(1) |
  377. CQHCI_END(end ? 1 : 0) |
  378. CQHCI_INT(0) |
  379. CQHCI_ACT(0x4) |
  380. CQHCI_DAT_LENGTH(len));
  381. if (dma64) {
  382. __le64 *dataddr = (__le64 __force *)(desc + 4);
  383. dataddr[0] = cpu_to_le64(addr);
  384. } else {
  385. __le32 *dataddr = (__le32 __force *)(desc + 4);
  386. dataddr[0] = cpu_to_le32(addr);
  387. }
  388. }
  389. static int cqhci_prep_tran_desc(struct mmc_request *mrq,
  390. struct cqhci_host *cq_host, int tag)
  391. {
  392. struct mmc_data *data = mrq->data;
  393. int i, sg_count, len;
  394. bool end = false;
  395. bool dma64 = cq_host->dma64;
  396. dma_addr_t addr;
  397. u8 *desc;
  398. struct scatterlist *sg;
  399. sg_count = cqhci_dma_map(mrq->host, mrq);
  400. if (sg_count < 0) {
  401. pr_err("%s: %s: unable to map sg lists, %d\n",
  402. mmc_hostname(mrq->host), __func__, sg_count);
  403. return sg_count;
  404. }
  405. desc = get_trans_desc(cq_host, tag);
  406. for_each_sg(data->sg, sg, sg_count, i) {
  407. addr = sg_dma_address(sg);
  408. len = sg_dma_len(sg);
  409. if ((i+1) == sg_count)
  410. end = true;
  411. cqhci_set_tran_desc(desc, addr, len, end, dma64);
  412. desc += cq_host->trans_desc_len;
  413. }
  414. return 0;
  415. }
  416. static void cqhci_prep_dcmd_desc(struct mmc_host *mmc,
  417. struct mmc_request *mrq)
  418. {
  419. u64 *task_desc = NULL;
  420. u64 data = 0;
  421. u8 resp_type;
  422. u8 *desc;
  423. __le64 *dataddr;
  424. struct cqhci_host *cq_host = mmc->cqe_private;
  425. u8 timing;
  426. if (!(mrq->cmd->flags & MMC_RSP_PRESENT)) {
  427. resp_type = 0x0;
  428. timing = 0x1;
  429. } else {
  430. if (mrq->cmd->flags & MMC_RSP_R1B) {
  431. resp_type = 0x3;
  432. timing = 0x0;
  433. } else {
  434. resp_type = 0x2;
  435. timing = 0x1;
  436. }
  437. }
  438. task_desc = (__le64 __force *)get_desc(cq_host, cq_host->dcmd_slot);
  439. memset(task_desc, 0, cq_host->task_desc_len);
  440. data |= (CQHCI_VALID(1) |
  441. CQHCI_END(1) |
  442. CQHCI_INT(1) |
  443. CQHCI_QBAR(1) |
  444. CQHCI_ACT(0x5) |
  445. CQHCI_CMD_INDEX(mrq->cmd->opcode) |
  446. CQHCI_CMD_TIMING(timing) | CQHCI_RESP_TYPE(resp_type));
  447. if (cq_host->ops->update_dcmd_desc)
  448. cq_host->ops->update_dcmd_desc(mmc, mrq, &data);
  449. *task_desc |= data;
  450. desc = (u8 *)task_desc;
  451. pr_debug("%s: cqhci: dcmd: cmd: %d timing: %d resp: %d\n",
  452. mmc_hostname(mmc), mrq->cmd->opcode, timing, resp_type);
  453. dataddr = (__le64 __force *)(desc + 4);
  454. dataddr[0] = cpu_to_le64((u64)mrq->cmd->arg);
  455. }
  456. static void cqhci_post_req(struct mmc_host *host, struct mmc_request *mrq)
  457. {
  458. struct mmc_data *data = mrq->data;
  459. if (data) {
  460. dma_unmap_sg(mmc_dev(host), data->sg, data->sg_len,
  461. (data->flags & MMC_DATA_READ) ?
  462. DMA_FROM_DEVICE : DMA_TO_DEVICE);
  463. }
  464. }
  465. static inline int cqhci_tag(struct mmc_request *mrq)
  466. {
  467. return mrq->cmd ? DCMD_SLOT : mrq->tag;
  468. }
  469. static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  470. {
  471. int err = 0;
  472. int tag = cqhci_tag(mrq);
  473. struct cqhci_host *cq_host = mmc->cqe_private;
  474. unsigned long flags;
  475. if (!cq_host->enabled) {
  476. pr_err("%s: cqhci: not enabled\n", mmc_hostname(mmc));
  477. return -EINVAL;
  478. }
  479. /* First request after resume has to re-enable */
  480. if (!cq_host->activated)
  481. __cqhci_enable(cq_host);
  482. if (!mmc->cqe_on) {
  483. if (cq_host->ops->pre_enable)
  484. cq_host->ops->pre_enable(mmc);
  485. cqhci_writel(cq_host, 0, CQHCI_CTL);
  486. mmc->cqe_on = true;
  487. pr_debug("%s: cqhci: CQE on\n", mmc_hostname(mmc));
  488. if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT) {
  489. pr_err("%s: cqhci: CQE failed to exit halt state\n",
  490. mmc_hostname(mmc));
  491. }
  492. if (cq_host->ops->enable)
  493. cq_host->ops->enable(mmc);
  494. }
  495. if (mrq->data) {
  496. cqhci_prep_task_desc(mrq, cq_host, tag);
  497. err = cqhci_prep_tran_desc(mrq, cq_host, tag);
  498. if (err) {
  499. pr_err("%s: cqhci: failed to setup tx desc: %d\n",
  500. mmc_hostname(mmc), err);
  501. return err;
  502. }
  503. } else {
  504. cqhci_prep_dcmd_desc(mmc, mrq);
  505. }
  506. spin_lock_irqsave(&cq_host->lock, flags);
  507. if (cq_host->recovery_halt) {
  508. err = -EBUSY;
  509. goto out_unlock;
  510. }
  511. cq_host->slot[tag].mrq = mrq;
  512. cq_host->slot[tag].flags = 0;
  513. cq_host->qcnt += 1;
  514. /* Make sure descriptors are ready before ringing the doorbell */
  515. wmb();
  516. cqhci_writel(cq_host, 1 << tag, CQHCI_TDBR);
  517. if (!(cqhci_readl(cq_host, CQHCI_TDBR) & (1 << tag)))
  518. pr_debug("%s: cqhci: doorbell not set for tag %d\n",
  519. mmc_hostname(mmc), tag);
  520. out_unlock:
  521. spin_unlock_irqrestore(&cq_host->lock, flags);
  522. if (err)
  523. cqhci_post_req(mmc, mrq);
  524. return err;
  525. }
  526. static void cqhci_recovery_needed(struct mmc_host *mmc, struct mmc_request *mrq,
  527. bool notify)
  528. {
  529. struct cqhci_host *cq_host = mmc->cqe_private;
  530. if (!cq_host->recovery_halt) {
  531. cq_host->recovery_halt = true;
  532. pr_debug("%s: cqhci: recovery needed\n", mmc_hostname(mmc));
  533. wake_up(&cq_host->wait_queue);
  534. if (notify && mrq->recovery_notifier)
  535. mrq->recovery_notifier(mrq);
  536. }
  537. }
  538. static unsigned int cqhci_error_flags(int error1, int error2)
  539. {
  540. int error = error1 ? error1 : error2;
  541. switch (error) {
  542. case -EILSEQ:
  543. return CQHCI_HOST_CRC;
  544. case -ETIMEDOUT:
  545. return CQHCI_HOST_TIMEOUT;
  546. default:
  547. return CQHCI_HOST_OTHER;
  548. }
  549. }
  550. static void cqhci_error_irq(struct mmc_host *mmc, u32 status, int cmd_error,
  551. int data_error)
  552. {
  553. struct cqhci_host *cq_host = mmc->cqe_private;
  554. struct cqhci_slot *slot;
  555. u32 terri;
  556. u32 tdpe;
  557. int tag;
  558. spin_lock(&cq_host->lock);
  559. terri = cqhci_readl(cq_host, CQHCI_TERRI);
  560. pr_debug("%s: cqhci: error IRQ status: 0x%08x cmd error %d data error %d TERRI: 0x%08x\n",
  561. mmc_hostname(mmc), status, cmd_error, data_error, terri);
  562. /* Forget about errors when recovery has already been triggered */
  563. if (cq_host->recovery_halt)
  564. goto out_unlock;
  565. if (!cq_host->qcnt) {
  566. WARN_ONCE(1, "%s: cqhci: error when idle. IRQ status: 0x%08x cmd error %d data error %d TERRI: 0x%08x\n",
  567. mmc_hostname(mmc), status, cmd_error, data_error,
  568. terri);
  569. goto out_unlock;
  570. }
  571. if (CQHCI_TERRI_C_VALID(terri)) {
  572. tag = CQHCI_TERRI_C_TASK(terri);
  573. slot = &cq_host->slot[tag];
  574. if (slot->mrq) {
  575. slot->flags = cqhci_error_flags(cmd_error, data_error);
  576. cqhci_recovery_needed(mmc, slot->mrq, true);
  577. }
  578. }
  579. if (CQHCI_TERRI_D_VALID(terri)) {
  580. tag = CQHCI_TERRI_D_TASK(terri);
  581. slot = &cq_host->slot[tag];
  582. if (slot->mrq) {
  583. slot->flags = cqhci_error_flags(data_error, cmd_error);
  584. cqhci_recovery_needed(mmc, slot->mrq, true);
  585. }
  586. }
  587. /*
  588. * Handle ICCE ("Invalid Crypto Configuration Error"). This should
  589. * never happen, since the block layer ensures that all crypto-enabled
  590. * I/O requests have a valid keyslot before they reach the driver.
  591. *
  592. * Note that GCE ("General Crypto Error") is different; it already got
  593. * handled above by checking TERRI.
  594. */
  595. if (status & CQHCI_IS_ICCE) {
  596. tdpe = cqhci_readl(cq_host, CQHCI_TDPE);
  597. WARN_ONCE(1,
  598. "%s: cqhci: invalid crypto configuration error. IRQ status: 0x%08x TDPE: 0x%08x\n",
  599. mmc_hostname(mmc), status, tdpe);
  600. while (tdpe != 0) {
  601. tag = __ffs(tdpe);
  602. tdpe &= ~(1 << tag);
  603. slot = &cq_host->slot[tag];
  604. if (!slot->mrq)
  605. continue;
  606. slot->flags = cqhci_error_flags(data_error, cmd_error);
  607. cqhci_recovery_needed(mmc, slot->mrq, true);
  608. }
  609. }
  610. if (!cq_host->recovery_halt) {
  611. /*
  612. * The only way to guarantee forward progress is to mark at
  613. * least one task in error, so if none is indicated, pick one.
  614. */
  615. for (tag = 0; tag < NUM_SLOTS; tag++) {
  616. slot = &cq_host->slot[tag];
  617. if (!slot->mrq)
  618. continue;
  619. slot->flags = cqhci_error_flags(data_error, cmd_error);
  620. cqhci_recovery_needed(mmc, slot->mrq, true);
  621. break;
  622. }
  623. }
  624. out_unlock:
  625. spin_unlock(&cq_host->lock);
  626. }
  627. static void cqhci_finish_mrq(struct mmc_host *mmc, unsigned int tag)
  628. {
  629. struct cqhci_host *cq_host = mmc->cqe_private;
  630. struct cqhci_slot *slot = &cq_host->slot[tag];
  631. struct mmc_request *mrq = slot->mrq;
  632. struct mmc_data *data;
  633. if (!mrq) {
  634. WARN_ONCE(1, "%s: cqhci: spurious TCN for tag %d\n",
  635. mmc_hostname(mmc), tag);
  636. return;
  637. }
  638. /* No completions allowed during recovery */
  639. if (cq_host->recovery_halt) {
  640. slot->flags |= CQHCI_COMPLETED;
  641. return;
  642. }
  643. slot->mrq = NULL;
  644. cq_host->qcnt -= 1;
  645. data = mrq->data;
  646. if (data) {
  647. if (data->error)
  648. data->bytes_xfered = 0;
  649. else
  650. data->bytes_xfered = data->blksz * data->blocks;
  651. }
  652. mmc_cqe_request_done(mmc, mrq);
  653. }
  654. irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
  655. int data_error)
  656. {
  657. u32 status;
  658. unsigned long tag = 0, comp_status;
  659. struct cqhci_host *cq_host = mmc->cqe_private;
  660. status = cqhci_readl(cq_host, CQHCI_IS);
  661. cqhci_writel(cq_host, status, CQHCI_IS);
  662. pr_debug("%s: cqhci: IRQ status: 0x%08x\n", mmc_hostname(mmc), status);
  663. if ((status & (CQHCI_IS_RED | CQHCI_IS_GCE | CQHCI_IS_ICCE)) ||
  664. cmd_error || data_error)
  665. cqhci_error_irq(mmc, status, cmd_error, data_error);
  666. if (status & CQHCI_IS_TCC) {
  667. /* read TCN and complete the request */
  668. comp_status = cqhci_readl(cq_host, CQHCI_TCN);
  669. cqhci_writel(cq_host, comp_status, CQHCI_TCN);
  670. pr_debug("%s: cqhci: TCN: 0x%08lx\n",
  671. mmc_hostname(mmc), comp_status);
  672. spin_lock(&cq_host->lock);
  673. for_each_set_bit(tag, &comp_status, cq_host->num_slots) {
  674. /* complete the corresponding mrq */
  675. pr_debug("%s: cqhci: completing tag %lu\n",
  676. mmc_hostname(mmc), tag);
  677. cqhci_finish_mrq(mmc, tag);
  678. }
  679. if (cq_host->waiting_for_idle && !cq_host->qcnt) {
  680. cq_host->waiting_for_idle = false;
  681. wake_up(&cq_host->wait_queue);
  682. }
  683. spin_unlock(&cq_host->lock);
  684. }
  685. if (status & CQHCI_IS_TCL)
  686. wake_up(&cq_host->wait_queue);
  687. if (status & CQHCI_IS_HAC)
  688. wake_up(&cq_host->wait_queue);
  689. return IRQ_HANDLED;
  690. }
  691. EXPORT_SYMBOL(cqhci_irq);
  692. static bool cqhci_is_idle(struct cqhci_host *cq_host, int *ret)
  693. {
  694. unsigned long flags;
  695. bool is_idle;
  696. spin_lock_irqsave(&cq_host->lock, flags);
  697. is_idle = !cq_host->qcnt || cq_host->recovery_halt;
  698. *ret = cq_host->recovery_halt ? -EBUSY : 0;
  699. cq_host->waiting_for_idle = !is_idle;
  700. spin_unlock_irqrestore(&cq_host->lock, flags);
  701. return is_idle;
  702. }
  703. static int cqhci_wait_for_idle(struct mmc_host *mmc)
  704. {
  705. struct cqhci_host *cq_host = mmc->cqe_private;
  706. int ret;
  707. wait_event(cq_host->wait_queue, cqhci_is_idle(cq_host, &ret));
  708. return ret;
  709. }
  710. static bool cqhci_timeout(struct mmc_host *mmc, struct mmc_request *mrq,
  711. bool *recovery_needed)
  712. {
  713. struct cqhci_host *cq_host = mmc->cqe_private;
  714. int tag = cqhci_tag(mrq);
  715. struct cqhci_slot *slot = &cq_host->slot[tag];
  716. unsigned long flags;
  717. bool timed_out;
  718. spin_lock_irqsave(&cq_host->lock, flags);
  719. timed_out = slot->mrq == mrq;
  720. if (timed_out) {
  721. slot->flags |= CQHCI_EXTERNAL_TIMEOUT;
  722. cqhci_recovery_needed(mmc, mrq, false);
  723. *recovery_needed = cq_host->recovery_halt;
  724. }
  725. spin_unlock_irqrestore(&cq_host->lock, flags);
  726. if (timed_out) {
  727. pr_err("%s: cqhci: timeout for tag %d\n",
  728. mmc_hostname(mmc), tag);
  729. cqhci_dumpregs(cq_host);
  730. }
  731. return timed_out;
  732. }
  733. static bool cqhci_tasks_cleared(struct cqhci_host *cq_host)
  734. {
  735. return !(cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_CLEAR_ALL_TASKS);
  736. }
  737. static bool cqhci_clear_all_tasks(struct mmc_host *mmc, unsigned int timeout)
  738. {
  739. struct cqhci_host *cq_host = mmc->cqe_private;
  740. bool ret;
  741. u32 ctl;
  742. cqhci_set_irqs(cq_host, CQHCI_IS_TCL);
  743. ctl = cqhci_readl(cq_host, CQHCI_CTL);
  744. ctl |= CQHCI_CLEAR_ALL_TASKS;
  745. cqhci_writel(cq_host, ctl, CQHCI_CTL);
  746. wait_event_timeout(cq_host->wait_queue, cqhci_tasks_cleared(cq_host),
  747. msecs_to_jiffies(timeout) + 1);
  748. cqhci_set_irqs(cq_host, 0);
  749. ret = cqhci_tasks_cleared(cq_host);
  750. if (!ret)
  751. pr_debug("%s: cqhci: Failed to clear tasks\n",
  752. mmc_hostname(mmc));
  753. return ret;
  754. }
  755. static bool cqhci_halted(struct cqhci_host *cq_host)
  756. {
  757. return cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT;
  758. }
  759. static bool cqhci_halt(struct mmc_host *mmc, unsigned int timeout)
  760. {
  761. struct cqhci_host *cq_host = mmc->cqe_private;
  762. bool ret;
  763. u32 ctl;
  764. if (cqhci_halted(cq_host))
  765. return true;
  766. cqhci_set_irqs(cq_host, CQHCI_IS_HAC);
  767. ctl = cqhci_readl(cq_host, CQHCI_CTL);
  768. ctl |= CQHCI_HALT;
  769. cqhci_writel(cq_host, ctl, CQHCI_CTL);
  770. wait_event_timeout(cq_host->wait_queue, cqhci_halted(cq_host),
  771. msecs_to_jiffies(timeout) + 1);
  772. cqhci_set_irqs(cq_host, 0);
  773. ret = cqhci_halted(cq_host);
  774. if (!ret)
  775. pr_debug("%s: cqhci: Failed to halt\n", mmc_hostname(mmc));
  776. return ret;
  777. }
  778. /*
  779. * After halting we expect to be able to use the command line. We interpret the
  780. * failure to halt to mean the data lines might still be in use (and the upper
  781. * layers will need to send a STOP command), so we set the timeout based on a
  782. * generous command timeout.
  783. */
  784. #define CQHCI_START_HALT_TIMEOUT 5
  785. static void cqhci_recovery_start(struct mmc_host *mmc)
  786. {
  787. struct cqhci_host *cq_host = mmc->cqe_private;
  788. pr_debug("%s: cqhci: %s\n", mmc_hostname(mmc), __func__);
  789. WARN_ON(!cq_host->recovery_halt);
  790. cqhci_halt(mmc, CQHCI_START_HALT_TIMEOUT);
  791. if (cq_host->ops->disable)
  792. cq_host->ops->disable(mmc, true);
  793. mmc->cqe_on = false;
  794. }
  795. static int cqhci_error_from_flags(unsigned int flags)
  796. {
  797. if (!flags)
  798. return 0;
  799. /* CRC errors might indicate re-tuning so prefer to report that */
  800. if (flags & CQHCI_HOST_CRC)
  801. return -EILSEQ;
  802. if (flags & (CQHCI_EXTERNAL_TIMEOUT | CQHCI_HOST_TIMEOUT))
  803. return -ETIMEDOUT;
  804. return -EIO;
  805. }
  806. static void cqhci_recover_mrq(struct cqhci_host *cq_host, unsigned int tag)
  807. {
  808. struct cqhci_slot *slot = &cq_host->slot[tag];
  809. struct mmc_request *mrq = slot->mrq;
  810. struct mmc_data *data;
  811. if (!mrq)
  812. return;
  813. slot->mrq = NULL;
  814. cq_host->qcnt -= 1;
  815. data = mrq->data;
  816. if (data) {
  817. data->bytes_xfered = 0;
  818. data->error = cqhci_error_from_flags(slot->flags);
  819. } else {
  820. mrq->cmd->error = cqhci_error_from_flags(slot->flags);
  821. }
  822. mmc_cqe_request_done(cq_host->mmc, mrq);
  823. }
  824. static void cqhci_recover_mrqs(struct cqhci_host *cq_host)
  825. {
  826. int i;
  827. for (i = 0; i < cq_host->num_slots; i++)
  828. cqhci_recover_mrq(cq_host, i);
  829. }
  830. /*
  831. * By now the command and data lines should be unused so there is no reason for
  832. * CQHCI to take a long time to halt, but if it doesn't halt there could be
  833. * problems clearing tasks, so be generous.
  834. */
  835. #define CQHCI_FINISH_HALT_TIMEOUT 20
  836. /* CQHCI could be expected to clear it's internal state pretty quickly */
  837. #define CQHCI_CLEAR_TIMEOUT 20
  838. static void cqhci_recovery_finish(struct mmc_host *mmc)
  839. {
  840. struct cqhci_host *cq_host = mmc->cqe_private;
  841. unsigned long flags;
  842. u32 cqcfg;
  843. bool ok;
  844. pr_debug("%s: cqhci: %s\n", mmc_hostname(mmc), __func__);
  845. WARN_ON(!cq_host->recovery_halt);
  846. ok = cqhci_halt(mmc, CQHCI_FINISH_HALT_TIMEOUT);
  847. if (!cqhci_clear_all_tasks(mmc, CQHCI_CLEAR_TIMEOUT))
  848. ok = false;
  849. /*
  850. * The specification contradicts itself, by saying that tasks cannot be
  851. * cleared if CQHCI does not halt, but if CQHCI does not halt, it should
  852. * be disabled/re-enabled, but not to disable before clearing tasks.
  853. * Have a go anyway.
  854. */
  855. if (!ok) {
  856. pr_debug("%s: cqhci: disable / re-enable\n", mmc_hostname(mmc));
  857. cqcfg = cqhci_readl(cq_host, CQHCI_CFG);
  858. cqcfg &= ~CQHCI_ENABLE;
  859. cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
  860. cqcfg |= CQHCI_ENABLE;
  861. cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
  862. /* Be sure that there are no tasks */
  863. ok = cqhci_halt(mmc, CQHCI_FINISH_HALT_TIMEOUT);
  864. if (!cqhci_clear_all_tasks(mmc, CQHCI_CLEAR_TIMEOUT))
  865. ok = false;
  866. WARN_ON(!ok);
  867. }
  868. cqhci_recover_mrqs(cq_host);
  869. WARN_ON(cq_host->qcnt);
  870. spin_lock_irqsave(&cq_host->lock, flags);
  871. cq_host->qcnt = 0;
  872. cq_host->recovery_halt = false;
  873. mmc->cqe_on = false;
  874. spin_unlock_irqrestore(&cq_host->lock, flags);
  875. /* Ensure all writes are done before interrupts are re-enabled */
  876. wmb();
  877. cqhci_writel(cq_host, CQHCI_IS_HAC | CQHCI_IS_TCL, CQHCI_IS);
  878. cqhci_set_irqs(cq_host, CQHCI_IS_MASK);
  879. pr_debug("%s: cqhci: recovery done\n", mmc_hostname(mmc));
  880. }
  881. static const struct mmc_cqe_ops cqhci_cqe_ops = {
  882. .cqe_enable = cqhci_enable,
  883. .cqe_disable = cqhci_disable,
  884. .cqe_request = cqhci_request,
  885. .cqe_post_req = cqhci_post_req,
  886. .cqe_off = cqhci_off,
  887. .cqe_wait_for_idle = cqhci_wait_for_idle,
  888. .cqe_timeout = cqhci_timeout,
  889. .cqe_recovery_start = cqhci_recovery_start,
  890. .cqe_recovery_finish = cqhci_recovery_finish,
  891. };
  892. struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev)
  893. {
  894. struct cqhci_host *cq_host;
  895. struct resource *cqhci_memres = NULL;
  896. /* check and setup CMDQ interface */
  897. cqhci_memres = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  898. "cqhci");
  899. if (!cqhci_memres) {
  900. dev_dbg(&pdev->dev, "CMDQ not supported\n");
  901. return ERR_PTR(-EINVAL);
  902. }
  903. cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
  904. if (!cq_host)
  905. return ERR_PTR(-ENOMEM);
  906. cq_host->mmio = devm_ioremap(&pdev->dev,
  907. cqhci_memres->start,
  908. resource_size(cqhci_memres));
  909. if (!cq_host->mmio) {
  910. dev_err(&pdev->dev, "failed to remap cqhci regs\n");
  911. return ERR_PTR(-EBUSY);
  912. }
  913. dev_dbg(&pdev->dev, "CMDQ ioremap: done\n");
  914. return cq_host;
  915. }
  916. EXPORT_SYMBOL(cqhci_pltfm_init);
  917. static unsigned int cqhci_ver_major(struct cqhci_host *cq_host)
  918. {
  919. return CQHCI_VER_MAJOR(cqhci_readl(cq_host, CQHCI_VER));
  920. }
  921. static unsigned int cqhci_ver_minor(struct cqhci_host *cq_host)
  922. {
  923. u32 ver = cqhci_readl(cq_host, CQHCI_VER);
  924. return CQHCI_VER_MINOR1(ver) * 10 + CQHCI_VER_MINOR2(ver);
  925. }
  926. int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc,
  927. bool dma64)
  928. {
  929. int err;
  930. cq_host->dma64 = dma64;
  931. cq_host->mmc = mmc;
  932. cq_host->mmc->cqe_private = cq_host;
  933. cq_host->num_slots = NUM_SLOTS;
  934. cq_host->dcmd_slot = DCMD_SLOT;
  935. mmc->cqe_ops = &cqhci_cqe_ops;
  936. mmc->cqe_qdepth = NUM_SLOTS;
  937. if (mmc->caps2 & MMC_CAP2_CQE_DCMD)
  938. mmc->cqe_qdepth -= 1;
  939. cq_host->slot = devm_kcalloc(mmc_dev(mmc), cq_host->num_slots,
  940. sizeof(*cq_host->slot), GFP_KERNEL);
  941. if (!cq_host->slot) {
  942. err = -ENOMEM;
  943. goto out_err;
  944. }
  945. err = cqhci_crypto_init(cq_host);
  946. if (err) {
  947. pr_err("%s: CQHCI crypto initialization failed\n",
  948. mmc_hostname(mmc));
  949. goto out_err;
  950. }
  951. spin_lock_init(&cq_host->lock);
  952. init_completion(&cq_host->halt_comp);
  953. init_waitqueue_head(&cq_host->wait_queue);
  954. pr_info("%s: CQHCI version %u.%02u\n",
  955. mmc_hostname(mmc), cqhci_ver_major(cq_host),
  956. cqhci_ver_minor(cq_host));
  957. return 0;
  958. out_err:
  959. pr_err("%s: CQHCI version %u.%02u failed to initialize, error %d\n",
  960. mmc_hostname(mmc), cqhci_ver_major(cq_host),
  961. cqhci_ver_minor(cq_host), err);
  962. return err;
  963. }
  964. EXPORT_SYMBOL(cqhci_init);
  965. MODULE_AUTHOR("Venkat Gopalakrishnan <venkatg@codeaurora.org>");
  966. MODULE_DESCRIPTION("Command Queue Host Controller Interface driver");
  967. MODULE_LICENSE("GPL v2");