cavium-octeon.c 8.4 KB

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  1. /*
  2. * Driver for MMC and SSD cards for Cavium OCTEON SOCs.
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 2012-2017 Cavium Inc.
  9. */
  10. #include <linux/dma-mapping.h>
  11. #include <linux/gpio/consumer.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/mmc/mmc.h>
  14. #include <linux/mmc/slot-gpio.h>
  15. #include <linux/module.h>
  16. #include <linux/of_platform.h>
  17. #include <asm/octeon/octeon.h>
  18. #include "cavium.h"
  19. #define CVMX_MIO_BOOT_CTL CVMX_ADD_IO_SEG(0x00011800000000D0ull)
  20. /*
  21. * The l2c* functions below are used for the EMMC-17978 workaround.
  22. *
  23. * Due to a bug in the design of the MMC bus hardware, the 2nd to last
  24. * cache block of a DMA read must be locked into the L2 Cache.
  25. * Otherwise, data corruption may occur.
  26. */
  27. static inline void *phys_to_ptr(u64 address)
  28. {
  29. return (void *)(address | (1ull << 63)); /* XKPHYS */
  30. }
  31. /*
  32. * Lock a single line into L2. The line is zeroed before locking
  33. * to make sure no dram accesses are made.
  34. */
  35. static void l2c_lock_line(u64 addr)
  36. {
  37. char *addr_ptr = phys_to_ptr(addr);
  38. asm volatile (
  39. "cache 31, %[line]" /* Unlock the line */
  40. ::[line] "m" (*addr_ptr));
  41. }
  42. /* Unlock a single line in the L2 cache. */
  43. static void l2c_unlock_line(u64 addr)
  44. {
  45. char *addr_ptr = phys_to_ptr(addr);
  46. asm volatile (
  47. "cache 23, %[line]" /* Unlock the line */
  48. ::[line] "m" (*addr_ptr));
  49. }
  50. /* Locks a memory region in the L2 cache. */
  51. static void l2c_lock_mem_region(u64 start, u64 len)
  52. {
  53. u64 end;
  54. /* Round start/end to cache line boundaries */
  55. end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE);
  56. start = ALIGN(start, CVMX_CACHE_LINE_SIZE);
  57. while (start <= end) {
  58. l2c_lock_line(start);
  59. start += CVMX_CACHE_LINE_SIZE;
  60. }
  61. asm volatile("sync");
  62. }
  63. /* Unlock a memory region in the L2 cache. */
  64. static void l2c_unlock_mem_region(u64 start, u64 len)
  65. {
  66. u64 end;
  67. /* Round start/end to cache line boundaries */
  68. end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE);
  69. start = ALIGN(start, CVMX_CACHE_LINE_SIZE);
  70. while (start <= end) {
  71. l2c_unlock_line(start);
  72. start += CVMX_CACHE_LINE_SIZE;
  73. }
  74. }
  75. static void octeon_mmc_acquire_bus(struct cvm_mmc_host *host)
  76. {
  77. if (!host->has_ciu3) {
  78. down(&octeon_bootbus_sem);
  79. /* For CN70XX, switch the MMC controller onto the bus. */
  80. if (OCTEON_IS_MODEL(OCTEON_CN70XX))
  81. writeq(0, (void __iomem *)CVMX_MIO_BOOT_CTL);
  82. } else {
  83. down(&host->mmc_serializer);
  84. }
  85. }
  86. static void octeon_mmc_release_bus(struct cvm_mmc_host *host)
  87. {
  88. if (!host->has_ciu3)
  89. up(&octeon_bootbus_sem);
  90. else
  91. up(&host->mmc_serializer);
  92. }
  93. static void octeon_mmc_int_enable(struct cvm_mmc_host *host, u64 val)
  94. {
  95. writeq(val, host->base + MIO_EMM_INT(host));
  96. if (!host->has_ciu3)
  97. writeq(val, host->base + MIO_EMM_INT_EN(host));
  98. }
  99. static void octeon_mmc_set_shared_power(struct cvm_mmc_host *host, int dir)
  100. {
  101. if (dir == 0)
  102. if (!atomic_dec_return(&host->shared_power_users))
  103. gpiod_set_value_cansleep(host->global_pwr_gpiod, 0);
  104. if (dir == 1)
  105. if (atomic_inc_return(&host->shared_power_users) == 1)
  106. gpiod_set_value_cansleep(host->global_pwr_gpiod, 1);
  107. }
  108. static void octeon_mmc_dmar_fixup(struct cvm_mmc_host *host,
  109. struct mmc_command *cmd,
  110. struct mmc_data *data,
  111. u64 addr)
  112. {
  113. if (cmd->opcode != MMC_WRITE_MULTIPLE_BLOCK)
  114. return;
  115. if (data->blksz * data->blocks <= 1024)
  116. return;
  117. host->n_minus_one = addr + (data->blksz * data->blocks) - 1024;
  118. l2c_lock_mem_region(host->n_minus_one, 512);
  119. }
  120. static void octeon_mmc_dmar_fixup_done(struct cvm_mmc_host *host)
  121. {
  122. if (!host->n_minus_one)
  123. return;
  124. l2c_unlock_mem_region(host->n_minus_one, 512);
  125. host->n_minus_one = 0;
  126. }
  127. static int octeon_mmc_probe(struct platform_device *pdev)
  128. {
  129. struct device_node *cn, *node = pdev->dev.of_node;
  130. struct cvm_mmc_host *host;
  131. void __iomem *base;
  132. int mmc_irq[9];
  133. int i, ret = 0;
  134. u64 val;
  135. host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
  136. if (!host)
  137. return -ENOMEM;
  138. spin_lock_init(&host->irq_handler_lock);
  139. sema_init(&host->mmc_serializer, 1);
  140. host->dev = &pdev->dev;
  141. host->acquire_bus = octeon_mmc_acquire_bus;
  142. host->release_bus = octeon_mmc_release_bus;
  143. host->int_enable = octeon_mmc_int_enable;
  144. host->set_shared_power = octeon_mmc_set_shared_power;
  145. if (OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
  146. OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
  147. host->dmar_fixup = octeon_mmc_dmar_fixup;
  148. host->dmar_fixup_done = octeon_mmc_dmar_fixup_done;
  149. }
  150. host->sys_freq = octeon_get_io_clock_rate();
  151. if (of_device_is_compatible(node, "cavium,octeon-7890-mmc")) {
  152. host->big_dma_addr = true;
  153. host->need_irq_handler_lock = true;
  154. host->has_ciu3 = true;
  155. host->use_sg = true;
  156. /*
  157. * First seven are the EMM_INT bits 0..6, then two for
  158. * the EMM_DMA_INT bits
  159. */
  160. for (i = 0; i < 9; i++) {
  161. mmc_irq[i] = platform_get_irq(pdev, i);
  162. if (mmc_irq[i] < 0)
  163. return mmc_irq[i];
  164. /* work around legacy u-boot device trees */
  165. irq_set_irq_type(mmc_irq[i], IRQ_TYPE_EDGE_RISING);
  166. }
  167. } else {
  168. host->big_dma_addr = false;
  169. host->need_irq_handler_lock = false;
  170. host->has_ciu3 = false;
  171. /* First one is EMM second DMA */
  172. for (i = 0; i < 2; i++) {
  173. mmc_irq[i] = platform_get_irq(pdev, i);
  174. if (mmc_irq[i] < 0)
  175. return mmc_irq[i];
  176. }
  177. }
  178. host->last_slot = -1;
  179. base = devm_platform_ioremap_resource(pdev, 0);
  180. if (IS_ERR(base))
  181. return PTR_ERR(base);
  182. host->base = base;
  183. host->reg_off = 0;
  184. base = devm_platform_ioremap_resource(pdev, 1);
  185. if (IS_ERR(base))
  186. return PTR_ERR(base);
  187. host->dma_base = base;
  188. /*
  189. * To keep the register addresses shared we intentionaly use
  190. * a negative offset here, first register used on Octeon therefore
  191. * starts at 0x20 (MIO_EMM_DMA_CFG).
  192. */
  193. host->reg_off_dma = -0x20;
  194. ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
  195. if (ret)
  196. return ret;
  197. /*
  198. * Clear out any pending interrupts that may be left over from
  199. * bootloader.
  200. */
  201. val = readq(host->base + MIO_EMM_INT(host));
  202. writeq(val, host->base + MIO_EMM_INT(host));
  203. if (host->has_ciu3) {
  204. /* Only CMD_DONE, DMA_DONE, CMD_ERR, DMA_ERR */
  205. for (i = 1; i <= 4; i++) {
  206. ret = devm_request_irq(&pdev->dev, mmc_irq[i],
  207. cvm_mmc_interrupt,
  208. 0, cvm_mmc_irq_names[i], host);
  209. if (ret < 0) {
  210. dev_err(&pdev->dev, "Error: devm_request_irq %d\n",
  211. mmc_irq[i]);
  212. return ret;
  213. }
  214. }
  215. } else {
  216. ret = devm_request_irq(&pdev->dev, mmc_irq[0],
  217. cvm_mmc_interrupt, 0, KBUILD_MODNAME,
  218. host);
  219. if (ret < 0) {
  220. dev_err(&pdev->dev, "Error: devm_request_irq %d\n",
  221. mmc_irq[0]);
  222. return ret;
  223. }
  224. }
  225. host->global_pwr_gpiod = devm_gpiod_get_optional(&pdev->dev,
  226. "power",
  227. GPIOD_OUT_HIGH);
  228. if (IS_ERR(host->global_pwr_gpiod)) {
  229. dev_err(&pdev->dev, "Invalid power GPIO\n");
  230. return PTR_ERR(host->global_pwr_gpiod);
  231. }
  232. platform_set_drvdata(pdev, host);
  233. i = 0;
  234. for_each_child_of_node(node, cn) {
  235. host->slot_pdev[i] =
  236. of_platform_device_create(cn, NULL, &pdev->dev);
  237. if (!host->slot_pdev[i]) {
  238. i++;
  239. continue;
  240. }
  241. ret = cvm_mmc_of_slot_probe(&host->slot_pdev[i]->dev, host);
  242. if (ret) {
  243. dev_err(&pdev->dev, "Error populating slots\n");
  244. octeon_mmc_set_shared_power(host, 0);
  245. goto error;
  246. }
  247. i++;
  248. }
  249. return 0;
  250. error:
  251. for (i = 0; i < CAVIUM_MAX_MMC; i++) {
  252. if (host->slot[i])
  253. cvm_mmc_of_slot_remove(host->slot[i]);
  254. if (host->slot_pdev[i])
  255. of_platform_device_destroy(&host->slot_pdev[i]->dev, NULL);
  256. }
  257. return ret;
  258. }
  259. static int octeon_mmc_remove(struct platform_device *pdev)
  260. {
  261. struct cvm_mmc_host *host = platform_get_drvdata(pdev);
  262. u64 dma_cfg;
  263. int i;
  264. for (i = 0; i < CAVIUM_MAX_MMC; i++)
  265. if (host->slot[i])
  266. cvm_mmc_of_slot_remove(host->slot[i]);
  267. dma_cfg = readq(host->dma_base + MIO_EMM_DMA_CFG(host));
  268. dma_cfg &= ~MIO_EMM_DMA_CFG_EN;
  269. writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host));
  270. octeon_mmc_set_shared_power(host, 0);
  271. return 0;
  272. }
  273. static const struct of_device_id octeon_mmc_match[] = {
  274. {
  275. .compatible = "cavium,octeon-6130-mmc",
  276. },
  277. {
  278. .compatible = "cavium,octeon-7890-mmc",
  279. },
  280. {},
  281. };
  282. MODULE_DEVICE_TABLE(of, octeon_mmc_match);
  283. static struct platform_driver octeon_mmc_driver = {
  284. .probe = octeon_mmc_probe,
  285. .remove = octeon_mmc_remove,
  286. .driver = {
  287. .name = KBUILD_MODNAME,
  288. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  289. .of_match_table = octeon_mmc_match,
  290. },
  291. };
  292. module_platform_driver(octeon_mmc_driver);
  293. MODULE_AUTHOR("Cavium Inc. <support@cavium.com>");
  294. MODULE_DESCRIPTION("Low-level driver for Cavium OCTEON MMC/SSD card");
  295. MODULE_LICENSE("GPL");