au1xmmc.c 29 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
  4. *
  5. * Copyright (c) 2005, Advanced Micro Devices, Inc.
  6. *
  7. * Developed with help from the 2.4.30 MMC AU1XXX controller including
  8. * the following copyright notices:
  9. * Copyright (c) 2003-2004 Embedded Edge, LLC.
  10. * Portions Copyright (C) 2002 Embedix, Inc
  11. * Copyright 2002 Hewlett-Packard Company
  12. * 2.6 version of this driver inspired by:
  13. * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
  14. * All Rights Reserved.
  15. * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
  16. * All Rights Reserved.
  17. *
  18. */
  19. /* Why don't we use the SD controllers' carddetect feature?
  20. *
  21. * From the AU1100 MMC application guide:
  22. * If the Au1100-based design is intended to support both MultiMediaCards
  23. * and 1- or 4-data bit SecureDigital cards, then the solution is to
  24. * connect a weak (560KOhm) pull-up resistor to connector pin 1.
  25. * In doing so, a MMC card never enters SPI-mode communications,
  26. * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
  27. * (the low to high transition will not occur).
  28. */
  29. #include <linux/clk.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/mm.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/scatterlist.h>
  37. #include <linux/highmem.h>
  38. #include <linux/leds.h>
  39. #include <linux/mmc/host.h>
  40. #include <linux/slab.h>
  41. #include <asm/io.h>
  42. #include <asm/mach-au1x00/au1000.h>
  43. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  44. #include <asm/mach-au1x00/au1100_mmc.h>
  45. #define DRIVER_NAME "au1xxx-mmc"
  46. /* Set this to enable special debugging macros */
  47. /* #define DEBUG */
  48. #ifdef DEBUG
  49. #define DBG(fmt, idx, args...) \
  50. pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args)
  51. #else
  52. #define DBG(fmt, idx, args...) do {} while (0)
  53. #endif
  54. /* Hardware definitions */
  55. #define AU1XMMC_DESCRIPTOR_COUNT 1
  56. /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
  57. #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff
  58. #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff
  59. #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
  60. MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
  61. MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
  62. /* This gives us a hard value for the stop command that we can write directly
  63. * to the command register.
  64. */
  65. #define STOP_CMD \
  66. (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
  67. /* This is the set of interrupts that we configure by default. */
  68. #define AU1XMMC_INTERRUPTS \
  69. (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \
  70. SD_CONFIG_CR | SD_CONFIG_I)
  71. /* The poll event (looking for insert/remove events runs twice a second. */
  72. #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
  73. struct au1xmmc_host {
  74. struct mmc_host *mmc;
  75. struct mmc_request *mrq;
  76. u32 flags;
  77. void __iomem *iobase;
  78. u32 clock;
  79. u32 bus_width;
  80. u32 power_mode;
  81. int status;
  82. struct {
  83. int len;
  84. int dir;
  85. } dma;
  86. struct {
  87. int index;
  88. int offset;
  89. int len;
  90. } pio;
  91. u32 tx_chan;
  92. u32 rx_chan;
  93. int irq;
  94. struct tasklet_struct finish_task;
  95. struct tasklet_struct data_task;
  96. struct au1xmmc_platform_data *platdata;
  97. struct platform_device *pdev;
  98. struct resource *ioarea;
  99. struct clk *clk;
  100. };
  101. /* Status flags used by the host structure */
  102. #define HOST_F_XMIT 0x0001
  103. #define HOST_F_RECV 0x0002
  104. #define HOST_F_DMA 0x0010
  105. #define HOST_F_DBDMA 0x0020
  106. #define HOST_F_ACTIVE 0x0100
  107. #define HOST_F_STOP 0x1000
  108. #define HOST_S_IDLE 0x0001
  109. #define HOST_S_CMD 0x0002
  110. #define HOST_S_DATA 0x0003
  111. #define HOST_S_STOP 0x0004
  112. /* Easy access macros */
  113. #define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
  114. #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
  115. #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
  116. #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
  117. #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
  118. #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
  119. #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
  120. #define HOST_CMD(h) ((h)->iobase + SD_CMD)
  121. #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
  122. #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
  123. #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
  124. #define DMA_CHANNEL(h) \
  125. (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
  126. static inline int has_dbdma(void)
  127. {
  128. switch (alchemy_get_cputype()) {
  129. case ALCHEMY_CPU_AU1200:
  130. case ALCHEMY_CPU_AU1300:
  131. return 1;
  132. default:
  133. return 0;
  134. }
  135. }
  136. static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
  137. {
  138. u32 val = __raw_readl(HOST_CONFIG(host));
  139. val |= mask;
  140. __raw_writel(val, HOST_CONFIG(host));
  141. wmb(); /* drain writebuffer */
  142. }
  143. static inline void FLUSH_FIFO(struct au1xmmc_host *host)
  144. {
  145. u32 val = __raw_readl(HOST_CONFIG2(host));
  146. __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
  147. wmb(); /* drain writebuffer */
  148. mdelay(1);
  149. /* SEND_STOP will turn off clock control - this re-enables it */
  150. val &= ~SD_CONFIG2_DF;
  151. __raw_writel(val, HOST_CONFIG2(host));
  152. wmb(); /* drain writebuffer */
  153. }
  154. static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
  155. {
  156. u32 val = __raw_readl(HOST_CONFIG(host));
  157. val &= ~mask;
  158. __raw_writel(val, HOST_CONFIG(host));
  159. wmb(); /* drain writebuffer */
  160. }
  161. static inline void SEND_STOP(struct au1xmmc_host *host)
  162. {
  163. u32 config2;
  164. WARN_ON(host->status != HOST_S_DATA);
  165. host->status = HOST_S_STOP;
  166. config2 = __raw_readl(HOST_CONFIG2(host));
  167. __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
  168. wmb(); /* drain writebuffer */
  169. /* Send the stop command */
  170. __raw_writel(STOP_CMD, HOST_CMD(host));
  171. wmb(); /* drain writebuffer */
  172. }
  173. static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
  174. {
  175. if (host->platdata && host->platdata->set_power)
  176. host->platdata->set_power(host->mmc, state);
  177. }
  178. static int au1xmmc_card_inserted(struct mmc_host *mmc)
  179. {
  180. struct au1xmmc_host *host = mmc_priv(mmc);
  181. if (host->platdata && host->platdata->card_inserted)
  182. return !!host->platdata->card_inserted(host->mmc);
  183. return -ENOSYS;
  184. }
  185. static int au1xmmc_card_readonly(struct mmc_host *mmc)
  186. {
  187. struct au1xmmc_host *host = mmc_priv(mmc);
  188. if (host->platdata && host->platdata->card_readonly)
  189. return !!host->platdata->card_readonly(mmc);
  190. return -ENOSYS;
  191. }
  192. static void au1xmmc_finish_request(struct au1xmmc_host *host)
  193. {
  194. struct mmc_request *mrq = host->mrq;
  195. host->mrq = NULL;
  196. host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
  197. host->dma.len = 0;
  198. host->dma.dir = 0;
  199. host->pio.index = 0;
  200. host->pio.offset = 0;
  201. host->pio.len = 0;
  202. host->status = HOST_S_IDLE;
  203. mmc_request_done(host->mmc, mrq);
  204. }
  205. static void au1xmmc_tasklet_finish(unsigned long param)
  206. {
  207. struct au1xmmc_host *host = (struct au1xmmc_host *) param;
  208. au1xmmc_finish_request(host);
  209. }
  210. static int au1xmmc_send_command(struct au1xmmc_host *host,
  211. struct mmc_command *cmd, struct mmc_data *data)
  212. {
  213. u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
  214. switch (mmc_resp_type(cmd)) {
  215. case MMC_RSP_NONE:
  216. break;
  217. case MMC_RSP_R1:
  218. mmccmd |= SD_CMD_RT_1;
  219. break;
  220. case MMC_RSP_R1B:
  221. mmccmd |= SD_CMD_RT_1B;
  222. break;
  223. case MMC_RSP_R2:
  224. mmccmd |= SD_CMD_RT_2;
  225. break;
  226. case MMC_RSP_R3:
  227. mmccmd |= SD_CMD_RT_3;
  228. break;
  229. default:
  230. pr_info("au1xmmc: unhandled response type %02x\n",
  231. mmc_resp_type(cmd));
  232. return -EINVAL;
  233. }
  234. if (data) {
  235. if (data->flags & MMC_DATA_READ) {
  236. if (data->blocks > 1)
  237. mmccmd |= SD_CMD_CT_4;
  238. else
  239. mmccmd |= SD_CMD_CT_2;
  240. } else if (data->flags & MMC_DATA_WRITE) {
  241. if (data->blocks > 1)
  242. mmccmd |= SD_CMD_CT_3;
  243. else
  244. mmccmd |= SD_CMD_CT_1;
  245. }
  246. }
  247. __raw_writel(cmd->arg, HOST_CMDARG(host));
  248. wmb(); /* drain writebuffer */
  249. __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
  250. wmb(); /* drain writebuffer */
  251. /* Wait for the command to go on the line */
  252. while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO)
  253. /* nop */;
  254. return 0;
  255. }
  256. static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
  257. {
  258. struct mmc_request *mrq = host->mrq;
  259. struct mmc_data *data;
  260. u32 crc;
  261. WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
  262. if (host->mrq == NULL)
  263. return;
  264. data = mrq->cmd->data;
  265. if (status == 0)
  266. status = __raw_readl(HOST_STATUS(host));
  267. /* The transaction is really over when the SD_STATUS_DB bit is clear */
  268. while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
  269. status = __raw_readl(HOST_STATUS(host));
  270. data->error = 0;
  271. dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
  272. /* Process any errors */
  273. crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
  274. if (host->flags & HOST_F_XMIT)
  275. crc |= ((status & 0x07) == 0x02) ? 0 : 1;
  276. if (crc)
  277. data->error = -EILSEQ;
  278. /* Clear the CRC bits */
  279. __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
  280. data->bytes_xfered = 0;
  281. if (!data->error) {
  282. if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
  283. u32 chan = DMA_CHANNEL(host);
  284. chan_tab_t *c = *((chan_tab_t **)chan);
  285. au1x_dma_chan_t *cp = c->chan_ptr;
  286. data->bytes_xfered = cp->ddma_bytecnt;
  287. } else
  288. data->bytes_xfered =
  289. (data->blocks * data->blksz) - host->pio.len;
  290. }
  291. au1xmmc_finish_request(host);
  292. }
  293. static void au1xmmc_tasklet_data(unsigned long param)
  294. {
  295. struct au1xmmc_host *host = (struct au1xmmc_host *)param;
  296. u32 status = __raw_readl(HOST_STATUS(host));
  297. au1xmmc_data_complete(host, status);
  298. }
  299. #define AU1XMMC_MAX_TRANSFER 8
  300. static void au1xmmc_send_pio(struct au1xmmc_host *host)
  301. {
  302. struct mmc_data *data;
  303. int sg_len, max, count;
  304. unsigned char *sg_ptr, val;
  305. u32 status;
  306. struct scatterlist *sg;
  307. data = host->mrq->data;
  308. if (!(host->flags & HOST_F_XMIT))
  309. return;
  310. /* This is the pointer to the data buffer */
  311. sg = &data->sg[host->pio.index];
  312. sg_ptr = kmap_atomic(sg_page(sg)) + sg->offset + host->pio.offset;
  313. /* This is the space left inside the buffer */
  314. sg_len = data->sg[host->pio.index].length - host->pio.offset;
  315. /* Check if we need less than the size of the sg_buffer */
  316. max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
  317. if (max > AU1XMMC_MAX_TRANSFER)
  318. max = AU1XMMC_MAX_TRANSFER;
  319. for (count = 0; count < max; count++) {
  320. status = __raw_readl(HOST_STATUS(host));
  321. if (!(status & SD_STATUS_TH))
  322. break;
  323. val = sg_ptr[count];
  324. __raw_writel((unsigned long)val, HOST_TXPORT(host));
  325. wmb(); /* drain writebuffer */
  326. }
  327. kunmap_atomic(sg_ptr);
  328. host->pio.len -= count;
  329. host->pio.offset += count;
  330. if (count == sg_len) {
  331. host->pio.index++;
  332. host->pio.offset = 0;
  333. }
  334. if (host->pio.len == 0) {
  335. IRQ_OFF(host, SD_CONFIG_TH);
  336. if (host->flags & HOST_F_STOP)
  337. SEND_STOP(host);
  338. tasklet_schedule(&host->data_task);
  339. }
  340. }
  341. static void au1xmmc_receive_pio(struct au1xmmc_host *host)
  342. {
  343. struct mmc_data *data;
  344. int max, count, sg_len = 0;
  345. unsigned char *sg_ptr = NULL;
  346. u32 status, val;
  347. struct scatterlist *sg;
  348. data = host->mrq->data;
  349. if (!(host->flags & HOST_F_RECV))
  350. return;
  351. max = host->pio.len;
  352. if (host->pio.index < host->dma.len) {
  353. sg = &data->sg[host->pio.index];
  354. sg_ptr = kmap_atomic(sg_page(sg)) + sg->offset + host->pio.offset;
  355. /* This is the space left inside the buffer */
  356. sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
  357. /* Check if we need less than the size of the sg_buffer */
  358. if (sg_len < max)
  359. max = sg_len;
  360. }
  361. if (max > AU1XMMC_MAX_TRANSFER)
  362. max = AU1XMMC_MAX_TRANSFER;
  363. for (count = 0; count < max; count++) {
  364. status = __raw_readl(HOST_STATUS(host));
  365. if (!(status & SD_STATUS_NE))
  366. break;
  367. if (status & SD_STATUS_RC) {
  368. DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
  369. host->pio.len, count);
  370. break;
  371. }
  372. if (status & SD_STATUS_RO) {
  373. DBG("RX Overrun [%d + %d]\n", host->pdev->id,
  374. host->pio.len, count);
  375. break;
  376. }
  377. else if (status & SD_STATUS_RU) {
  378. DBG("RX Underrun [%d + %d]\n", host->pdev->id,
  379. host->pio.len, count);
  380. break;
  381. }
  382. val = __raw_readl(HOST_RXPORT(host));
  383. if (sg_ptr)
  384. sg_ptr[count] = (unsigned char)(val & 0xFF);
  385. }
  386. if (sg_ptr)
  387. kunmap_atomic(sg_ptr);
  388. host->pio.len -= count;
  389. host->pio.offset += count;
  390. if (sg_len && count == sg_len) {
  391. host->pio.index++;
  392. host->pio.offset = 0;
  393. }
  394. if (host->pio.len == 0) {
  395. /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
  396. IRQ_OFF(host, SD_CONFIG_NE);
  397. if (host->flags & HOST_F_STOP)
  398. SEND_STOP(host);
  399. tasklet_schedule(&host->data_task);
  400. }
  401. }
  402. /* This is called when a command has been completed - grab the response
  403. * and check for errors. Then start the data transfer if it is indicated.
  404. */
  405. static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
  406. {
  407. struct mmc_request *mrq = host->mrq;
  408. struct mmc_command *cmd;
  409. u32 r[4];
  410. int i, trans;
  411. if (!host->mrq)
  412. return;
  413. cmd = mrq->cmd;
  414. cmd->error = 0;
  415. if (cmd->flags & MMC_RSP_PRESENT) {
  416. if (cmd->flags & MMC_RSP_136) {
  417. r[0] = __raw_readl(host->iobase + SD_RESP3);
  418. r[1] = __raw_readl(host->iobase + SD_RESP2);
  419. r[2] = __raw_readl(host->iobase + SD_RESP1);
  420. r[3] = __raw_readl(host->iobase + SD_RESP0);
  421. /* The CRC is omitted from the response, so really
  422. * we only got 120 bytes, but the engine expects
  423. * 128 bits, so we have to shift things up.
  424. */
  425. for (i = 0; i < 4; i++) {
  426. cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
  427. if (i != 3)
  428. cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
  429. }
  430. } else {
  431. /* Techincally, we should be getting all 48 bits of
  432. * the response (SD_RESP1 + SD_RESP2), but because
  433. * our response omits the CRC, our data ends up
  434. * being shifted 8 bits to the right. In this case,
  435. * that means that the OSR data starts at bit 31,
  436. * so we can just read RESP0 and return that.
  437. */
  438. cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0);
  439. }
  440. }
  441. /* Figure out errors */
  442. if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
  443. cmd->error = -EILSEQ;
  444. trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
  445. if (!trans || cmd->error) {
  446. IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
  447. tasklet_schedule(&host->finish_task);
  448. return;
  449. }
  450. host->status = HOST_S_DATA;
  451. if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) {
  452. u32 channel = DMA_CHANNEL(host);
  453. /* Start the DBDMA as soon as the buffer gets something in it */
  454. if (host->flags & HOST_F_RECV) {
  455. u32 mask = SD_STATUS_DB | SD_STATUS_NE;
  456. while((status & mask) != mask)
  457. status = __raw_readl(HOST_STATUS(host));
  458. }
  459. au1xxx_dbdma_start(channel);
  460. }
  461. }
  462. static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
  463. {
  464. unsigned int pbus = clk_get_rate(host->clk);
  465. unsigned int divisor = ((pbus / rate) / 2) - 1;
  466. u32 config;
  467. config = __raw_readl(HOST_CONFIG(host));
  468. config &= ~(SD_CONFIG_DIV);
  469. config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
  470. __raw_writel(config, HOST_CONFIG(host));
  471. wmb(); /* drain writebuffer */
  472. }
  473. static int au1xmmc_prepare_data(struct au1xmmc_host *host,
  474. struct mmc_data *data)
  475. {
  476. int datalen = data->blocks * data->blksz;
  477. if (data->flags & MMC_DATA_READ)
  478. host->flags |= HOST_F_RECV;
  479. else
  480. host->flags |= HOST_F_XMIT;
  481. if (host->mrq->stop)
  482. host->flags |= HOST_F_STOP;
  483. host->dma.dir = DMA_BIDIRECTIONAL;
  484. host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
  485. data->sg_len, host->dma.dir);
  486. if (host->dma.len == 0)
  487. return -ETIMEDOUT;
  488. __raw_writel(data->blksz - 1, HOST_BLKSIZE(host));
  489. if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
  490. int i;
  491. u32 channel = DMA_CHANNEL(host);
  492. au1xxx_dbdma_stop(channel);
  493. for (i = 0; i < host->dma.len; i++) {
  494. u32 ret = 0, flags = DDMA_FLAGS_NOIE;
  495. struct scatterlist *sg = &data->sg[i];
  496. int sg_len = sg->length;
  497. int len = (datalen > sg_len) ? sg_len : datalen;
  498. if (i == host->dma.len - 1)
  499. flags = DDMA_FLAGS_IE;
  500. if (host->flags & HOST_F_XMIT) {
  501. ret = au1xxx_dbdma_put_source(channel,
  502. sg_phys(sg), len, flags);
  503. } else {
  504. ret = au1xxx_dbdma_put_dest(channel,
  505. sg_phys(sg), len, flags);
  506. }
  507. if (!ret)
  508. goto dataerr;
  509. datalen -= len;
  510. }
  511. } else {
  512. host->pio.index = 0;
  513. host->pio.offset = 0;
  514. host->pio.len = datalen;
  515. if (host->flags & HOST_F_XMIT)
  516. IRQ_ON(host, SD_CONFIG_TH);
  517. else
  518. IRQ_ON(host, SD_CONFIG_NE);
  519. /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
  520. }
  521. return 0;
  522. dataerr:
  523. dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  524. host->dma.dir);
  525. return -ETIMEDOUT;
  526. }
  527. /* This actually starts a command or data transaction */
  528. static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
  529. {
  530. struct au1xmmc_host *host = mmc_priv(mmc);
  531. int ret = 0;
  532. WARN_ON(irqs_disabled());
  533. WARN_ON(host->status != HOST_S_IDLE);
  534. host->mrq = mrq;
  535. host->status = HOST_S_CMD;
  536. /* fail request immediately if no card is present */
  537. if (0 == au1xmmc_card_inserted(mmc)) {
  538. mrq->cmd->error = -ENOMEDIUM;
  539. au1xmmc_finish_request(host);
  540. return;
  541. }
  542. if (mrq->data) {
  543. FLUSH_FIFO(host);
  544. ret = au1xmmc_prepare_data(host, mrq->data);
  545. }
  546. if (!ret)
  547. ret = au1xmmc_send_command(host, mrq->cmd, mrq->data);
  548. if (ret) {
  549. mrq->cmd->error = ret;
  550. au1xmmc_finish_request(host);
  551. }
  552. }
  553. static void au1xmmc_reset_controller(struct au1xmmc_host *host)
  554. {
  555. /* Apply the clock */
  556. __raw_writel(SD_ENABLE_CE, HOST_ENABLE(host));
  557. wmb(); /* drain writebuffer */
  558. mdelay(1);
  559. __raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
  560. wmb(); /* drain writebuffer */
  561. mdelay(5);
  562. __raw_writel(~0, HOST_STATUS(host));
  563. wmb(); /* drain writebuffer */
  564. __raw_writel(0, HOST_BLKSIZE(host));
  565. __raw_writel(0x001fffff, HOST_TIMEOUT(host));
  566. wmb(); /* drain writebuffer */
  567. __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
  568. wmb(); /* drain writebuffer */
  569. __raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
  570. wmb(); /* drain writebuffer */
  571. mdelay(1);
  572. __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
  573. wmb(); /* drain writebuffer */
  574. /* Configure interrupts */
  575. __raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
  576. wmb(); /* drain writebuffer */
  577. }
  578. static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  579. {
  580. struct au1xmmc_host *host = mmc_priv(mmc);
  581. u32 config2;
  582. if (ios->power_mode == MMC_POWER_OFF)
  583. au1xmmc_set_power(host, 0);
  584. else if (ios->power_mode == MMC_POWER_ON) {
  585. au1xmmc_set_power(host, 1);
  586. }
  587. if (ios->clock && ios->clock != host->clock) {
  588. au1xmmc_set_clock(host, ios->clock);
  589. host->clock = ios->clock;
  590. }
  591. config2 = __raw_readl(HOST_CONFIG2(host));
  592. switch (ios->bus_width) {
  593. case MMC_BUS_WIDTH_8:
  594. config2 |= SD_CONFIG2_BB;
  595. break;
  596. case MMC_BUS_WIDTH_4:
  597. config2 &= ~SD_CONFIG2_BB;
  598. config2 |= SD_CONFIG2_WB;
  599. break;
  600. case MMC_BUS_WIDTH_1:
  601. config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
  602. break;
  603. }
  604. __raw_writel(config2, HOST_CONFIG2(host));
  605. wmb(); /* drain writebuffer */
  606. }
  607. #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
  608. #define STATUS_DATA_IN (SD_STATUS_NE)
  609. #define STATUS_DATA_OUT (SD_STATUS_TH)
  610. static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
  611. {
  612. struct au1xmmc_host *host = dev_id;
  613. u32 status;
  614. status = __raw_readl(HOST_STATUS(host));
  615. if (!(status & SD_STATUS_I))
  616. return IRQ_NONE; /* not ours */
  617. if (status & SD_STATUS_SI) /* SDIO */
  618. mmc_signal_sdio_irq(host->mmc);
  619. if (host->mrq && (status & STATUS_TIMEOUT)) {
  620. if (status & SD_STATUS_RAT)
  621. host->mrq->cmd->error = -ETIMEDOUT;
  622. else if (status & SD_STATUS_DT)
  623. host->mrq->data->error = -ETIMEDOUT;
  624. /* In PIO mode, interrupts might still be enabled */
  625. IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
  626. /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
  627. tasklet_schedule(&host->finish_task);
  628. }
  629. #if 0
  630. else if (status & SD_STATUS_DD) {
  631. /* Sometimes we get a DD before a NE in PIO mode */
  632. if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
  633. au1xmmc_receive_pio(host);
  634. else {
  635. au1xmmc_data_complete(host, status);
  636. /* tasklet_schedule(&host->data_task); */
  637. }
  638. }
  639. #endif
  640. else if (status & SD_STATUS_CR) {
  641. if (host->status == HOST_S_CMD)
  642. au1xmmc_cmd_complete(host, status);
  643. } else if (!(host->flags & HOST_F_DMA)) {
  644. if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
  645. au1xmmc_send_pio(host);
  646. else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
  647. au1xmmc_receive_pio(host);
  648. } else if (status & 0x203F3C70) {
  649. DBG("Unhandled status %8.8x\n", host->pdev->id,
  650. status);
  651. }
  652. __raw_writel(status, HOST_STATUS(host));
  653. wmb(); /* drain writebuffer */
  654. return IRQ_HANDLED;
  655. }
  656. /* 8bit memory DMA device */
  657. static dbdev_tab_t au1xmmc_mem_dbdev = {
  658. .dev_id = DSCR_CMD0_ALWAYS,
  659. .dev_flags = DEV_FLAGS_ANYUSE,
  660. .dev_tsize = 0,
  661. .dev_devwidth = 8,
  662. .dev_physaddr = 0x00000000,
  663. .dev_intlevel = 0,
  664. .dev_intpolarity = 0,
  665. };
  666. static int memid;
  667. static void au1xmmc_dbdma_callback(int irq, void *dev_id)
  668. {
  669. struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
  670. /* Avoid spurious interrupts */
  671. if (!host->mrq)
  672. return;
  673. if (host->flags & HOST_F_STOP)
  674. SEND_STOP(host);
  675. tasklet_schedule(&host->data_task);
  676. }
  677. static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
  678. {
  679. struct resource *res;
  680. int txid, rxid;
  681. res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
  682. if (!res)
  683. return -ENODEV;
  684. txid = res->start;
  685. res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
  686. if (!res)
  687. return -ENODEV;
  688. rxid = res->start;
  689. if (!memid)
  690. return -ENODEV;
  691. host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
  692. au1xmmc_dbdma_callback, (void *)host);
  693. if (!host->tx_chan) {
  694. dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
  695. return -ENODEV;
  696. }
  697. host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
  698. au1xmmc_dbdma_callback, (void *)host);
  699. if (!host->rx_chan) {
  700. dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
  701. au1xxx_dbdma_chan_free(host->tx_chan);
  702. return -ENODEV;
  703. }
  704. au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
  705. au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
  706. au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
  707. au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
  708. /* DBDMA is good to go */
  709. host->flags |= HOST_F_DMA | HOST_F_DBDMA;
  710. return 0;
  711. }
  712. static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
  713. {
  714. if (host->flags & HOST_F_DMA) {
  715. host->flags &= ~HOST_F_DMA;
  716. au1xxx_dbdma_chan_free(host->tx_chan);
  717. au1xxx_dbdma_chan_free(host->rx_chan);
  718. }
  719. }
  720. static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
  721. {
  722. struct au1xmmc_host *host = mmc_priv(mmc);
  723. if (en)
  724. IRQ_ON(host, SD_CONFIG_SI);
  725. else
  726. IRQ_OFF(host, SD_CONFIG_SI);
  727. }
  728. static const struct mmc_host_ops au1xmmc_ops = {
  729. .request = au1xmmc_request,
  730. .set_ios = au1xmmc_set_ios,
  731. .get_ro = au1xmmc_card_readonly,
  732. .get_cd = au1xmmc_card_inserted,
  733. .enable_sdio_irq = au1xmmc_enable_sdio_irq,
  734. };
  735. static int au1xmmc_probe(struct platform_device *pdev)
  736. {
  737. struct mmc_host *mmc;
  738. struct au1xmmc_host *host;
  739. struct resource *r;
  740. int ret, iflag;
  741. mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
  742. if (!mmc) {
  743. dev_err(&pdev->dev, "no memory for mmc_host\n");
  744. ret = -ENOMEM;
  745. goto out0;
  746. }
  747. host = mmc_priv(mmc);
  748. host->mmc = mmc;
  749. host->platdata = pdev->dev.platform_data;
  750. host->pdev = pdev;
  751. ret = -ENODEV;
  752. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  753. if (!r) {
  754. dev_err(&pdev->dev, "no mmio defined\n");
  755. goto out1;
  756. }
  757. host->ioarea = request_mem_region(r->start, resource_size(r),
  758. pdev->name);
  759. if (!host->ioarea) {
  760. dev_err(&pdev->dev, "mmio already in use\n");
  761. goto out1;
  762. }
  763. host->iobase = ioremap(r->start, 0x3c);
  764. if (!host->iobase) {
  765. dev_err(&pdev->dev, "cannot remap mmio\n");
  766. goto out2;
  767. }
  768. host->irq = platform_get_irq(pdev, 0);
  769. if (host->irq < 0)
  770. goto out3;
  771. mmc->ops = &au1xmmc_ops;
  772. mmc->f_min = 450000;
  773. mmc->f_max = 24000000;
  774. mmc->max_blk_size = 2048;
  775. mmc->max_blk_count = 512;
  776. mmc->ocr_avail = AU1XMMC_OCR;
  777. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
  778. mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
  779. iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */
  780. switch (alchemy_get_cputype()) {
  781. case ALCHEMY_CPU_AU1100:
  782. mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
  783. break;
  784. case ALCHEMY_CPU_AU1200:
  785. mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
  786. break;
  787. case ALCHEMY_CPU_AU1300:
  788. iflag = 0; /* nothing is shared */
  789. mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
  790. mmc->f_max = 52000000;
  791. if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
  792. mmc->caps |= MMC_CAP_8_BIT_DATA;
  793. break;
  794. }
  795. ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
  796. if (ret) {
  797. dev_err(&pdev->dev, "cannot grab IRQ\n");
  798. goto out3;
  799. }
  800. host->clk = clk_get(&pdev->dev, ALCHEMY_PERIPH_CLK);
  801. if (IS_ERR(host->clk)) {
  802. dev_err(&pdev->dev, "cannot find clock\n");
  803. ret = PTR_ERR(host->clk);
  804. goto out_irq;
  805. }
  806. ret = clk_prepare_enable(host->clk);
  807. if (ret) {
  808. dev_err(&pdev->dev, "cannot enable clock\n");
  809. goto out_clk;
  810. }
  811. host->status = HOST_S_IDLE;
  812. /* board-specific carddetect setup, if any */
  813. if (host->platdata && host->platdata->cd_setup) {
  814. ret = host->platdata->cd_setup(mmc, 1);
  815. if (ret) {
  816. dev_warn(&pdev->dev, "board CD setup failed\n");
  817. mmc->caps |= MMC_CAP_NEEDS_POLL;
  818. }
  819. } else
  820. mmc->caps |= MMC_CAP_NEEDS_POLL;
  821. /* platform may not be able to use all advertised caps */
  822. if (host->platdata)
  823. mmc->caps &= ~(host->platdata->mask_host_caps);
  824. tasklet_init(&host->data_task, au1xmmc_tasklet_data,
  825. (unsigned long)host);
  826. tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
  827. (unsigned long)host);
  828. if (has_dbdma()) {
  829. ret = au1xmmc_dbdma_init(host);
  830. if (ret)
  831. pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n");
  832. }
  833. #ifdef CONFIG_LEDS_CLASS
  834. if (host->platdata && host->platdata->led) {
  835. struct led_classdev *led = host->platdata->led;
  836. led->name = mmc_hostname(mmc);
  837. led->brightness = LED_OFF;
  838. led->default_trigger = mmc_hostname(mmc);
  839. ret = led_classdev_register(mmc_dev(mmc), led);
  840. if (ret)
  841. goto out5;
  842. }
  843. #endif
  844. au1xmmc_reset_controller(host);
  845. ret = mmc_add_host(mmc);
  846. if (ret) {
  847. dev_err(&pdev->dev, "cannot add mmc host\n");
  848. goto out6;
  849. }
  850. platform_set_drvdata(pdev, host);
  851. pr_info(DRIVER_NAME ": MMC Controller %d set up at %p"
  852. " (mode=%s)\n", pdev->id, host->iobase,
  853. host->flags & HOST_F_DMA ? "dma" : "pio");
  854. return 0; /* all ok */
  855. out6:
  856. #ifdef CONFIG_LEDS_CLASS
  857. if (host->platdata && host->platdata->led)
  858. led_classdev_unregister(host->platdata->led);
  859. out5:
  860. #endif
  861. __raw_writel(0, HOST_ENABLE(host));
  862. __raw_writel(0, HOST_CONFIG(host));
  863. __raw_writel(0, HOST_CONFIG2(host));
  864. wmb(); /* drain writebuffer */
  865. if (host->flags & HOST_F_DBDMA)
  866. au1xmmc_dbdma_shutdown(host);
  867. tasklet_kill(&host->data_task);
  868. tasklet_kill(&host->finish_task);
  869. if (host->platdata && host->platdata->cd_setup &&
  870. !(mmc->caps & MMC_CAP_NEEDS_POLL))
  871. host->platdata->cd_setup(mmc, 0);
  872. out_clk:
  873. clk_disable_unprepare(host->clk);
  874. clk_put(host->clk);
  875. out_irq:
  876. free_irq(host->irq, host);
  877. out3:
  878. iounmap((void *)host->iobase);
  879. out2:
  880. release_resource(host->ioarea);
  881. kfree(host->ioarea);
  882. out1:
  883. mmc_free_host(mmc);
  884. out0:
  885. return ret;
  886. }
  887. static int au1xmmc_remove(struct platform_device *pdev)
  888. {
  889. struct au1xmmc_host *host = platform_get_drvdata(pdev);
  890. if (host) {
  891. mmc_remove_host(host->mmc);
  892. #ifdef CONFIG_LEDS_CLASS
  893. if (host->platdata && host->platdata->led)
  894. led_classdev_unregister(host->platdata->led);
  895. #endif
  896. if (host->platdata && host->platdata->cd_setup &&
  897. !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
  898. host->platdata->cd_setup(host->mmc, 0);
  899. __raw_writel(0, HOST_ENABLE(host));
  900. __raw_writel(0, HOST_CONFIG(host));
  901. __raw_writel(0, HOST_CONFIG2(host));
  902. wmb(); /* drain writebuffer */
  903. tasklet_kill(&host->data_task);
  904. tasklet_kill(&host->finish_task);
  905. if (host->flags & HOST_F_DBDMA)
  906. au1xmmc_dbdma_shutdown(host);
  907. au1xmmc_set_power(host, 0);
  908. clk_disable_unprepare(host->clk);
  909. clk_put(host->clk);
  910. free_irq(host->irq, host);
  911. iounmap((void *)host->iobase);
  912. release_resource(host->ioarea);
  913. kfree(host->ioarea);
  914. mmc_free_host(host->mmc);
  915. }
  916. return 0;
  917. }
  918. #ifdef CONFIG_PM
  919. static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
  920. {
  921. struct au1xmmc_host *host = platform_get_drvdata(pdev);
  922. __raw_writel(0, HOST_CONFIG2(host));
  923. __raw_writel(0, HOST_CONFIG(host));
  924. __raw_writel(0xffffffff, HOST_STATUS(host));
  925. __raw_writel(0, HOST_ENABLE(host));
  926. wmb(); /* drain writebuffer */
  927. return 0;
  928. }
  929. static int au1xmmc_resume(struct platform_device *pdev)
  930. {
  931. struct au1xmmc_host *host = platform_get_drvdata(pdev);
  932. au1xmmc_reset_controller(host);
  933. return 0;
  934. }
  935. #else
  936. #define au1xmmc_suspend NULL
  937. #define au1xmmc_resume NULL
  938. #endif
  939. static struct platform_driver au1xmmc_driver = {
  940. .probe = au1xmmc_probe,
  941. .remove = au1xmmc_remove,
  942. .suspend = au1xmmc_suspend,
  943. .resume = au1xmmc_resume,
  944. .driver = {
  945. .name = DRIVER_NAME,
  946. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  947. },
  948. };
  949. static int __init au1xmmc_init(void)
  950. {
  951. if (has_dbdma()) {
  952. /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
  953. * of 8 bits. And since devices are shared, we need to create
  954. * our own to avoid freaking out other devices.
  955. */
  956. memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
  957. if (!memid)
  958. pr_err("au1xmmc: cannot add memory dbdma\n");
  959. }
  960. return platform_driver_register(&au1xmmc_driver);
  961. }
  962. static void __exit au1xmmc_exit(void)
  963. {
  964. if (has_dbdma() && memid)
  965. au1xxx_ddma_del_device(memid);
  966. platform_driver_unregister(&au1xmmc_driver);
  967. }
  968. module_init(au1xmmc_init);
  969. module_exit(au1xmmc_exit);
  970. MODULE_AUTHOR("Advanced Micro Devices, Inc");
  971. MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
  972. MODULE_LICENSE("GPL");
  973. MODULE_ALIAS("platform:au1xxx-mmc");