gruhandles.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * SN Platform GRU Driver
  4. *
  5. * GRU HANDLE DEFINITION
  6. *
  7. * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
  8. */
  9. #ifndef __GRUHANDLES_H__
  10. #define __GRUHANDLES_H__
  11. #include "gru_instructions.h"
  12. /*
  13. * Manifest constants for GRU Memory Map
  14. */
  15. #define GRU_GSEG0_BASE 0
  16. #define GRU_MCS_BASE (64 * 1024 * 1024)
  17. #define GRU_SIZE (128UL * 1024 * 1024)
  18. /* Handle & resource counts */
  19. #define GRU_NUM_CB 128
  20. #define GRU_NUM_DSR_BYTES (32 * 1024)
  21. #define GRU_NUM_TFM 16
  22. #define GRU_NUM_TGH 24
  23. #define GRU_NUM_CBE 128
  24. #define GRU_NUM_TFH 128
  25. #define GRU_NUM_CCH 16
  26. /* Maximum resource counts that can be reserved by user programs */
  27. #define GRU_NUM_USER_CBR GRU_NUM_CBE
  28. #define GRU_NUM_USER_DSR_BYTES GRU_NUM_DSR_BYTES
  29. /* Bytes per handle & handle stride. Code assumes all cb, tfh, cbe handles
  30. * are the same */
  31. #define GRU_HANDLE_BYTES 64
  32. #define GRU_HANDLE_STRIDE 256
  33. /* Base addresses of handles */
  34. #define GRU_TFM_BASE (GRU_MCS_BASE + 0x00000)
  35. #define GRU_TGH_BASE (GRU_MCS_BASE + 0x08000)
  36. #define GRU_CBE_BASE (GRU_MCS_BASE + 0x10000)
  37. #define GRU_TFH_BASE (GRU_MCS_BASE + 0x18000)
  38. #define GRU_CCH_BASE (GRU_MCS_BASE + 0x20000)
  39. /* User gseg constants */
  40. #define GRU_GSEG_STRIDE (4 * 1024 * 1024)
  41. #define GSEG_BASE(a) ((a) & ~(GRU_GSEG_PAGESIZE - 1))
  42. /* Data segment constants */
  43. #define GRU_DSR_AU_BYTES 1024
  44. #define GRU_DSR_CL (GRU_NUM_DSR_BYTES / GRU_CACHE_LINE_BYTES)
  45. #define GRU_DSR_AU_CL (GRU_DSR_AU_BYTES / GRU_CACHE_LINE_BYTES)
  46. #define GRU_DSR_AU (GRU_NUM_DSR_BYTES / GRU_DSR_AU_BYTES)
  47. /* Control block constants */
  48. #define GRU_CBR_AU_SIZE 2
  49. #define GRU_CBR_AU (GRU_NUM_CBE / GRU_CBR_AU_SIZE)
  50. /* Convert resource counts to the number of AU */
  51. #define GRU_DS_BYTES_TO_AU(n) DIV_ROUND_UP(n, GRU_DSR_AU_BYTES)
  52. #define GRU_CB_COUNT_TO_AU(n) DIV_ROUND_UP(n, GRU_CBR_AU_SIZE)
  53. /* UV limits */
  54. #define GRU_CHIPLETS_PER_HUB 2
  55. #define GRU_HUBS_PER_BLADE 1
  56. #define GRU_CHIPLETS_PER_BLADE (GRU_HUBS_PER_BLADE * GRU_CHIPLETS_PER_HUB)
  57. /* User GRU Gseg offsets */
  58. #define GRU_CB_BASE 0
  59. #define GRU_CB_LIMIT (GRU_CB_BASE + GRU_HANDLE_STRIDE * GRU_NUM_CBE)
  60. #define GRU_DS_BASE 0x20000
  61. #define GRU_DS_LIMIT (GRU_DS_BASE + GRU_NUM_DSR_BYTES)
  62. /* Convert a GRU physical address to the chiplet offset */
  63. #define GSEGPOFF(h) ((h) & (GRU_SIZE - 1))
  64. /* Convert an arbitrary handle address to the beginning of the GRU segment */
  65. #define GRUBASE(h) ((void *)((unsigned long)(h) & ~(GRU_SIZE - 1)))
  66. /* Test a valid handle address to determine the type */
  67. #define TYPE_IS(hn, h) ((h) >= GRU_##hn##_BASE && (h) < \
  68. GRU_##hn##_BASE + GRU_NUM_##hn * GRU_HANDLE_STRIDE && \
  69. (((h) & (GRU_HANDLE_STRIDE - 1)) == 0))
  70. /* General addressing macros. */
  71. static inline void *get_gseg_base_address(void *base, int ctxnum)
  72. {
  73. return (void *)(base + GRU_GSEG0_BASE + GRU_GSEG_STRIDE * ctxnum);
  74. }
  75. static inline void *get_gseg_base_address_cb(void *base, int ctxnum, int line)
  76. {
  77. return (void *)(get_gseg_base_address(base, ctxnum) +
  78. GRU_CB_BASE + GRU_HANDLE_STRIDE * line);
  79. }
  80. static inline void *get_gseg_base_address_ds(void *base, int ctxnum, int line)
  81. {
  82. return (void *)(get_gseg_base_address(base, ctxnum) + GRU_DS_BASE +
  83. GRU_CACHE_LINE_BYTES * line);
  84. }
  85. static inline struct gru_tlb_fault_map *get_tfm(void *base, int ctxnum)
  86. {
  87. return (struct gru_tlb_fault_map *)(base + GRU_TFM_BASE +
  88. ctxnum * GRU_HANDLE_STRIDE);
  89. }
  90. static inline struct gru_tlb_global_handle *get_tgh(void *base, int ctxnum)
  91. {
  92. return (struct gru_tlb_global_handle *)(base + GRU_TGH_BASE +
  93. ctxnum * GRU_HANDLE_STRIDE);
  94. }
  95. static inline struct gru_control_block_extended *get_cbe(void *base, int ctxnum)
  96. {
  97. return (struct gru_control_block_extended *)(base + GRU_CBE_BASE +
  98. ctxnum * GRU_HANDLE_STRIDE);
  99. }
  100. static inline struct gru_tlb_fault_handle *get_tfh(void *base, int ctxnum)
  101. {
  102. return (struct gru_tlb_fault_handle *)(base + GRU_TFH_BASE +
  103. ctxnum * GRU_HANDLE_STRIDE);
  104. }
  105. static inline struct gru_context_configuration_handle *get_cch(void *base,
  106. int ctxnum)
  107. {
  108. return (struct gru_context_configuration_handle *)(base +
  109. GRU_CCH_BASE + ctxnum * GRU_HANDLE_STRIDE);
  110. }
  111. static inline unsigned long get_cb_number(void *cb)
  112. {
  113. return (((unsigned long)cb - GRU_CB_BASE) % GRU_GSEG_PAGESIZE) /
  114. GRU_HANDLE_STRIDE;
  115. }
  116. /* byte offset to a specific GRU chiplet. (p=pnode, c=chiplet (0 or 1)*/
  117. static inline unsigned long gru_chiplet_paddr(unsigned long paddr, int pnode,
  118. int chiplet)
  119. {
  120. return paddr + GRU_SIZE * (2 * pnode + chiplet);
  121. }
  122. static inline void *gru_chiplet_vaddr(void *vaddr, int pnode, int chiplet)
  123. {
  124. return vaddr + GRU_SIZE * (2 * pnode + chiplet);
  125. }
  126. static inline struct gru_control_block_extended *gru_tfh_to_cbe(
  127. struct gru_tlb_fault_handle *tfh)
  128. {
  129. unsigned long cbe;
  130. cbe = (unsigned long)tfh - GRU_TFH_BASE + GRU_CBE_BASE;
  131. return (struct gru_control_block_extended*)cbe;
  132. }
  133. /*
  134. * Global TLB Fault Map
  135. * Bitmap of outstanding TLB misses needing interrupt/polling service.
  136. *
  137. */
  138. struct gru_tlb_fault_map {
  139. unsigned long fault_bits[BITS_TO_LONGS(GRU_NUM_CBE)];
  140. unsigned long fill0[2];
  141. unsigned long done_bits[BITS_TO_LONGS(GRU_NUM_CBE)];
  142. unsigned long fill1[2];
  143. };
  144. /*
  145. * TGH - TLB Global Handle
  146. * Used for TLB flushing.
  147. *
  148. */
  149. struct gru_tlb_global_handle {
  150. unsigned int cmd:1; /* DW 0 */
  151. unsigned int delresp:1;
  152. unsigned int opc:1;
  153. unsigned int fill1:5;
  154. unsigned int fill2:8;
  155. unsigned int status:2;
  156. unsigned long fill3:2;
  157. unsigned int state:3;
  158. unsigned long fill4:1;
  159. unsigned int cause:3;
  160. unsigned long fill5:37;
  161. unsigned long vaddr:64; /* DW 1 */
  162. unsigned int asid:24; /* DW 2 */
  163. unsigned int fill6:8;
  164. unsigned int pagesize:5;
  165. unsigned int fill7:11;
  166. unsigned int global:1;
  167. unsigned int fill8:15;
  168. unsigned long vaddrmask:39; /* DW 3 */
  169. unsigned int fill9:9;
  170. unsigned int n:10;
  171. unsigned int fill10:6;
  172. unsigned int ctxbitmap:16; /* DW4 */
  173. unsigned long fill11[3];
  174. };
  175. enum gru_tgh_cmd {
  176. TGHCMD_START
  177. };
  178. enum gru_tgh_opc {
  179. TGHOP_TLBNOP,
  180. TGHOP_TLBINV
  181. };
  182. enum gru_tgh_status {
  183. TGHSTATUS_IDLE,
  184. TGHSTATUS_EXCEPTION,
  185. TGHSTATUS_ACTIVE
  186. };
  187. enum gru_tgh_state {
  188. TGHSTATE_IDLE,
  189. TGHSTATE_PE_INVAL,
  190. TGHSTATE_INTERRUPT_INVAL,
  191. TGHSTATE_WAITDONE,
  192. TGHSTATE_RESTART_CTX,
  193. };
  194. enum gru_tgh_cause {
  195. TGHCAUSE_RR_ECC,
  196. TGHCAUSE_TLB_ECC,
  197. TGHCAUSE_LRU_ECC,
  198. TGHCAUSE_PS_ECC,
  199. TGHCAUSE_MUL_ERR,
  200. TGHCAUSE_DATA_ERR,
  201. TGHCAUSE_SW_FORCE
  202. };
  203. /*
  204. * TFH - TLB Global Handle
  205. * Used for TLB dropins into the GRU TLB.
  206. *
  207. */
  208. struct gru_tlb_fault_handle {
  209. unsigned int cmd:1; /* DW 0 - low 32*/
  210. unsigned int delresp:1;
  211. unsigned int fill0:2;
  212. unsigned int opc:3;
  213. unsigned int fill1:9;
  214. unsigned int status:2;
  215. unsigned int fill2:2;
  216. unsigned int state:3;
  217. unsigned int fill3:1;
  218. unsigned int cause:6;
  219. unsigned int cb_int:1;
  220. unsigned int fill4:1;
  221. unsigned int indexway:12; /* DW 0 - high 32 */
  222. unsigned int fill5:4;
  223. unsigned int ctxnum:4;
  224. unsigned int fill6:12;
  225. unsigned long missvaddr:64; /* DW 1 */
  226. unsigned int missasid:24; /* DW 2 */
  227. unsigned int fill7:8;
  228. unsigned int fillasid:24;
  229. unsigned int dirty:1;
  230. unsigned int gaa:2;
  231. unsigned long fill8:5;
  232. unsigned long pfn:41; /* DW 3 */
  233. unsigned int fill9:7;
  234. unsigned int pagesize:5;
  235. unsigned int fill10:11;
  236. unsigned long fillvaddr:64; /* DW 4 */
  237. unsigned long fill11[3];
  238. };
  239. enum gru_tfh_opc {
  240. TFHOP_NOOP,
  241. TFHOP_RESTART,
  242. TFHOP_WRITE_ONLY,
  243. TFHOP_WRITE_RESTART,
  244. TFHOP_EXCEPTION,
  245. TFHOP_USER_POLLING_MODE = 7,
  246. };
  247. enum tfh_status {
  248. TFHSTATUS_IDLE,
  249. TFHSTATUS_EXCEPTION,
  250. TFHSTATUS_ACTIVE,
  251. };
  252. enum tfh_state {
  253. TFHSTATE_INACTIVE,
  254. TFHSTATE_IDLE,
  255. TFHSTATE_MISS_UPM,
  256. TFHSTATE_MISS_FMM,
  257. TFHSTATE_HW_ERR,
  258. TFHSTATE_WRITE_TLB,
  259. TFHSTATE_RESTART_CBR,
  260. };
  261. /* TFH cause bits */
  262. enum tfh_cause {
  263. TFHCAUSE_NONE,
  264. TFHCAUSE_TLB_MISS,
  265. TFHCAUSE_TLB_MOD,
  266. TFHCAUSE_HW_ERROR_RR,
  267. TFHCAUSE_HW_ERROR_MAIN_ARRAY,
  268. TFHCAUSE_HW_ERROR_VALID,
  269. TFHCAUSE_HW_ERROR_PAGESIZE,
  270. TFHCAUSE_INSTRUCTION_EXCEPTION,
  271. TFHCAUSE_UNCORRECTIBLE_ERROR,
  272. };
  273. /* GAA values */
  274. #define GAA_RAM 0x0
  275. #define GAA_NCRAM 0x2
  276. #define GAA_MMIO 0x1
  277. #define GAA_REGISTER 0x3
  278. /* GRU paddr shift for pfn. (NOTE: shift is NOT by actual pagesize) */
  279. #define GRU_PADDR_SHIFT 12
  280. /*
  281. * Context Configuration handle
  282. * Used to allocate resources to a GSEG context.
  283. *
  284. */
  285. struct gru_context_configuration_handle {
  286. unsigned int cmd:1; /* DW0 */
  287. unsigned int delresp:1;
  288. unsigned int opc:3;
  289. unsigned int unmap_enable:1;
  290. unsigned int req_slice_set_enable:1;
  291. unsigned int req_slice:2;
  292. unsigned int cb_int_enable:1;
  293. unsigned int tlb_int_enable:1;
  294. unsigned int tfm_fault_bit_enable:1;
  295. unsigned int tlb_int_select:4;
  296. unsigned int status:2;
  297. unsigned int state:2;
  298. unsigned int reserved2:4;
  299. unsigned int cause:4;
  300. unsigned int tfm_done_bit_enable:1;
  301. unsigned int unused:3;
  302. unsigned int dsr_allocation_map;
  303. unsigned long cbr_allocation_map; /* DW1 */
  304. unsigned int asid[8]; /* DW 2 - 5 */
  305. unsigned short sizeavail[8]; /* DW 6 - 7 */
  306. } __attribute__ ((packed));
  307. enum gru_cch_opc {
  308. CCHOP_START = 1,
  309. CCHOP_ALLOCATE,
  310. CCHOP_INTERRUPT,
  311. CCHOP_DEALLOCATE,
  312. CCHOP_INTERRUPT_SYNC,
  313. };
  314. enum gru_cch_status {
  315. CCHSTATUS_IDLE,
  316. CCHSTATUS_EXCEPTION,
  317. CCHSTATUS_ACTIVE,
  318. };
  319. enum gru_cch_state {
  320. CCHSTATE_INACTIVE,
  321. CCHSTATE_MAPPED,
  322. CCHSTATE_ACTIVE,
  323. CCHSTATE_INTERRUPTED,
  324. };
  325. /* CCH Exception cause */
  326. enum gru_cch_cause {
  327. CCHCAUSE_REGION_REGISTER_WRITE_ERROR = 1,
  328. CCHCAUSE_ILLEGAL_OPCODE = 2,
  329. CCHCAUSE_INVALID_START_REQUEST = 3,
  330. CCHCAUSE_INVALID_ALLOCATION_REQUEST = 4,
  331. CCHCAUSE_INVALID_DEALLOCATION_REQUEST = 5,
  332. CCHCAUSE_INVALID_INTERRUPT_REQUEST = 6,
  333. CCHCAUSE_CCH_BUSY = 7,
  334. CCHCAUSE_NO_CBRS_TO_ALLOCATE = 8,
  335. CCHCAUSE_BAD_TFM_CONFIG = 9,
  336. CCHCAUSE_CBR_RESOURCES_OVERSUBSCRIPED = 10,
  337. CCHCAUSE_DSR_RESOURCES_OVERSUBSCRIPED = 11,
  338. CCHCAUSE_CBR_DEALLOCATION_ERROR = 12,
  339. };
  340. /*
  341. * CBE - Control Block Extended
  342. * Maintains internal GRU state for active CBs.
  343. *
  344. */
  345. struct gru_control_block_extended {
  346. unsigned int reserved0:1; /* DW 0 - low */
  347. unsigned int imacpy:3;
  348. unsigned int reserved1:4;
  349. unsigned int xtypecpy:3;
  350. unsigned int iaa0cpy:2;
  351. unsigned int iaa1cpy:2;
  352. unsigned int reserved2:1;
  353. unsigned int opccpy:8;
  354. unsigned int exopccpy:8;
  355. unsigned int idef2cpy:22; /* DW 0 - high */
  356. unsigned int reserved3:10;
  357. unsigned int idef4cpy:22; /* DW 1 */
  358. unsigned int reserved4:10;
  359. unsigned int idef4upd:22;
  360. unsigned int reserved5:10;
  361. unsigned long idef1upd:64; /* DW 2 */
  362. unsigned long idef5cpy:64; /* DW 3 */
  363. unsigned long idef6cpy:64; /* DW 4 */
  364. unsigned long idef3upd:64; /* DW 5 */
  365. unsigned long idef5upd:64; /* DW 6 */
  366. unsigned int idef2upd:22; /* DW 7 */
  367. unsigned int reserved6:10;
  368. unsigned int ecause:20;
  369. unsigned int cbrstate:4;
  370. unsigned int cbrexecstatus:8;
  371. };
  372. /* CBE fields for active BCOPY instructions */
  373. #define cbe_baddr0 idef1upd
  374. #define cbe_baddr1 idef3upd
  375. #define cbe_src_cl idef6cpy
  376. #define cbe_nelemcur idef5upd
  377. enum gru_cbr_state {
  378. CBRSTATE_INACTIVE,
  379. CBRSTATE_IDLE,
  380. CBRSTATE_PE_CHECK,
  381. CBRSTATE_QUEUED,
  382. CBRSTATE_WAIT_RESPONSE,
  383. CBRSTATE_INTERRUPTED,
  384. CBRSTATE_INTERRUPTED_MISS_FMM,
  385. CBRSTATE_BUSY_INTERRUPT_MISS_FMM,
  386. CBRSTATE_INTERRUPTED_MISS_UPM,
  387. CBRSTATE_BUSY_INTERRUPTED_MISS_UPM,
  388. CBRSTATE_REQUEST_ISSUE,
  389. CBRSTATE_BUSY_INTERRUPT,
  390. };
  391. /* CBE cbrexecstatus bits - defined in gru_instructions.h*/
  392. /* CBE ecause bits - defined in gru_instructions.h */
  393. /*
  394. * Convert a processor pagesize into the strange encoded pagesize used by the
  395. * GRU. Processor pagesize is encoded as log of bytes per page. (or PAGE_SHIFT)
  396. * pagesize log pagesize grupagesize
  397. * 4k 12 0
  398. * 16k 14 1
  399. * 64k 16 2
  400. * 256k 18 3
  401. * 1m 20 4
  402. * 2m 21 5
  403. * 4m 22 6
  404. * 16m 24 7
  405. * 64m 26 8
  406. * ...
  407. */
  408. #define GRU_PAGESIZE(sh) ((((sh) > 20 ? (sh) + 2 : (sh)) >> 1) - 6)
  409. #define GRU_SIZEAVAIL(sh) (1UL << GRU_PAGESIZE(sh))
  410. /* minimum TLB purge count to ensure a full purge */
  411. #define GRUMAXINVAL 1024UL
  412. int cch_allocate(struct gru_context_configuration_handle *cch);
  413. int cch_start(struct gru_context_configuration_handle *cch);
  414. int cch_interrupt(struct gru_context_configuration_handle *cch);
  415. int cch_deallocate(struct gru_context_configuration_handle *cch);
  416. int cch_interrupt_sync(struct gru_context_configuration_handle *cch);
  417. int tgh_invalidate(struct gru_tlb_global_handle *tgh, unsigned long vaddr,
  418. unsigned long vaddrmask, int asid, int pagesize, int global, int n,
  419. unsigned short ctxbitmap);
  420. int tfh_write_only(struct gru_tlb_fault_handle *tfh, unsigned long paddr,
  421. int gaa, unsigned long vaddr, int asid, int dirty, int pagesize);
  422. void tfh_write_restart(struct gru_tlb_fault_handle *tfh, unsigned long paddr,
  423. int gaa, unsigned long vaddr, int asid, int dirty, int pagesize);
  424. void tfh_user_polling_mode(struct gru_tlb_fault_handle *tfh);
  425. void tfh_exception(struct gru_tlb_fault_handle *tfh);
  426. #endif /* __GRUHANDLES_H__ */