grufile.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * SN Platform GRU Driver
  4. *
  5. * FILE OPERATIONS & DRIVER INITIALIZATION
  6. *
  7. * This file supports the user system call for file open, close, mmap, etc.
  8. * This also incudes the driver initialization code.
  9. *
  10. * (C) Copyright 2020 Hewlett Packard Enterprise Development LP
  11. * Copyright (c) 2008-2014 Silicon Graphics, Inc. All Rights Reserved.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/slab.h>
  17. #include <linux/mm.h>
  18. #include <linux/io.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/device.h>
  21. #include <linux/miscdevice.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/proc_fs.h>
  24. #include <linux/uaccess.h>
  25. #ifdef CONFIG_X86_64
  26. #include <asm/uv/uv_irq.h>
  27. #endif
  28. #include <asm/uv/uv.h>
  29. #include "gru.h"
  30. #include "grulib.h"
  31. #include "grutables.h"
  32. #include <asm/uv/uv_hub.h>
  33. #include <asm/uv/uv_mmrs.h>
  34. struct gru_blade_state *gru_base[GRU_MAX_BLADES] __read_mostly;
  35. unsigned long gru_start_paddr __read_mostly;
  36. void *gru_start_vaddr __read_mostly;
  37. unsigned long gru_end_paddr __read_mostly;
  38. unsigned int gru_max_gids __read_mostly;
  39. struct gru_stats_s gru_stats;
  40. /* Guaranteed user available resources on each node */
  41. static int max_user_cbrs, max_user_dsr_bytes;
  42. static struct miscdevice gru_miscdev;
  43. static int gru_supported(void)
  44. {
  45. return is_uv_system() &&
  46. (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE);
  47. }
  48. /*
  49. * gru_vma_close
  50. *
  51. * Called when unmapping a device mapping. Frees all gru resources
  52. * and tables belonging to the vma.
  53. */
  54. static void gru_vma_close(struct vm_area_struct *vma)
  55. {
  56. struct gru_vma_data *vdata;
  57. struct gru_thread_state *gts;
  58. struct list_head *entry, *next;
  59. if (!vma->vm_private_data)
  60. return;
  61. vdata = vma->vm_private_data;
  62. vma->vm_private_data = NULL;
  63. gru_dbg(grudev, "vma %p, file %p, vdata %p\n", vma, vma->vm_file,
  64. vdata);
  65. list_for_each_safe(entry, next, &vdata->vd_head) {
  66. gts =
  67. list_entry(entry, struct gru_thread_state, ts_next);
  68. list_del(&gts->ts_next);
  69. mutex_lock(&gts->ts_ctxlock);
  70. if (gts->ts_gru)
  71. gru_unload_context(gts, 0);
  72. mutex_unlock(&gts->ts_ctxlock);
  73. gts_drop(gts);
  74. }
  75. kfree(vdata);
  76. STAT(vdata_free);
  77. }
  78. /*
  79. * gru_file_mmap
  80. *
  81. * Called when mmapping the device. Initializes the vma with a fault handler
  82. * and private data structure necessary to allocate, track, and free the
  83. * underlying pages.
  84. */
  85. static int gru_file_mmap(struct file *file, struct vm_area_struct *vma)
  86. {
  87. if ((vma->vm_flags & (VM_SHARED | VM_WRITE)) != (VM_SHARED | VM_WRITE))
  88. return -EPERM;
  89. if (vma->vm_start & (GRU_GSEG_PAGESIZE - 1) ||
  90. vma->vm_end & (GRU_GSEG_PAGESIZE - 1))
  91. return -EINVAL;
  92. vma->vm_flags |= VM_IO | VM_PFNMAP | VM_LOCKED |
  93. VM_DONTCOPY | VM_DONTEXPAND | VM_DONTDUMP;
  94. vma->vm_page_prot = PAGE_SHARED;
  95. vma->vm_ops = &gru_vm_ops;
  96. vma->vm_private_data = gru_alloc_vma_data(vma, 0);
  97. if (!vma->vm_private_data)
  98. return -ENOMEM;
  99. gru_dbg(grudev, "file %p, vaddr 0x%lx, vma %p, vdata %p\n",
  100. file, vma->vm_start, vma, vma->vm_private_data);
  101. return 0;
  102. }
  103. /*
  104. * Create a new GRU context
  105. */
  106. static int gru_create_new_context(unsigned long arg)
  107. {
  108. struct gru_create_context_req req;
  109. struct vm_area_struct *vma;
  110. struct gru_vma_data *vdata;
  111. int ret = -EINVAL;
  112. if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
  113. return -EFAULT;
  114. if (req.data_segment_bytes > max_user_dsr_bytes)
  115. return -EINVAL;
  116. if (req.control_blocks > max_user_cbrs || !req.maximum_thread_count)
  117. return -EINVAL;
  118. if (!(req.options & GRU_OPT_MISS_MASK))
  119. req.options |= GRU_OPT_MISS_FMM_INTR;
  120. mmap_write_lock(current->mm);
  121. vma = gru_find_vma(req.gseg);
  122. if (vma) {
  123. vdata = vma->vm_private_data;
  124. vdata->vd_user_options = req.options;
  125. vdata->vd_dsr_au_count =
  126. GRU_DS_BYTES_TO_AU(req.data_segment_bytes);
  127. vdata->vd_cbr_au_count = GRU_CB_COUNT_TO_AU(req.control_blocks);
  128. vdata->vd_tlb_preload_count = req.tlb_preload_count;
  129. ret = 0;
  130. }
  131. mmap_write_unlock(current->mm);
  132. return ret;
  133. }
  134. /*
  135. * Get GRU configuration info (temp - for emulator testing)
  136. */
  137. static long gru_get_config_info(unsigned long arg)
  138. {
  139. struct gru_config_info info;
  140. int nodesperblade;
  141. if (num_online_nodes() > 1 &&
  142. (uv_node_to_blade_id(1) == uv_node_to_blade_id(0)))
  143. nodesperblade = 2;
  144. else
  145. nodesperblade = 1;
  146. memset(&info, 0, sizeof(info));
  147. info.cpus = num_online_cpus();
  148. info.nodes = num_online_nodes();
  149. info.blades = info.nodes / nodesperblade;
  150. info.chiplets = GRU_CHIPLETS_PER_BLADE * info.blades;
  151. if (copy_to_user((void __user *)arg, &info, sizeof(info)))
  152. return -EFAULT;
  153. return 0;
  154. }
  155. /*
  156. * gru_file_unlocked_ioctl
  157. *
  158. * Called to update file attributes via IOCTL calls.
  159. */
  160. static long gru_file_unlocked_ioctl(struct file *file, unsigned int req,
  161. unsigned long arg)
  162. {
  163. int err = -EBADRQC;
  164. gru_dbg(grudev, "file %p, req 0x%x, 0x%lx\n", file, req, arg);
  165. switch (req) {
  166. case GRU_CREATE_CONTEXT:
  167. err = gru_create_new_context(arg);
  168. break;
  169. case GRU_SET_CONTEXT_OPTION:
  170. err = gru_set_context_option(arg);
  171. break;
  172. case GRU_USER_GET_EXCEPTION_DETAIL:
  173. err = gru_get_exception_detail(arg);
  174. break;
  175. case GRU_USER_UNLOAD_CONTEXT:
  176. err = gru_user_unload_context(arg);
  177. break;
  178. case GRU_USER_FLUSH_TLB:
  179. err = gru_user_flush_tlb(arg);
  180. break;
  181. case GRU_USER_CALL_OS:
  182. err = gru_handle_user_call_os(arg);
  183. break;
  184. case GRU_GET_GSEG_STATISTICS:
  185. err = gru_get_gseg_statistics(arg);
  186. break;
  187. case GRU_KTEST:
  188. err = gru_ktest(arg);
  189. break;
  190. case GRU_GET_CONFIG_INFO:
  191. err = gru_get_config_info(arg);
  192. break;
  193. case GRU_DUMP_CHIPLET_STATE:
  194. err = gru_dump_chiplet_request(arg);
  195. break;
  196. }
  197. return err;
  198. }
  199. /*
  200. * Called at init time to build tables for all GRUs that are present in the
  201. * system.
  202. */
  203. static void gru_init_chiplet(struct gru_state *gru, unsigned long paddr,
  204. void *vaddr, int blade_id, int chiplet_id)
  205. {
  206. spin_lock_init(&gru->gs_lock);
  207. spin_lock_init(&gru->gs_asid_lock);
  208. gru->gs_gru_base_paddr = paddr;
  209. gru->gs_gru_base_vaddr = vaddr;
  210. gru->gs_gid = blade_id * GRU_CHIPLETS_PER_BLADE + chiplet_id;
  211. gru->gs_blade = gru_base[blade_id];
  212. gru->gs_blade_id = blade_id;
  213. gru->gs_chiplet_id = chiplet_id;
  214. gru->gs_cbr_map = (GRU_CBR_AU == 64) ? ~0 : (1UL << GRU_CBR_AU) - 1;
  215. gru->gs_dsr_map = (1UL << GRU_DSR_AU) - 1;
  216. gru->gs_asid_limit = MAX_ASID;
  217. gru_tgh_flush_init(gru);
  218. if (gru->gs_gid >= gru_max_gids)
  219. gru_max_gids = gru->gs_gid + 1;
  220. gru_dbg(grudev, "bid %d, gid %d, vaddr %p (0x%lx)\n",
  221. blade_id, gru->gs_gid, gru->gs_gru_base_vaddr,
  222. gru->gs_gru_base_paddr);
  223. }
  224. static int gru_init_tables(unsigned long gru_base_paddr, void *gru_base_vaddr)
  225. {
  226. int pnode, nid, bid, chip;
  227. int cbrs, dsrbytes, n;
  228. int order = get_order(sizeof(struct gru_blade_state));
  229. struct page *page;
  230. struct gru_state *gru;
  231. unsigned long paddr;
  232. void *vaddr;
  233. max_user_cbrs = GRU_NUM_CB;
  234. max_user_dsr_bytes = GRU_NUM_DSR_BYTES;
  235. for_each_possible_blade(bid) {
  236. pnode = uv_blade_to_pnode(bid);
  237. nid = uv_blade_to_memory_nid(bid);/* -1 if no memory on blade */
  238. page = alloc_pages_node(nid, GFP_KERNEL, order);
  239. if (!page)
  240. goto fail;
  241. gru_base[bid] = page_address(page);
  242. memset(gru_base[bid], 0, sizeof(struct gru_blade_state));
  243. gru_base[bid]->bs_lru_gru = &gru_base[bid]->bs_grus[0];
  244. spin_lock_init(&gru_base[bid]->bs_lock);
  245. init_rwsem(&gru_base[bid]->bs_kgts_sema);
  246. dsrbytes = 0;
  247. cbrs = 0;
  248. for (gru = gru_base[bid]->bs_grus, chip = 0;
  249. chip < GRU_CHIPLETS_PER_BLADE;
  250. chip++, gru++) {
  251. paddr = gru_chiplet_paddr(gru_base_paddr, pnode, chip);
  252. vaddr = gru_chiplet_vaddr(gru_base_vaddr, pnode, chip);
  253. gru_init_chiplet(gru, paddr, vaddr, bid, chip);
  254. n = hweight64(gru->gs_cbr_map) * GRU_CBR_AU_SIZE;
  255. cbrs = max(cbrs, n);
  256. n = hweight64(gru->gs_dsr_map) * GRU_DSR_AU_BYTES;
  257. dsrbytes = max(dsrbytes, n);
  258. }
  259. max_user_cbrs = min(max_user_cbrs, cbrs);
  260. max_user_dsr_bytes = min(max_user_dsr_bytes, dsrbytes);
  261. }
  262. return 0;
  263. fail:
  264. for (bid--; bid >= 0; bid--)
  265. free_pages((unsigned long)gru_base[bid], order);
  266. return -ENOMEM;
  267. }
  268. static void gru_free_tables(void)
  269. {
  270. int bid;
  271. int order = get_order(sizeof(struct gru_state) *
  272. GRU_CHIPLETS_PER_BLADE);
  273. for (bid = 0; bid < GRU_MAX_BLADES; bid++)
  274. free_pages((unsigned long)gru_base[bid], order);
  275. }
  276. static unsigned long gru_chiplet_cpu_to_mmr(int chiplet, int cpu, int *corep)
  277. {
  278. unsigned long mmr = 0;
  279. int core;
  280. /*
  281. * We target the cores of a blade and not the hyperthreads themselves.
  282. * There is a max of 8 cores per socket and 2 sockets per blade,
  283. * making for a max total of 16 cores (i.e., 16 CPUs without
  284. * hyperthreading and 32 CPUs with hyperthreading).
  285. */
  286. core = uv_cpu_core_number(cpu) + UV_MAX_INT_CORES * uv_cpu_socket_number(cpu);
  287. if (core >= GRU_NUM_TFM || uv_cpu_ht_number(cpu))
  288. return 0;
  289. if (chiplet == 0) {
  290. mmr = UVH_GR0_TLB_INT0_CONFIG +
  291. core * (UVH_GR0_TLB_INT1_CONFIG - UVH_GR0_TLB_INT0_CONFIG);
  292. } else if (chiplet == 1) {
  293. mmr = UVH_GR1_TLB_INT0_CONFIG +
  294. core * (UVH_GR1_TLB_INT1_CONFIG - UVH_GR1_TLB_INT0_CONFIG);
  295. } else {
  296. BUG();
  297. }
  298. *corep = core;
  299. return mmr;
  300. }
  301. #ifdef CONFIG_IA64
  302. static int gru_irq_count[GRU_CHIPLETS_PER_BLADE];
  303. static void gru_noop(struct irq_data *d)
  304. {
  305. }
  306. static struct irq_chip gru_chip[GRU_CHIPLETS_PER_BLADE] = {
  307. [0 ... GRU_CHIPLETS_PER_BLADE - 1] {
  308. .irq_mask = gru_noop,
  309. .irq_unmask = gru_noop,
  310. .irq_ack = gru_noop
  311. }
  312. };
  313. static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
  314. irq_handler_t irq_handler, int cpu, int blade)
  315. {
  316. unsigned long mmr;
  317. int irq = IRQ_GRU + chiplet;
  318. int ret, core;
  319. mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
  320. if (mmr == 0)
  321. return 0;
  322. if (gru_irq_count[chiplet] == 0) {
  323. gru_chip[chiplet].name = irq_name;
  324. ret = irq_set_chip(irq, &gru_chip[chiplet]);
  325. if (ret) {
  326. printk(KERN_ERR "%s: set_irq_chip failed, errno=%d\n",
  327. GRU_DRIVER_ID_STR, -ret);
  328. return ret;
  329. }
  330. ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
  331. if (ret) {
  332. printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
  333. GRU_DRIVER_ID_STR, -ret);
  334. return ret;
  335. }
  336. }
  337. gru_irq_count[chiplet]++;
  338. return 0;
  339. }
  340. static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
  341. {
  342. unsigned long mmr;
  343. int core, irq = IRQ_GRU + chiplet;
  344. if (gru_irq_count[chiplet] == 0)
  345. return;
  346. mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
  347. if (mmr == 0)
  348. return;
  349. if (--gru_irq_count[chiplet] == 0)
  350. free_irq(irq, NULL);
  351. }
  352. #elif defined CONFIG_X86_64
  353. static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
  354. irq_handler_t irq_handler, int cpu, int blade)
  355. {
  356. unsigned long mmr;
  357. int irq, core;
  358. int ret;
  359. mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
  360. if (mmr == 0)
  361. return 0;
  362. irq = uv_setup_irq(irq_name, cpu, blade, mmr, UV_AFFINITY_CPU);
  363. if (irq < 0) {
  364. printk(KERN_ERR "%s: uv_setup_irq failed, errno=%d\n",
  365. GRU_DRIVER_ID_STR, -irq);
  366. return irq;
  367. }
  368. ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
  369. if (ret) {
  370. uv_teardown_irq(irq);
  371. printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
  372. GRU_DRIVER_ID_STR, -ret);
  373. return ret;
  374. }
  375. gru_base[blade]->bs_grus[chiplet].gs_irq[core] = irq;
  376. return 0;
  377. }
  378. static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
  379. {
  380. int irq, core;
  381. unsigned long mmr;
  382. mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
  383. if (mmr) {
  384. irq = gru_base[blade]->bs_grus[chiplet].gs_irq[core];
  385. if (irq) {
  386. free_irq(irq, NULL);
  387. uv_teardown_irq(irq);
  388. }
  389. }
  390. }
  391. #endif
  392. static void gru_teardown_tlb_irqs(void)
  393. {
  394. int blade;
  395. int cpu;
  396. for_each_online_cpu(cpu) {
  397. blade = uv_cpu_to_blade_id(cpu);
  398. gru_chiplet_teardown_tlb_irq(0, cpu, blade);
  399. gru_chiplet_teardown_tlb_irq(1, cpu, blade);
  400. }
  401. for_each_possible_blade(blade) {
  402. if (uv_blade_nr_possible_cpus(blade))
  403. continue;
  404. gru_chiplet_teardown_tlb_irq(0, 0, blade);
  405. gru_chiplet_teardown_tlb_irq(1, 0, blade);
  406. }
  407. }
  408. static int gru_setup_tlb_irqs(void)
  409. {
  410. int blade;
  411. int cpu;
  412. int ret;
  413. for_each_online_cpu(cpu) {
  414. blade = uv_cpu_to_blade_id(cpu);
  415. ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru0_intr, cpu, blade);
  416. if (ret != 0)
  417. goto exit1;
  418. ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru1_intr, cpu, blade);
  419. if (ret != 0)
  420. goto exit1;
  421. }
  422. for_each_possible_blade(blade) {
  423. if (uv_blade_nr_possible_cpus(blade))
  424. continue;
  425. ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru_intr_mblade, 0, blade);
  426. if (ret != 0)
  427. goto exit1;
  428. ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru_intr_mblade, 0, blade);
  429. if (ret != 0)
  430. goto exit1;
  431. }
  432. return 0;
  433. exit1:
  434. gru_teardown_tlb_irqs();
  435. return ret;
  436. }
  437. /*
  438. * gru_init
  439. *
  440. * Called at boot or module load time to initialize the GRUs.
  441. */
  442. static int __init gru_init(void)
  443. {
  444. int ret;
  445. if (!gru_supported())
  446. return 0;
  447. #if defined CONFIG_IA64
  448. gru_start_paddr = 0xd000000000UL; /* ZZZZZZZZZZZZZZZZZZZ fixme */
  449. #else
  450. gru_start_paddr = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG) &
  451. 0x7fffffffffffUL;
  452. #endif
  453. gru_start_vaddr = __va(gru_start_paddr);
  454. gru_end_paddr = gru_start_paddr + GRU_MAX_BLADES * GRU_SIZE;
  455. printk(KERN_INFO "GRU space: 0x%lx - 0x%lx\n",
  456. gru_start_paddr, gru_end_paddr);
  457. ret = misc_register(&gru_miscdev);
  458. if (ret) {
  459. printk(KERN_ERR "%s: misc_register failed\n",
  460. GRU_DRIVER_ID_STR);
  461. goto exit0;
  462. }
  463. ret = gru_proc_init();
  464. if (ret) {
  465. printk(KERN_ERR "%s: proc init failed\n", GRU_DRIVER_ID_STR);
  466. goto exit1;
  467. }
  468. ret = gru_init_tables(gru_start_paddr, gru_start_vaddr);
  469. if (ret) {
  470. printk(KERN_ERR "%s: init tables failed\n", GRU_DRIVER_ID_STR);
  471. goto exit2;
  472. }
  473. ret = gru_setup_tlb_irqs();
  474. if (ret != 0)
  475. goto exit3;
  476. gru_kservices_init();
  477. printk(KERN_INFO "%s: v%s\n", GRU_DRIVER_ID_STR,
  478. GRU_DRIVER_VERSION_STR);
  479. return 0;
  480. exit3:
  481. gru_free_tables();
  482. exit2:
  483. gru_proc_exit();
  484. exit1:
  485. misc_deregister(&gru_miscdev);
  486. exit0:
  487. return ret;
  488. }
  489. static void __exit gru_exit(void)
  490. {
  491. if (!gru_supported())
  492. return;
  493. gru_teardown_tlb_irqs();
  494. gru_kservices_exit();
  495. gru_free_tables();
  496. misc_deregister(&gru_miscdev);
  497. gru_proc_exit();
  498. mmu_notifier_synchronize();
  499. }
  500. static const struct file_operations gru_fops = {
  501. .owner = THIS_MODULE,
  502. .unlocked_ioctl = gru_file_unlocked_ioctl,
  503. .mmap = gru_file_mmap,
  504. .llseek = noop_llseek,
  505. };
  506. static struct miscdevice gru_miscdev = {
  507. .minor = MISC_DYNAMIC_MINOR,
  508. .name = "gru",
  509. .fops = &gru_fops,
  510. };
  511. const struct vm_operations_struct gru_vm_ops = {
  512. .close = gru_vma_close,
  513. .fault = gru_fault,
  514. };
  515. #ifndef MODULE
  516. fs_initcall(gru_init);
  517. #else
  518. module_init(gru_init);
  519. #endif
  520. module_exit(gru_exit);
  521. module_param(gru_options, ulong, 0644);
  522. MODULE_PARM_DESC(gru_options, "Various debug options");
  523. MODULE_AUTHOR("Silicon Graphics, Inc.");
  524. MODULE_LICENSE("GPL");
  525. MODULE_DESCRIPTION(GRU_DRIVER_ID_STR GRU_DRIVER_VERSION_STR);
  526. MODULE_VERSION(GRU_DRIVER_VERSION_STR);