pci_endpoint_test.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /**
  3. * Host side test driver to test endpoint functionality
  4. *
  5. * Copyright (C) 2017 Texas Instruments
  6. * Author: Kishon Vijay Abraham I <kishon@ti.com>
  7. */
  8. #include <linux/crc32.h>
  9. #include <linux/delay.h>
  10. #include <linux/fs.h>
  11. #include <linux/io.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/irq.h>
  14. #include <linux/miscdevice.h>
  15. #include <linux/module.h>
  16. #include <linux/mutex.h>
  17. #include <linux/random.h>
  18. #include <linux/slab.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/pci.h>
  21. #include <linux/pci_ids.h>
  22. #include <linux/pci_regs.h>
  23. #include <uapi/linux/pcitest.h>
  24. #define DRV_MODULE_NAME "pci-endpoint-test"
  25. #define IRQ_TYPE_UNDEFINED -1
  26. #define IRQ_TYPE_LEGACY 0
  27. #define IRQ_TYPE_MSI 1
  28. #define IRQ_TYPE_MSIX 2
  29. #define PCI_ENDPOINT_TEST_MAGIC 0x0
  30. #define PCI_ENDPOINT_TEST_COMMAND 0x4
  31. #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
  32. #define COMMAND_RAISE_MSI_IRQ BIT(1)
  33. #define COMMAND_RAISE_MSIX_IRQ BIT(2)
  34. #define COMMAND_READ BIT(3)
  35. #define COMMAND_WRITE BIT(4)
  36. #define COMMAND_COPY BIT(5)
  37. #define PCI_ENDPOINT_TEST_STATUS 0x8
  38. #define STATUS_READ_SUCCESS BIT(0)
  39. #define STATUS_READ_FAIL BIT(1)
  40. #define STATUS_WRITE_SUCCESS BIT(2)
  41. #define STATUS_WRITE_FAIL BIT(3)
  42. #define STATUS_COPY_SUCCESS BIT(4)
  43. #define STATUS_COPY_FAIL BIT(5)
  44. #define STATUS_IRQ_RAISED BIT(6)
  45. #define STATUS_SRC_ADDR_INVALID BIT(7)
  46. #define STATUS_DST_ADDR_INVALID BIT(8)
  47. #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
  48. #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
  49. #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
  50. #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
  51. #define PCI_ENDPOINT_TEST_SIZE 0x1c
  52. #define PCI_ENDPOINT_TEST_CHECKSUM 0x20
  53. #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
  54. #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
  55. #define PCI_ENDPOINT_TEST_FLAGS 0x2c
  56. #define FLAG_USE_DMA BIT(0)
  57. #define PCI_DEVICE_ID_TI_J721E 0xb00d
  58. #define PCI_DEVICE_ID_TI_AM654 0xb00c
  59. #define PCI_DEVICE_ID_LS1088A 0x80c0
  60. #define is_am654_pci_dev(pdev) \
  61. ((pdev)->device == PCI_DEVICE_ID_TI_AM654)
  62. #define PCI_DEVICE_ID_RENESAS_R8A774A1 0x0028
  63. #define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
  64. #define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
  65. #define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
  66. static DEFINE_IDA(pci_endpoint_test_ida);
  67. #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
  68. miscdev)
  69. static bool no_msi;
  70. module_param(no_msi, bool, 0444);
  71. MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
  72. static int irq_type = IRQ_TYPE_MSI;
  73. module_param(irq_type, int, 0444);
  74. MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
  75. enum pci_barno {
  76. BAR_0,
  77. BAR_1,
  78. BAR_2,
  79. BAR_3,
  80. BAR_4,
  81. BAR_5,
  82. };
  83. struct pci_endpoint_test {
  84. struct pci_dev *pdev;
  85. void __iomem *base;
  86. void __iomem *bar[PCI_STD_NUM_BARS];
  87. struct completion irq_raised;
  88. int last_irq;
  89. int num_irqs;
  90. int irq_type;
  91. /* mutex to protect the ioctls */
  92. struct mutex mutex;
  93. struct miscdevice miscdev;
  94. enum pci_barno test_reg_bar;
  95. size_t alignment;
  96. const char *name;
  97. };
  98. struct pci_endpoint_test_data {
  99. enum pci_barno test_reg_bar;
  100. size_t alignment;
  101. int irq_type;
  102. };
  103. static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
  104. u32 offset)
  105. {
  106. return readl(test->base + offset);
  107. }
  108. static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
  109. u32 offset, u32 value)
  110. {
  111. writel(value, test->base + offset);
  112. }
  113. static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
  114. int bar, int offset)
  115. {
  116. return readl(test->bar[bar] + offset);
  117. }
  118. static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
  119. int bar, u32 offset, u32 value)
  120. {
  121. writel(value, test->bar[bar] + offset);
  122. }
  123. static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
  124. {
  125. struct pci_endpoint_test *test = dev_id;
  126. u32 reg;
  127. reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
  128. if (reg & STATUS_IRQ_RAISED) {
  129. test->last_irq = irq;
  130. complete(&test->irq_raised);
  131. reg &= ~STATUS_IRQ_RAISED;
  132. }
  133. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
  134. reg);
  135. return IRQ_HANDLED;
  136. }
  137. static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
  138. {
  139. struct pci_dev *pdev = test->pdev;
  140. pci_free_irq_vectors(pdev);
  141. test->irq_type = IRQ_TYPE_UNDEFINED;
  142. }
  143. static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
  144. int type)
  145. {
  146. int irq = -1;
  147. struct pci_dev *pdev = test->pdev;
  148. struct device *dev = &pdev->dev;
  149. bool res = true;
  150. switch (type) {
  151. case IRQ_TYPE_LEGACY:
  152. irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
  153. if (irq < 0)
  154. dev_err(dev, "Failed to get Legacy interrupt\n");
  155. break;
  156. case IRQ_TYPE_MSI:
  157. irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
  158. if (irq < 0)
  159. dev_err(dev, "Failed to get MSI interrupts\n");
  160. break;
  161. case IRQ_TYPE_MSIX:
  162. irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
  163. if (irq < 0)
  164. dev_err(dev, "Failed to get MSI-X interrupts\n");
  165. break;
  166. default:
  167. dev_err(dev, "Invalid IRQ type selected\n");
  168. }
  169. if (irq < 0) {
  170. irq = 0;
  171. res = false;
  172. }
  173. test->irq_type = type;
  174. test->num_irqs = irq;
  175. return res;
  176. }
  177. static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
  178. {
  179. int i;
  180. struct pci_dev *pdev = test->pdev;
  181. struct device *dev = &pdev->dev;
  182. for (i = 0; i < test->num_irqs; i++)
  183. devm_free_irq(dev, pci_irq_vector(pdev, i), test);
  184. test->num_irqs = 0;
  185. }
  186. static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
  187. {
  188. int i;
  189. int err;
  190. struct pci_dev *pdev = test->pdev;
  191. struct device *dev = &pdev->dev;
  192. for (i = 0; i < test->num_irqs; i++) {
  193. err = devm_request_irq(dev, pci_irq_vector(pdev, i),
  194. pci_endpoint_test_irqhandler,
  195. IRQF_SHARED, test->name, test);
  196. if (err)
  197. goto fail;
  198. }
  199. return true;
  200. fail:
  201. switch (irq_type) {
  202. case IRQ_TYPE_LEGACY:
  203. dev_err(dev, "Failed to request IRQ %d for Legacy\n",
  204. pci_irq_vector(pdev, i));
  205. break;
  206. case IRQ_TYPE_MSI:
  207. dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
  208. pci_irq_vector(pdev, i),
  209. i + 1);
  210. break;
  211. case IRQ_TYPE_MSIX:
  212. dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
  213. pci_irq_vector(pdev, i),
  214. i + 1);
  215. break;
  216. }
  217. return false;
  218. }
  219. static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
  220. enum pci_barno barno)
  221. {
  222. int j;
  223. u32 val;
  224. int size;
  225. struct pci_dev *pdev = test->pdev;
  226. if (!test->bar[barno])
  227. return false;
  228. size = pci_resource_len(pdev, barno);
  229. if (barno == test->test_reg_bar)
  230. size = 0x4;
  231. for (j = 0; j < size; j += 4)
  232. pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
  233. for (j = 0; j < size; j += 4) {
  234. val = pci_endpoint_test_bar_readl(test, barno, j);
  235. if (val != 0xA0A0A0A0)
  236. return false;
  237. }
  238. return true;
  239. }
  240. static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
  241. {
  242. u32 val;
  243. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
  244. IRQ_TYPE_LEGACY);
  245. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
  246. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
  247. COMMAND_RAISE_LEGACY_IRQ);
  248. val = wait_for_completion_timeout(&test->irq_raised,
  249. msecs_to_jiffies(1000));
  250. if (!val)
  251. return false;
  252. return true;
  253. }
  254. static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
  255. u16 msi_num, bool msix)
  256. {
  257. u32 val;
  258. struct pci_dev *pdev = test->pdev;
  259. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
  260. msix == false ? IRQ_TYPE_MSI :
  261. IRQ_TYPE_MSIX);
  262. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
  263. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
  264. msix == false ? COMMAND_RAISE_MSI_IRQ :
  265. COMMAND_RAISE_MSIX_IRQ);
  266. val = wait_for_completion_timeout(&test->irq_raised,
  267. msecs_to_jiffies(1000));
  268. if (!val)
  269. return false;
  270. if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
  271. return true;
  272. return false;
  273. }
  274. static bool pci_endpoint_test_copy(struct pci_endpoint_test *test,
  275. unsigned long arg)
  276. {
  277. struct pci_endpoint_test_xfer_param param;
  278. bool ret = false;
  279. void *src_addr;
  280. void *dst_addr;
  281. u32 flags = 0;
  282. bool use_dma;
  283. size_t size;
  284. dma_addr_t src_phys_addr;
  285. dma_addr_t dst_phys_addr;
  286. struct pci_dev *pdev = test->pdev;
  287. struct device *dev = &pdev->dev;
  288. void *orig_src_addr;
  289. dma_addr_t orig_src_phys_addr;
  290. void *orig_dst_addr;
  291. dma_addr_t orig_dst_phys_addr;
  292. size_t offset;
  293. size_t alignment = test->alignment;
  294. int irq_type = test->irq_type;
  295. u32 src_crc32;
  296. u32 dst_crc32;
  297. int err;
  298. err = copy_from_user(&param, (void __user *)arg, sizeof(param));
  299. if (err) {
  300. dev_err(dev, "Failed to get transfer param\n");
  301. return false;
  302. }
  303. size = param.size;
  304. if (size > SIZE_MAX - alignment)
  305. goto err;
  306. use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
  307. if (use_dma)
  308. flags |= FLAG_USE_DMA;
  309. if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
  310. dev_err(dev, "Invalid IRQ type option\n");
  311. goto err;
  312. }
  313. orig_src_addr = kzalloc(size + alignment, GFP_KERNEL);
  314. if (!orig_src_addr) {
  315. dev_err(dev, "Failed to allocate source buffer\n");
  316. ret = false;
  317. goto err;
  318. }
  319. get_random_bytes(orig_src_addr, size + alignment);
  320. orig_src_phys_addr = dma_map_single(dev, orig_src_addr,
  321. size + alignment, DMA_TO_DEVICE);
  322. if (dma_mapping_error(dev, orig_src_phys_addr)) {
  323. dev_err(dev, "failed to map source buffer address\n");
  324. ret = false;
  325. goto err_src_phys_addr;
  326. }
  327. if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
  328. src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
  329. offset = src_phys_addr - orig_src_phys_addr;
  330. src_addr = orig_src_addr + offset;
  331. } else {
  332. src_phys_addr = orig_src_phys_addr;
  333. src_addr = orig_src_addr;
  334. }
  335. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
  336. lower_32_bits(src_phys_addr));
  337. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
  338. upper_32_bits(src_phys_addr));
  339. src_crc32 = crc32_le(~0, src_addr, size);
  340. orig_dst_addr = kzalloc(size + alignment, GFP_KERNEL);
  341. if (!orig_dst_addr) {
  342. dev_err(dev, "Failed to allocate destination address\n");
  343. ret = false;
  344. goto err_dst_addr;
  345. }
  346. orig_dst_phys_addr = dma_map_single(dev, orig_dst_addr,
  347. size + alignment, DMA_FROM_DEVICE);
  348. if (dma_mapping_error(dev, orig_dst_phys_addr)) {
  349. dev_err(dev, "failed to map destination buffer address\n");
  350. ret = false;
  351. goto err_dst_phys_addr;
  352. }
  353. if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
  354. dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
  355. offset = dst_phys_addr - orig_dst_phys_addr;
  356. dst_addr = orig_dst_addr + offset;
  357. } else {
  358. dst_phys_addr = orig_dst_phys_addr;
  359. dst_addr = orig_dst_addr;
  360. }
  361. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
  362. lower_32_bits(dst_phys_addr));
  363. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
  364. upper_32_bits(dst_phys_addr));
  365. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
  366. size);
  367. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
  368. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
  369. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
  370. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
  371. COMMAND_COPY);
  372. wait_for_completion(&test->irq_raised);
  373. dma_unmap_single(dev, orig_dst_phys_addr, size + alignment,
  374. DMA_FROM_DEVICE);
  375. dst_crc32 = crc32_le(~0, dst_addr, size);
  376. if (dst_crc32 == src_crc32)
  377. ret = true;
  378. err_dst_phys_addr:
  379. kfree(orig_dst_addr);
  380. err_dst_addr:
  381. dma_unmap_single(dev, orig_src_phys_addr, size + alignment,
  382. DMA_TO_DEVICE);
  383. err_src_phys_addr:
  384. kfree(orig_src_addr);
  385. err:
  386. return ret;
  387. }
  388. static bool pci_endpoint_test_write(struct pci_endpoint_test *test,
  389. unsigned long arg)
  390. {
  391. struct pci_endpoint_test_xfer_param param;
  392. bool ret = false;
  393. u32 flags = 0;
  394. bool use_dma;
  395. u32 reg;
  396. void *addr;
  397. dma_addr_t phys_addr;
  398. struct pci_dev *pdev = test->pdev;
  399. struct device *dev = &pdev->dev;
  400. void *orig_addr;
  401. dma_addr_t orig_phys_addr;
  402. size_t offset;
  403. size_t alignment = test->alignment;
  404. int irq_type = test->irq_type;
  405. size_t size;
  406. u32 crc32;
  407. int err;
  408. err = copy_from_user(&param, (void __user *)arg, sizeof(param));
  409. if (err != 0) {
  410. dev_err(dev, "Failed to get transfer param\n");
  411. return false;
  412. }
  413. size = param.size;
  414. if (size > SIZE_MAX - alignment)
  415. goto err;
  416. use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
  417. if (use_dma)
  418. flags |= FLAG_USE_DMA;
  419. if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
  420. dev_err(dev, "Invalid IRQ type option\n");
  421. goto err;
  422. }
  423. orig_addr = kzalloc(size + alignment, GFP_KERNEL);
  424. if (!orig_addr) {
  425. dev_err(dev, "Failed to allocate address\n");
  426. ret = false;
  427. goto err;
  428. }
  429. get_random_bytes(orig_addr, size + alignment);
  430. orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
  431. DMA_TO_DEVICE);
  432. if (dma_mapping_error(dev, orig_phys_addr)) {
  433. dev_err(dev, "failed to map source buffer address\n");
  434. ret = false;
  435. goto err_phys_addr;
  436. }
  437. if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
  438. phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
  439. offset = phys_addr - orig_phys_addr;
  440. addr = orig_addr + offset;
  441. } else {
  442. phys_addr = orig_phys_addr;
  443. addr = orig_addr;
  444. }
  445. crc32 = crc32_le(~0, addr, size);
  446. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
  447. crc32);
  448. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
  449. lower_32_bits(phys_addr));
  450. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
  451. upper_32_bits(phys_addr));
  452. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
  453. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
  454. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
  455. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
  456. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
  457. COMMAND_READ);
  458. wait_for_completion(&test->irq_raised);
  459. reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
  460. if (reg & STATUS_READ_SUCCESS)
  461. ret = true;
  462. dma_unmap_single(dev, orig_phys_addr, size + alignment,
  463. DMA_TO_DEVICE);
  464. err_phys_addr:
  465. kfree(orig_addr);
  466. err:
  467. return ret;
  468. }
  469. static bool pci_endpoint_test_read(struct pci_endpoint_test *test,
  470. unsigned long arg)
  471. {
  472. struct pci_endpoint_test_xfer_param param;
  473. bool ret = false;
  474. u32 flags = 0;
  475. bool use_dma;
  476. size_t size;
  477. void *addr;
  478. dma_addr_t phys_addr;
  479. struct pci_dev *pdev = test->pdev;
  480. struct device *dev = &pdev->dev;
  481. void *orig_addr;
  482. dma_addr_t orig_phys_addr;
  483. size_t offset;
  484. size_t alignment = test->alignment;
  485. int irq_type = test->irq_type;
  486. u32 crc32;
  487. int err;
  488. err = copy_from_user(&param, (void __user *)arg, sizeof(param));
  489. if (err) {
  490. dev_err(dev, "Failed to get transfer param\n");
  491. return false;
  492. }
  493. size = param.size;
  494. if (size > SIZE_MAX - alignment)
  495. goto err;
  496. use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
  497. if (use_dma)
  498. flags |= FLAG_USE_DMA;
  499. if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
  500. dev_err(dev, "Invalid IRQ type option\n");
  501. goto err;
  502. }
  503. orig_addr = kzalloc(size + alignment, GFP_KERNEL);
  504. if (!orig_addr) {
  505. dev_err(dev, "Failed to allocate destination address\n");
  506. ret = false;
  507. goto err;
  508. }
  509. orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
  510. DMA_FROM_DEVICE);
  511. if (dma_mapping_error(dev, orig_phys_addr)) {
  512. dev_err(dev, "failed to map source buffer address\n");
  513. ret = false;
  514. goto err_phys_addr;
  515. }
  516. if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
  517. phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
  518. offset = phys_addr - orig_phys_addr;
  519. addr = orig_addr + offset;
  520. } else {
  521. phys_addr = orig_phys_addr;
  522. addr = orig_addr;
  523. }
  524. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
  525. lower_32_bits(phys_addr));
  526. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
  527. upper_32_bits(phys_addr));
  528. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
  529. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
  530. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
  531. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
  532. pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
  533. COMMAND_WRITE);
  534. wait_for_completion(&test->irq_raised);
  535. dma_unmap_single(dev, orig_phys_addr, size + alignment,
  536. DMA_FROM_DEVICE);
  537. crc32 = crc32_le(~0, addr, size);
  538. if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
  539. ret = true;
  540. err_phys_addr:
  541. kfree(orig_addr);
  542. err:
  543. return ret;
  544. }
  545. static bool pci_endpoint_test_clear_irq(struct pci_endpoint_test *test)
  546. {
  547. pci_endpoint_test_release_irq(test);
  548. pci_endpoint_test_free_irq_vectors(test);
  549. return true;
  550. }
  551. static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
  552. int req_irq_type)
  553. {
  554. struct pci_dev *pdev = test->pdev;
  555. struct device *dev = &pdev->dev;
  556. if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
  557. dev_err(dev, "Invalid IRQ type option\n");
  558. return false;
  559. }
  560. if (test->irq_type == req_irq_type)
  561. return true;
  562. pci_endpoint_test_release_irq(test);
  563. pci_endpoint_test_free_irq_vectors(test);
  564. if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
  565. goto err;
  566. if (!pci_endpoint_test_request_irq(test))
  567. goto err;
  568. return true;
  569. err:
  570. pci_endpoint_test_free_irq_vectors(test);
  571. return false;
  572. }
  573. static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
  574. unsigned long arg)
  575. {
  576. int ret = -EINVAL;
  577. enum pci_barno bar;
  578. struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
  579. struct pci_dev *pdev = test->pdev;
  580. mutex_lock(&test->mutex);
  581. switch (cmd) {
  582. case PCITEST_BAR:
  583. bar = arg;
  584. if (bar < 0 || bar > 5)
  585. goto ret;
  586. if (is_am654_pci_dev(pdev) && bar == BAR_0)
  587. goto ret;
  588. ret = pci_endpoint_test_bar(test, bar);
  589. break;
  590. case PCITEST_LEGACY_IRQ:
  591. ret = pci_endpoint_test_legacy_irq(test);
  592. break;
  593. case PCITEST_MSI:
  594. case PCITEST_MSIX:
  595. ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
  596. break;
  597. case PCITEST_WRITE:
  598. ret = pci_endpoint_test_write(test, arg);
  599. break;
  600. case PCITEST_READ:
  601. ret = pci_endpoint_test_read(test, arg);
  602. break;
  603. case PCITEST_COPY:
  604. ret = pci_endpoint_test_copy(test, arg);
  605. break;
  606. case PCITEST_SET_IRQTYPE:
  607. ret = pci_endpoint_test_set_irq(test, arg);
  608. break;
  609. case PCITEST_GET_IRQTYPE:
  610. ret = irq_type;
  611. break;
  612. case PCITEST_CLEAR_IRQ:
  613. ret = pci_endpoint_test_clear_irq(test);
  614. break;
  615. }
  616. ret:
  617. mutex_unlock(&test->mutex);
  618. return ret;
  619. }
  620. static const struct file_operations pci_endpoint_test_fops = {
  621. .owner = THIS_MODULE,
  622. .unlocked_ioctl = pci_endpoint_test_ioctl,
  623. };
  624. static int pci_endpoint_test_probe(struct pci_dev *pdev,
  625. const struct pci_device_id *ent)
  626. {
  627. int err;
  628. int id;
  629. char name[24];
  630. enum pci_barno bar;
  631. void __iomem *base;
  632. struct device *dev = &pdev->dev;
  633. struct pci_endpoint_test *test;
  634. struct pci_endpoint_test_data *data;
  635. enum pci_barno test_reg_bar = BAR_0;
  636. struct miscdevice *misc_device;
  637. if (pci_is_bridge(pdev))
  638. return -ENODEV;
  639. test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
  640. if (!test)
  641. return -ENOMEM;
  642. test->test_reg_bar = 0;
  643. test->alignment = 0;
  644. test->pdev = pdev;
  645. test->irq_type = IRQ_TYPE_UNDEFINED;
  646. if (no_msi)
  647. irq_type = IRQ_TYPE_LEGACY;
  648. data = (struct pci_endpoint_test_data *)ent->driver_data;
  649. if (data) {
  650. test_reg_bar = data->test_reg_bar;
  651. test->test_reg_bar = test_reg_bar;
  652. test->alignment = data->alignment;
  653. irq_type = data->irq_type;
  654. }
  655. init_completion(&test->irq_raised);
  656. mutex_init(&test->mutex);
  657. if ((dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)) != 0) &&
  658. dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
  659. dev_err(dev, "Cannot set DMA mask\n");
  660. return -EINVAL;
  661. }
  662. err = pci_enable_device(pdev);
  663. if (err) {
  664. dev_err(dev, "Cannot enable PCI device\n");
  665. return err;
  666. }
  667. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  668. if (err) {
  669. dev_err(dev, "Cannot obtain PCI resources\n");
  670. goto err_disable_pdev;
  671. }
  672. pci_set_master(pdev);
  673. if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type)) {
  674. err = -EINVAL;
  675. goto err_disable_irq;
  676. }
  677. for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
  678. if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
  679. base = pci_ioremap_bar(pdev, bar);
  680. if (!base) {
  681. dev_err(dev, "Failed to read BAR%d\n", bar);
  682. WARN_ON(bar == test_reg_bar);
  683. }
  684. test->bar[bar] = base;
  685. }
  686. }
  687. test->base = test->bar[test_reg_bar];
  688. if (!test->base) {
  689. err = -ENOMEM;
  690. dev_err(dev, "Cannot perform PCI test without BAR%d\n",
  691. test_reg_bar);
  692. goto err_iounmap;
  693. }
  694. pci_set_drvdata(pdev, test);
  695. id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
  696. if (id < 0) {
  697. err = id;
  698. dev_err(dev, "Unable to get id\n");
  699. goto err_iounmap;
  700. }
  701. snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
  702. test->name = kstrdup(name, GFP_KERNEL);
  703. if (!test->name) {
  704. err = -ENOMEM;
  705. goto err_ida_remove;
  706. }
  707. if (!pci_endpoint_test_request_irq(test)) {
  708. err = -EINVAL;
  709. goto err_kfree_test_name;
  710. }
  711. misc_device = &test->miscdev;
  712. misc_device->minor = MISC_DYNAMIC_MINOR;
  713. misc_device->name = kstrdup(name, GFP_KERNEL);
  714. if (!misc_device->name) {
  715. err = -ENOMEM;
  716. goto err_release_irq;
  717. }
  718. misc_device->fops = &pci_endpoint_test_fops,
  719. err = misc_register(misc_device);
  720. if (err) {
  721. dev_err(dev, "Failed to register device\n");
  722. goto err_kfree_name;
  723. }
  724. return 0;
  725. err_kfree_name:
  726. kfree(misc_device->name);
  727. err_release_irq:
  728. pci_endpoint_test_release_irq(test);
  729. err_kfree_test_name:
  730. kfree(test->name);
  731. err_ida_remove:
  732. ida_simple_remove(&pci_endpoint_test_ida, id);
  733. err_iounmap:
  734. for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
  735. if (test->bar[bar])
  736. pci_iounmap(pdev, test->bar[bar]);
  737. }
  738. err_disable_irq:
  739. pci_endpoint_test_free_irq_vectors(test);
  740. pci_release_regions(pdev);
  741. err_disable_pdev:
  742. pci_disable_device(pdev);
  743. return err;
  744. }
  745. static void pci_endpoint_test_remove(struct pci_dev *pdev)
  746. {
  747. int id;
  748. enum pci_barno bar;
  749. struct pci_endpoint_test *test = pci_get_drvdata(pdev);
  750. struct miscdevice *misc_device = &test->miscdev;
  751. if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
  752. return;
  753. if (id < 0)
  754. return;
  755. misc_deregister(&test->miscdev);
  756. kfree(misc_device->name);
  757. kfree(test->name);
  758. ida_simple_remove(&pci_endpoint_test_ida, id);
  759. for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
  760. if (test->bar[bar])
  761. pci_iounmap(pdev, test->bar[bar]);
  762. }
  763. pci_endpoint_test_release_irq(test);
  764. pci_endpoint_test_free_irq_vectors(test);
  765. pci_release_regions(pdev);
  766. pci_disable_device(pdev);
  767. }
  768. static const struct pci_endpoint_test_data default_data = {
  769. .test_reg_bar = BAR_0,
  770. .alignment = SZ_4K,
  771. .irq_type = IRQ_TYPE_MSI,
  772. };
  773. static const struct pci_endpoint_test_data am654_data = {
  774. .test_reg_bar = BAR_2,
  775. .alignment = SZ_64K,
  776. .irq_type = IRQ_TYPE_MSI,
  777. };
  778. static const struct pci_endpoint_test_data j721e_data = {
  779. .alignment = 256,
  780. .irq_type = IRQ_TYPE_MSI,
  781. };
  782. static const struct pci_device_id pci_endpoint_test_tbl[] = {
  783. { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
  784. .driver_data = (kernel_ulong_t)&default_data,
  785. },
  786. { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x),
  787. .driver_data = (kernel_ulong_t)&default_data,
  788. },
  789. { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0),
  790. .driver_data = (kernel_ulong_t)&default_data,
  791. },
  792. { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A),
  793. .driver_data = (kernel_ulong_t)&default_data,
  794. },
  795. { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
  796. { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
  797. .driver_data = (kernel_ulong_t)&am654_data
  798. },
  799. { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
  800. { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
  801. { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
  802. { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
  803. { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
  804. .driver_data = (kernel_ulong_t)&j721e_data,
  805. },
  806. { }
  807. };
  808. MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
  809. static struct pci_driver pci_endpoint_test_driver = {
  810. .name = DRV_MODULE_NAME,
  811. .id_table = pci_endpoint_test_tbl,
  812. .probe = pci_endpoint_test_probe,
  813. .remove = pci_endpoint_test_remove,
  814. };
  815. module_pci_driver(pci_endpoint_test_driver);
  816. MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
  817. MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
  818. MODULE_LICENSE("GPL v2");