pch_phub.c 27 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/kernel.h>
  7. #include <linux/types.h>
  8. #include <linux/fs.h>
  9. #include <linux/uaccess.h>
  10. #include <linux/string.h>
  11. #include <linux/pci.h>
  12. #include <linux/io.h>
  13. #include <linux/delay.h>
  14. #include <linux/mutex.h>
  15. #include <linux/if_ether.h>
  16. #include <linux/ctype.h>
  17. #include <linux/dmi.h>
  18. #include <linux/of.h>
  19. #define PHUB_STATUS 0x00 /* Status Register offset */
  20. #define PHUB_CONTROL 0x04 /* Control Register offset */
  21. #define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */
  22. #define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */
  23. #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
  24. #define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address
  25. offset */
  26. #define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address
  27. offset */
  28. #define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
  29. (Intel EG20T PCH)*/
  30. #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
  31. offset(LAPIS Semicon ML7213)
  32. */
  33. #define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
  34. offset(LAPIS Semicon ML7223)
  35. */
  36. /* MAX number of INT_REDUCE_CONTROL registers */
  37. #define MAX_NUM_INT_REDUCE_CONTROL_REG 128
  38. #define PCI_DEVICE_ID_PCH1_PHUB 0x8801
  39. #define PCH_MINOR_NOS 1
  40. #define CLKCFG_CAN_50MHZ 0x12000000
  41. #define CLKCFG_CANCLK_MASK 0xFF000000
  42. #define CLKCFG_UART_MASK 0xFFFFFF
  43. /* CM-iTC */
  44. #define CLKCFG_UART_48MHZ (1 << 16)
  45. #define CLKCFG_UART_25MHZ (2 << 16)
  46. #define CLKCFG_BAUDDIV (2 << 20)
  47. #define CLKCFG_PLL2VCO (8 << 9)
  48. #define CLKCFG_UARTCLKSEL (1 << 18)
  49. /* Macros for ML7213 */
  50. #define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A
  51. /* Macros for ML7223 */
  52. #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
  53. #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
  54. /* Macros for ML7831 */
  55. #define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801
  56. /* SROM ACCESS Macro */
  57. #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
  58. /* Registers address offset */
  59. #define PCH_PHUB_ID_REG 0x0000
  60. #define PCH_PHUB_QUEUE_PRI_VAL_REG 0x0004
  61. #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG 0x0008
  62. #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG 0x000C
  63. #define PCH_PHUB_COMP_RESP_TIMEOUT_REG 0x0010
  64. #define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014
  65. #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018
  66. #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020
  67. #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024
  68. #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028
  69. #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C
  70. #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040
  71. #define CLKCFG_REG_OFFSET 0x500
  72. #define FUNCSEL_REG_OFFSET 0x508
  73. #define PCH_PHUB_OROM_SIZE 15360
  74. /**
  75. * struct pch_phub_reg - PHUB register structure
  76. * @phub_id_reg: PHUB_ID register val
  77. * @q_pri_val_reg: QUEUE_PRI_VAL register val
  78. * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val
  79. * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val
  80. * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val
  81. * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val
  82. * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val
  83. * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val
  84. * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val
  85. * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val
  86. * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val
  87. * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val
  88. * @clkcfg_reg: CLK CFG register val
  89. * @funcsel_reg: Function select register value
  90. * @pch_phub_base_address: Register base address
  91. * @pch_phub_extrom_base_address: external rom base address
  92. * @pch_mac_start_address: MAC address area start address
  93. * @pch_opt_rom_start_address: Option ROM start address
  94. * @ioh_type: Save IOH type
  95. * @pdev: pointer to pci device struct
  96. */
  97. struct pch_phub_reg {
  98. u32 phub_id_reg;
  99. u32 q_pri_val_reg;
  100. u32 rc_q_maxsize_reg;
  101. u32 bri_q_maxsize_reg;
  102. u32 comp_resp_timeout_reg;
  103. u32 bus_slave_control_reg;
  104. u32 deadlock_avoid_type_reg;
  105. u32 intpin_reg_wpermit_reg0;
  106. u32 intpin_reg_wpermit_reg1;
  107. u32 intpin_reg_wpermit_reg2;
  108. u32 intpin_reg_wpermit_reg3;
  109. u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
  110. u32 clkcfg_reg;
  111. u32 funcsel_reg;
  112. void __iomem *pch_phub_base_address;
  113. void __iomem *pch_phub_extrom_base_address;
  114. u32 pch_mac_start_address;
  115. u32 pch_opt_rom_start_address;
  116. int ioh_type;
  117. struct pci_dev *pdev;
  118. };
  119. /* SROM SPEC for MAC address assignment offset */
  120. static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa};
  121. static DEFINE_MUTEX(pch_phub_mutex);
  122. /**
  123. * pch_phub_read_modify_write_reg() - Reading modifying and writing register
  124. * @chip: Pointer to the PHUB register structure
  125. * @reg_addr_offset: Register offset address value.
  126. * @data: Writing value.
  127. * @mask: Mask value.
  128. */
  129. static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
  130. unsigned int reg_addr_offset,
  131. unsigned int data, unsigned int mask)
  132. {
  133. void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
  134. iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
  135. }
  136. /* pch_phub_save_reg_conf - saves register configuration */
  137. static void __maybe_unused pch_phub_save_reg_conf(struct pci_dev *pdev)
  138. {
  139. unsigned int i;
  140. struct pch_phub_reg *chip = pci_get_drvdata(pdev);
  141. void __iomem *p = chip->pch_phub_base_address;
  142. chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
  143. chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
  144. chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
  145. chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
  146. chip->comp_resp_timeout_reg =
  147. ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
  148. chip->bus_slave_control_reg =
  149. ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
  150. chip->deadlock_avoid_type_reg =
  151. ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
  152. chip->intpin_reg_wpermit_reg0 =
  153. ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
  154. chip->intpin_reg_wpermit_reg1 =
  155. ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
  156. chip->intpin_reg_wpermit_reg2 =
  157. ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
  158. chip->intpin_reg_wpermit_reg3 =
  159. ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
  160. dev_dbg(&pdev->dev, "%s : "
  161. "chip->phub_id_reg=%x, "
  162. "chip->q_pri_val_reg=%x, "
  163. "chip->rc_q_maxsize_reg=%x, "
  164. "chip->bri_q_maxsize_reg=%x, "
  165. "chip->comp_resp_timeout_reg=%x, "
  166. "chip->bus_slave_control_reg=%x, "
  167. "chip->deadlock_avoid_type_reg=%x, "
  168. "chip->intpin_reg_wpermit_reg0=%x, "
  169. "chip->intpin_reg_wpermit_reg1=%x, "
  170. "chip->intpin_reg_wpermit_reg2=%x, "
  171. "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
  172. chip->phub_id_reg,
  173. chip->q_pri_val_reg,
  174. chip->rc_q_maxsize_reg,
  175. chip->bri_q_maxsize_reg,
  176. chip->comp_resp_timeout_reg,
  177. chip->bus_slave_control_reg,
  178. chip->deadlock_avoid_type_reg,
  179. chip->intpin_reg_wpermit_reg0,
  180. chip->intpin_reg_wpermit_reg1,
  181. chip->intpin_reg_wpermit_reg2,
  182. chip->intpin_reg_wpermit_reg3);
  183. for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
  184. chip->int_reduce_control_reg[i] =
  185. ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
  186. dev_dbg(&pdev->dev, "%s : "
  187. "chip->int_reduce_control_reg[%d]=%x\n",
  188. __func__, i, chip->int_reduce_control_reg[i]);
  189. }
  190. chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
  191. if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
  192. chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
  193. }
  194. /* pch_phub_restore_reg_conf - restore register configuration */
  195. static void __maybe_unused pch_phub_restore_reg_conf(struct pci_dev *pdev)
  196. {
  197. unsigned int i;
  198. struct pch_phub_reg *chip = pci_get_drvdata(pdev);
  199. void __iomem *p;
  200. p = chip->pch_phub_base_address;
  201. iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
  202. iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
  203. iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
  204. iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
  205. iowrite32(chip->comp_resp_timeout_reg,
  206. p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
  207. iowrite32(chip->bus_slave_control_reg,
  208. p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
  209. iowrite32(chip->deadlock_avoid_type_reg,
  210. p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
  211. iowrite32(chip->intpin_reg_wpermit_reg0,
  212. p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
  213. iowrite32(chip->intpin_reg_wpermit_reg1,
  214. p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
  215. iowrite32(chip->intpin_reg_wpermit_reg2,
  216. p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
  217. iowrite32(chip->intpin_reg_wpermit_reg3,
  218. p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
  219. dev_dbg(&pdev->dev, "%s : "
  220. "chip->phub_id_reg=%x, "
  221. "chip->q_pri_val_reg=%x, "
  222. "chip->rc_q_maxsize_reg=%x, "
  223. "chip->bri_q_maxsize_reg=%x, "
  224. "chip->comp_resp_timeout_reg=%x, "
  225. "chip->bus_slave_control_reg=%x, "
  226. "chip->deadlock_avoid_type_reg=%x, "
  227. "chip->intpin_reg_wpermit_reg0=%x, "
  228. "chip->intpin_reg_wpermit_reg1=%x, "
  229. "chip->intpin_reg_wpermit_reg2=%x, "
  230. "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
  231. chip->phub_id_reg,
  232. chip->q_pri_val_reg,
  233. chip->rc_q_maxsize_reg,
  234. chip->bri_q_maxsize_reg,
  235. chip->comp_resp_timeout_reg,
  236. chip->bus_slave_control_reg,
  237. chip->deadlock_avoid_type_reg,
  238. chip->intpin_reg_wpermit_reg0,
  239. chip->intpin_reg_wpermit_reg1,
  240. chip->intpin_reg_wpermit_reg2,
  241. chip->intpin_reg_wpermit_reg3);
  242. for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
  243. iowrite32(chip->int_reduce_control_reg[i],
  244. p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
  245. dev_dbg(&pdev->dev, "%s : "
  246. "chip->int_reduce_control_reg[%d]=%x\n",
  247. __func__, i, chip->int_reduce_control_reg[i]);
  248. }
  249. iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
  250. if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
  251. iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
  252. }
  253. /**
  254. * pch_phub_read_serial_rom() - Reading Serial ROM
  255. * @chip: Pointer to the PHUB register structure
  256. * @offset_address: Serial ROM offset address to read.
  257. * @data: Read buffer for specified Serial ROM value.
  258. */
  259. static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
  260. unsigned int offset_address, u8 *data)
  261. {
  262. void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
  263. offset_address;
  264. *data = ioread8(mem_addr);
  265. }
  266. /**
  267. * pch_phub_write_serial_rom() - Writing Serial ROM
  268. * @chip: Pointer to the PHUB register structure
  269. * @offset_address: Serial ROM offset address.
  270. * @data: Serial ROM value to write.
  271. */
  272. static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
  273. unsigned int offset_address, u8 data)
  274. {
  275. void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
  276. (offset_address & PCH_WORD_ADDR_MASK);
  277. int i;
  278. unsigned int word_data;
  279. unsigned int pos;
  280. unsigned int mask;
  281. pos = (offset_address % 4) * 8;
  282. mask = ~(0xFF << pos);
  283. iowrite32(PCH_PHUB_ROM_WRITE_ENABLE,
  284. chip->pch_phub_extrom_base_address + PHUB_CONTROL);
  285. word_data = ioread32(mem_addr);
  286. iowrite32((word_data & mask) | (u32)data << pos, mem_addr);
  287. i = 0;
  288. while (ioread8(chip->pch_phub_extrom_base_address +
  289. PHUB_STATUS) != 0x00) {
  290. msleep(1);
  291. if (i == PHUB_TIMEOUT)
  292. return -ETIMEDOUT;
  293. i++;
  294. }
  295. iowrite32(PCH_PHUB_ROM_WRITE_DISABLE,
  296. chip->pch_phub_extrom_base_address + PHUB_CONTROL);
  297. return 0;
  298. }
  299. /**
  300. * pch_phub_read_serial_rom_val() - Read Serial ROM value
  301. * @chip: Pointer to the PHUB register structure
  302. * @offset_address: Serial ROM address offset value.
  303. * @data: Serial ROM value to read.
  304. */
  305. static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
  306. unsigned int offset_address, u8 *data)
  307. {
  308. unsigned int mem_addr;
  309. mem_addr = chip->pch_mac_start_address +
  310. pch_phub_mac_offset[offset_address];
  311. pch_phub_read_serial_rom(chip, mem_addr, data);
  312. }
  313. /**
  314. * pch_phub_write_serial_rom_val() - writing Serial ROM value
  315. * @chip: Pointer to the PHUB register structure
  316. * @offset_address: Serial ROM address offset value.
  317. * @data: Serial ROM value.
  318. */
  319. static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
  320. unsigned int offset_address, u8 data)
  321. {
  322. int retval;
  323. unsigned int mem_addr;
  324. mem_addr = chip->pch_mac_start_address +
  325. pch_phub_mac_offset[offset_address];
  326. retval = pch_phub_write_serial_rom(chip, mem_addr, data);
  327. return retval;
  328. }
  329. /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
  330. * for Gigabit Ethernet MAC address
  331. */
  332. static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
  333. {
  334. int retval;
  335. retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
  336. retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
  337. retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
  338. retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
  339. retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
  340. retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
  341. retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
  342. retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
  343. retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
  344. retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
  345. retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
  346. retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
  347. retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
  348. retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
  349. retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
  350. retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
  351. retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
  352. retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
  353. retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
  354. retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
  355. retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
  356. retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
  357. retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
  358. retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
  359. return retval;
  360. }
  361. /* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
  362. * for Gigabit Ethernet MAC address
  363. */
  364. static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
  365. {
  366. int retval;
  367. u32 offset_addr;
  368. offset_addr = 0x200;
  369. retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
  370. retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
  371. retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
  372. retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
  373. retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
  374. retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
  375. retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
  376. retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
  377. retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
  378. retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
  379. retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
  380. retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
  381. retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
  382. retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
  383. retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
  384. retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
  385. retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
  386. retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
  387. retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
  388. retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
  389. retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
  390. retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
  391. retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
  392. retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
  393. return retval;
  394. }
  395. /**
  396. * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
  397. * @chip: Pointer to the PHUB register structure
  398. * @data: Buffer of the Gigabit Ethernet MAC address value.
  399. */
  400. static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
  401. {
  402. int i;
  403. for (i = 0; i < ETH_ALEN; i++)
  404. pch_phub_read_serial_rom_val(chip, i, &data[i]);
  405. }
  406. /**
  407. * pch_phub_write_gbe_mac_addr() - Write MAC address
  408. * @chip: Pointer to the PHUB register structure
  409. * @data: Gigabit Ethernet MAC address value.
  410. */
  411. static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
  412. {
  413. int retval;
  414. int i;
  415. if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/
  416. retval = pch_phub_gbe_serial_rom_conf(chip);
  417. else /* ML7223 */
  418. retval = pch_phub_gbe_serial_rom_conf_mp(chip);
  419. if (retval)
  420. return retval;
  421. for (i = 0; i < ETH_ALEN; i++) {
  422. retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
  423. if (retval)
  424. return retval;
  425. }
  426. return retval;
  427. }
  428. static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
  429. struct bin_attribute *attr, char *buf,
  430. loff_t off, size_t count)
  431. {
  432. unsigned int rom_signature;
  433. unsigned char rom_length;
  434. unsigned int tmp;
  435. unsigned int addr_offset;
  436. unsigned int orom_size;
  437. int ret;
  438. int err;
  439. ssize_t rom_size;
  440. struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
  441. ret = mutex_lock_interruptible(&pch_phub_mutex);
  442. if (ret) {
  443. err = -ERESTARTSYS;
  444. goto return_err_nomutex;
  445. }
  446. /* Get Rom signature */
  447. chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
  448. if (!chip->pch_phub_extrom_base_address) {
  449. err = -ENODATA;
  450. goto exrom_map_err;
  451. }
  452. pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
  453. (unsigned char *)&rom_signature);
  454. rom_signature &= 0xff;
  455. pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
  456. (unsigned char *)&tmp);
  457. rom_signature |= (tmp & 0xff) << 8;
  458. if (rom_signature == 0xAA55) {
  459. pch_phub_read_serial_rom(chip,
  460. chip->pch_opt_rom_start_address + 2,
  461. &rom_length);
  462. orom_size = rom_length * 512;
  463. if (orom_size < off) {
  464. addr_offset = 0;
  465. goto return_ok;
  466. }
  467. if (orom_size < count) {
  468. addr_offset = 0;
  469. goto return_ok;
  470. }
  471. for (addr_offset = 0; addr_offset < count; addr_offset++) {
  472. pch_phub_read_serial_rom(chip,
  473. chip->pch_opt_rom_start_address + addr_offset + off,
  474. &buf[addr_offset]);
  475. }
  476. } else {
  477. err = -ENODATA;
  478. goto return_err;
  479. }
  480. return_ok:
  481. pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
  482. mutex_unlock(&pch_phub_mutex);
  483. return addr_offset;
  484. return_err:
  485. pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
  486. exrom_map_err:
  487. mutex_unlock(&pch_phub_mutex);
  488. return_err_nomutex:
  489. return err;
  490. }
  491. static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
  492. struct bin_attribute *attr,
  493. char *buf, loff_t off, size_t count)
  494. {
  495. int err;
  496. unsigned int addr_offset;
  497. int ret;
  498. ssize_t rom_size;
  499. struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
  500. ret = mutex_lock_interruptible(&pch_phub_mutex);
  501. if (ret)
  502. return -ERESTARTSYS;
  503. if (off > PCH_PHUB_OROM_SIZE) {
  504. addr_offset = 0;
  505. goto return_ok;
  506. }
  507. if (count > PCH_PHUB_OROM_SIZE) {
  508. addr_offset = 0;
  509. goto return_ok;
  510. }
  511. chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
  512. if (!chip->pch_phub_extrom_base_address) {
  513. err = -ENOMEM;
  514. goto exrom_map_err;
  515. }
  516. for (addr_offset = 0; addr_offset < count; addr_offset++) {
  517. if (PCH_PHUB_OROM_SIZE < off + addr_offset)
  518. goto return_ok;
  519. ret = pch_phub_write_serial_rom(chip,
  520. chip->pch_opt_rom_start_address + addr_offset + off,
  521. buf[addr_offset]);
  522. if (ret) {
  523. err = ret;
  524. goto return_err;
  525. }
  526. }
  527. return_ok:
  528. pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
  529. mutex_unlock(&pch_phub_mutex);
  530. return addr_offset;
  531. return_err:
  532. pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
  533. exrom_map_err:
  534. mutex_unlock(&pch_phub_mutex);
  535. return err;
  536. }
  537. static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr,
  538. char *buf)
  539. {
  540. u8 mac[8];
  541. struct pch_phub_reg *chip = dev_get_drvdata(dev);
  542. ssize_t rom_size;
  543. chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
  544. if (!chip->pch_phub_extrom_base_address)
  545. return -ENOMEM;
  546. pch_phub_read_gbe_mac_addr(chip, mac);
  547. pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
  548. return sprintf(buf, "%pM\n", mac);
  549. }
  550. static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr,
  551. const char *buf, size_t count)
  552. {
  553. u8 mac[ETH_ALEN];
  554. ssize_t rom_size;
  555. struct pch_phub_reg *chip = dev_get_drvdata(dev);
  556. int ret;
  557. if (!mac_pton(buf, mac))
  558. return -EINVAL;
  559. chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
  560. if (!chip->pch_phub_extrom_base_address)
  561. return -ENOMEM;
  562. ret = pch_phub_write_gbe_mac_addr(chip, mac);
  563. pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
  564. if (ret)
  565. return ret;
  566. return count;
  567. }
  568. static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac);
  569. static const struct bin_attribute pch_bin_attr = {
  570. .attr = {
  571. .name = "pch_firmware",
  572. .mode = S_IRUGO | S_IWUSR,
  573. },
  574. .size = PCH_PHUB_OROM_SIZE + 1,
  575. .read = pch_phub_bin_read,
  576. .write = pch_phub_bin_write,
  577. };
  578. static int pch_phub_probe(struct pci_dev *pdev,
  579. const struct pci_device_id *id)
  580. {
  581. int ret;
  582. struct pch_phub_reg *chip;
  583. chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL);
  584. if (chip == NULL)
  585. return -ENOMEM;
  586. ret = pci_enable_device(pdev);
  587. if (ret) {
  588. dev_err(&pdev->dev,
  589. "%s : pci_enable_device FAILED(ret=%d)", __func__, ret);
  590. goto err_pci_enable_dev;
  591. }
  592. dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
  593. ret);
  594. ret = pci_request_regions(pdev, KBUILD_MODNAME);
  595. if (ret) {
  596. dev_err(&pdev->dev,
  597. "%s : pci_request_regions FAILED(ret=%d)", __func__, ret);
  598. goto err_req_regions;
  599. }
  600. dev_dbg(&pdev->dev, "%s : "
  601. "pci_request_regions returns %d\n", __func__, ret);
  602. chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
  603. if (chip->pch_phub_base_address == NULL) {
  604. dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
  605. ret = -ENOMEM;
  606. goto err_pci_iomap;
  607. }
  608. dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
  609. "in pch_phub_base_address variable is %p\n", __func__,
  610. chip->pch_phub_base_address);
  611. chip->pdev = pdev; /* Save pci device struct */
  612. if (id->driver_data == 1) { /* EG20T PCH */
  613. const char *board_name;
  614. unsigned int prefetch = 0x000affaa;
  615. if (pdev->dev.of_node)
  616. of_property_read_u32(pdev->dev.of_node,
  617. "intel,eg20t-prefetch",
  618. &prefetch);
  619. ret = sysfs_create_file(&pdev->dev.kobj,
  620. &dev_attr_pch_mac.attr);
  621. if (ret)
  622. goto err_sysfs_create;
  623. ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
  624. if (ret)
  625. goto exit_bin_attr;
  626. pch_phub_read_modify_write_reg(chip,
  627. (unsigned int)CLKCFG_REG_OFFSET,
  628. CLKCFG_CAN_50MHZ,
  629. CLKCFG_CANCLK_MASK);
  630. /* quirk for CM-iTC board */
  631. board_name = dmi_get_system_info(DMI_BOARD_NAME);
  632. if (board_name && strstr(board_name, "CM-iTC"))
  633. pch_phub_read_modify_write_reg(chip,
  634. (unsigned int)CLKCFG_REG_OFFSET,
  635. CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
  636. CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
  637. CLKCFG_UART_MASK);
  638. /* set the prefech value */
  639. iowrite32(prefetch, chip->pch_phub_base_address + 0x14);
  640. /* set the interrupt delay value */
  641. iowrite32(0x25, chip->pch_phub_base_address + 0x44);
  642. chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
  643. chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
  644. /* quirk for MIPS Boston platform */
  645. if (pdev->dev.of_node) {
  646. if (of_machine_is_compatible("img,boston")) {
  647. pch_phub_read_modify_write_reg(chip,
  648. (unsigned int)CLKCFG_REG_OFFSET,
  649. CLKCFG_UART_25MHZ,
  650. CLKCFG_UART_MASK);
  651. }
  652. }
  653. } else if (id->driver_data == 2) { /* ML7213 IOH */
  654. ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
  655. if (ret)
  656. goto err_sysfs_create;
  657. /* set the prefech value
  658. * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
  659. * Device4(SDIO #0,1,2):f
  660. * Device6(SATA 2):f
  661. * Device8(USB OHCI #0/ USB EHCI #0):a
  662. */
  663. iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
  664. chip->pch_opt_rom_start_address =\
  665. PCH_PHUB_ROM_START_ADDR_ML7213;
  666. } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/
  667. /* set the prefech value
  668. * Device8(GbE)
  669. */
  670. iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
  671. /* set the interrupt delay value */
  672. iowrite32(0x25, chip->pch_phub_base_address + 0x140);
  673. chip->pch_opt_rom_start_address =\
  674. PCH_PHUB_ROM_START_ADDR_ML7223;
  675. chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
  676. } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/
  677. ret = sysfs_create_file(&pdev->dev.kobj,
  678. &dev_attr_pch_mac.attr);
  679. if (ret)
  680. goto err_sysfs_create;
  681. ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
  682. if (ret)
  683. goto exit_bin_attr;
  684. /* set the prefech value
  685. * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a
  686. * Device4(SDIO #0,1):f
  687. * Device6(SATA 2):f
  688. */
  689. iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
  690. chip->pch_opt_rom_start_address =\
  691. PCH_PHUB_ROM_START_ADDR_ML7223;
  692. chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
  693. } else if (id->driver_data == 5) { /* ML7831 */
  694. ret = sysfs_create_file(&pdev->dev.kobj,
  695. &dev_attr_pch_mac.attr);
  696. if (ret)
  697. goto err_sysfs_create;
  698. ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
  699. if (ret)
  700. goto exit_bin_attr;
  701. /* set the prefech value */
  702. iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
  703. /* set the interrupt delay value */
  704. iowrite32(0x25, chip->pch_phub_base_address + 0x44);
  705. chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
  706. chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
  707. }
  708. chip->ioh_type = id->driver_data;
  709. pci_set_drvdata(pdev, chip);
  710. return 0;
  711. exit_bin_attr:
  712. sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
  713. err_sysfs_create:
  714. pci_iounmap(pdev, chip->pch_phub_base_address);
  715. err_pci_iomap:
  716. pci_release_regions(pdev);
  717. err_req_regions:
  718. pci_disable_device(pdev);
  719. err_pci_enable_dev:
  720. kfree(chip);
  721. dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
  722. return ret;
  723. }
  724. static void pch_phub_remove(struct pci_dev *pdev)
  725. {
  726. struct pch_phub_reg *chip = pci_get_drvdata(pdev);
  727. sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
  728. sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
  729. pci_iounmap(pdev, chip->pch_phub_base_address);
  730. pci_release_regions(pdev);
  731. pci_disable_device(pdev);
  732. kfree(chip);
  733. }
  734. static int __maybe_unused pch_phub_suspend(struct device *dev_d)
  735. {
  736. device_wakeup_disable(dev_d);
  737. return 0;
  738. }
  739. static int __maybe_unused pch_phub_resume(struct device *dev_d)
  740. {
  741. device_wakeup_disable(dev_d);
  742. return 0;
  743. }
  744. static const struct pci_device_id pch_phub_pcidev_id[] = {
  745. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), 1, },
  746. { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2, },
  747. { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3, },
  748. { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4, },
  749. { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), 5, },
  750. { }
  751. };
  752. MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id);
  753. static SIMPLE_DEV_PM_OPS(pch_phub_pm_ops, pch_phub_suspend, pch_phub_resume);
  754. static struct pci_driver pch_phub_driver = {
  755. .name = "pch_phub",
  756. .id_table = pch_phub_pcidev_id,
  757. .probe = pch_phub_probe,
  758. .remove = pch_phub_remove,
  759. .driver.pm = &pch_phub_pm_ops,
  760. };
  761. module_pci_driver(pch_phub_driver);
  762. MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB");
  763. MODULE_LICENSE("GPL");