lattice-ecp3-config.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2012 Stefan Roese <sr@denx.de>
  4. */
  5. #include <linux/device.h>
  6. #include <linux/firmware.h>
  7. #include <linux/module.h>
  8. #include <linux/errno.h>
  9. #include <linux/kernel.h>
  10. #include <linux/spi/spi.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/delay.h>
  13. #include <asm/unaligned.h>
  14. #define FIRMWARE_NAME "lattice-ecp3.bit"
  15. /*
  16. * The JTAG ID's of the supported FPGA's. The ID is 32bit wide
  17. * reversed as noted in the manual.
  18. */
  19. #define ID_ECP3_17 0xc2088080
  20. #define ID_ECP3_35 0xc2048080
  21. /* FPGA commands */
  22. #define FPGA_CMD_READ_ID 0x07 /* plus 24 bits */
  23. #define FPGA_CMD_READ_STATUS 0x09 /* plus 24 bits */
  24. #define FPGA_CMD_CLEAR 0x70
  25. #define FPGA_CMD_REFRESH 0x71
  26. #define FPGA_CMD_WRITE_EN 0x4a /* plus 2 bits */
  27. #define FPGA_CMD_WRITE_DIS 0x4f /* plus 8 bits */
  28. #define FPGA_CMD_WRITE_INC 0x41 /* plus 0 bits */
  29. /*
  30. * The status register is 32bit revered, DONE is bit 17 from the TN1222.pdf
  31. * (LatticeECP3 Slave SPI Port User's Guide)
  32. */
  33. #define FPGA_STATUS_DONE 0x00004000
  34. #define FPGA_STATUS_CLEARED 0x00010000
  35. #define FPGA_CLEAR_TIMEOUT 5000 /* max. 5000ms for FPGA clear */
  36. #define FPGA_CLEAR_MSLEEP 10
  37. #define FPGA_CLEAR_LOOP_COUNT (FPGA_CLEAR_TIMEOUT / FPGA_CLEAR_MSLEEP)
  38. struct fpga_data {
  39. struct completion fw_loaded;
  40. };
  41. struct ecp3_dev {
  42. u32 jedec_id;
  43. char *name;
  44. };
  45. static const struct ecp3_dev ecp3_dev[] = {
  46. {
  47. .jedec_id = ID_ECP3_17,
  48. .name = "Lattice ECP3-17",
  49. },
  50. {
  51. .jedec_id = ID_ECP3_35,
  52. .name = "Lattice ECP3-35",
  53. },
  54. };
  55. static void firmware_load(const struct firmware *fw, void *context)
  56. {
  57. struct spi_device *spi = (struct spi_device *)context;
  58. struct fpga_data *data = spi_get_drvdata(spi);
  59. u8 *buffer;
  60. u8 txbuf[8];
  61. u8 rxbuf[8];
  62. int rx_len = 8;
  63. int i;
  64. u32 jedec_id;
  65. u32 status;
  66. if (fw == NULL) {
  67. dev_err(&spi->dev, "Cannot load firmware, aborting\n");
  68. goto out;
  69. }
  70. if (fw->size == 0) {
  71. dev_err(&spi->dev, "Error: Firmware size is 0!\n");
  72. goto out;
  73. }
  74. /* Fill dummy data (24 stuffing bits for commands) */
  75. txbuf[1] = 0x00;
  76. txbuf[2] = 0x00;
  77. txbuf[3] = 0x00;
  78. /* Trying to speak with the FPGA via SPI... */
  79. txbuf[0] = FPGA_CMD_READ_ID;
  80. spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
  81. jedec_id = get_unaligned_be32(&rxbuf[4]);
  82. dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id);
  83. for (i = 0; i < ARRAY_SIZE(ecp3_dev); i++) {
  84. if (jedec_id == ecp3_dev[i].jedec_id)
  85. break;
  86. }
  87. if (i == ARRAY_SIZE(ecp3_dev)) {
  88. dev_err(&spi->dev,
  89. "Error: No supported FPGA detected (JEDEC_ID=%08x)!\n",
  90. jedec_id);
  91. goto out;
  92. }
  93. dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name);
  94. txbuf[0] = FPGA_CMD_READ_STATUS;
  95. spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
  96. status = get_unaligned_be32(&rxbuf[4]);
  97. dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
  98. buffer = kzalloc(fw->size + 8, GFP_KERNEL);
  99. if (!buffer) {
  100. dev_err(&spi->dev, "Error: Can't allocate memory!\n");
  101. goto out;
  102. }
  103. /*
  104. * Insert WRITE_INC command into stream (one SPI frame)
  105. */
  106. buffer[0] = FPGA_CMD_WRITE_INC;
  107. buffer[1] = 0xff;
  108. buffer[2] = 0xff;
  109. buffer[3] = 0xff;
  110. memcpy(buffer + 4, fw->data, fw->size);
  111. txbuf[0] = FPGA_CMD_REFRESH;
  112. spi_write(spi, txbuf, 4);
  113. txbuf[0] = FPGA_CMD_WRITE_EN;
  114. spi_write(spi, txbuf, 4);
  115. txbuf[0] = FPGA_CMD_CLEAR;
  116. spi_write(spi, txbuf, 4);
  117. /*
  118. * Wait for FPGA memory to become cleared
  119. */
  120. for (i = 0; i < FPGA_CLEAR_LOOP_COUNT; i++) {
  121. txbuf[0] = FPGA_CMD_READ_STATUS;
  122. spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
  123. status = get_unaligned_be32(&rxbuf[4]);
  124. if (status == FPGA_STATUS_CLEARED)
  125. break;
  126. msleep(FPGA_CLEAR_MSLEEP);
  127. }
  128. if (i == FPGA_CLEAR_LOOP_COUNT) {
  129. dev_err(&spi->dev,
  130. "Error: Timeout waiting for FPGA to clear (status=%08x)!\n",
  131. status);
  132. kfree(buffer);
  133. goto out;
  134. }
  135. dev_info(&spi->dev, "Configuring the FPGA...\n");
  136. spi_write(spi, buffer, fw->size + 8);
  137. txbuf[0] = FPGA_CMD_WRITE_DIS;
  138. spi_write(spi, txbuf, 4);
  139. txbuf[0] = FPGA_CMD_READ_STATUS;
  140. spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
  141. status = get_unaligned_be32(&rxbuf[4]);
  142. dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
  143. /* Check result */
  144. if (status & FPGA_STATUS_DONE)
  145. dev_info(&spi->dev, "FPGA successfully configured!\n");
  146. else
  147. dev_info(&spi->dev, "FPGA not configured (DONE not set)\n");
  148. /*
  149. * Don't forget to release the firmware again
  150. */
  151. release_firmware(fw);
  152. kfree(buffer);
  153. out:
  154. complete(&data->fw_loaded);
  155. }
  156. static int lattice_ecp3_probe(struct spi_device *spi)
  157. {
  158. struct fpga_data *data;
  159. int err;
  160. data = devm_kzalloc(&spi->dev, sizeof(*data), GFP_KERNEL);
  161. if (!data) {
  162. dev_err(&spi->dev, "Memory allocation for fpga_data failed\n");
  163. return -ENOMEM;
  164. }
  165. spi_set_drvdata(spi, data);
  166. init_completion(&data->fw_loaded);
  167. err = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  168. FIRMWARE_NAME, &spi->dev,
  169. GFP_KERNEL, spi, firmware_load);
  170. if (err) {
  171. dev_err(&spi->dev, "Firmware loading failed with %d!\n", err);
  172. return err;
  173. }
  174. dev_info(&spi->dev, "FPGA bitstream configuration driver registered\n");
  175. return 0;
  176. }
  177. static int lattice_ecp3_remove(struct spi_device *spi)
  178. {
  179. struct fpga_data *data = spi_get_drvdata(spi);
  180. wait_for_completion(&data->fw_loaded);
  181. return 0;
  182. }
  183. static const struct spi_device_id lattice_ecp3_id[] = {
  184. { "ecp3-17", 0 },
  185. { "ecp3-35", 0 },
  186. { }
  187. };
  188. MODULE_DEVICE_TABLE(spi, lattice_ecp3_id);
  189. static struct spi_driver lattice_ecp3_driver = {
  190. .driver = {
  191. .name = "lattice-ecp3",
  192. },
  193. .probe = lattice_ecp3_probe,
  194. .remove = lattice_ecp3_remove,
  195. .id_table = lattice_ecp3_id,
  196. };
  197. module_spi_driver(lattice_ecp3_driver);
  198. MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
  199. MODULE_DESCRIPTION("Lattice ECP3 FPGA configuration via SPI");
  200. MODULE_LICENSE("GPL");
  201. MODULE_FIRMWARE(FIRMWARE_NAME);