lowlevel.h 3.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * IBM ASM Service Processor Device Driver
  4. *
  5. * Copyright (C) IBM Corporation, 2004
  6. *
  7. * Author: Max Asböck <amax@us.ibm.com>
  8. */
  9. /* Condor service processor specific hardware definitions */
  10. #ifndef __IBMASM_CONDOR_H__
  11. #define __IBMASM_CONDOR_H__
  12. #include <asm/io.h>
  13. #define VENDORID_IBM 0x1014
  14. #define DEVICEID_RSA 0x010F
  15. #define GET_MFA_ADDR(x) (x & 0xFFFFFF00)
  16. #define MAILBOX_FULL(x) (x & 0x00000001)
  17. #define NO_MFAS_AVAILABLE 0xFFFFFFFF
  18. #define INBOUND_QUEUE_PORT 0x40 /* contains address of next free MFA */
  19. #define OUTBOUND_QUEUE_PORT 0x44 /* contains address of posted MFA */
  20. #define SP_INTR_MASK 0x00000008
  21. #define UART_INTR_MASK 0x00000010
  22. #define INTR_STATUS_REGISTER 0x13A0
  23. #define INTR_CONTROL_REGISTER 0x13A4
  24. #define SCOUT_COM_A_BASE 0x0000
  25. #define SCOUT_COM_B_BASE 0x0100
  26. #define SCOUT_COM_C_BASE 0x0200
  27. #define SCOUT_COM_D_BASE 0x0300
  28. static inline int sp_interrupt_pending(void __iomem *base_address)
  29. {
  30. return SP_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER);
  31. }
  32. static inline int uart_interrupt_pending(void __iomem *base_address)
  33. {
  34. return UART_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER);
  35. }
  36. static inline void ibmasm_enable_interrupts(void __iomem *base_address, int mask)
  37. {
  38. void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;
  39. writel( readl(ctrl_reg) & ~mask, ctrl_reg);
  40. }
  41. static inline void ibmasm_disable_interrupts(void __iomem *base_address, int mask)
  42. {
  43. void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;
  44. writel( readl(ctrl_reg) | mask, ctrl_reg);
  45. }
  46. static inline void enable_sp_interrupts(void __iomem *base_address)
  47. {
  48. ibmasm_enable_interrupts(base_address, SP_INTR_MASK);
  49. }
  50. static inline void disable_sp_interrupts(void __iomem *base_address)
  51. {
  52. ibmasm_disable_interrupts(base_address, SP_INTR_MASK);
  53. }
  54. static inline void enable_uart_interrupts(void __iomem *base_address)
  55. {
  56. ibmasm_enable_interrupts(base_address, UART_INTR_MASK);
  57. }
  58. static inline void disable_uart_interrupts(void __iomem *base_address)
  59. {
  60. ibmasm_disable_interrupts(base_address, UART_INTR_MASK);
  61. }
  62. #define valid_mfa(mfa) ( (mfa) != NO_MFAS_AVAILABLE )
  63. static inline u32 get_mfa_outbound(void __iomem *base_address)
  64. {
  65. int retry;
  66. u32 mfa;
  67. for (retry=0; retry<=10; retry++) {
  68. mfa = readl(base_address + OUTBOUND_QUEUE_PORT);
  69. if (valid_mfa(mfa))
  70. break;
  71. }
  72. return mfa;
  73. }
  74. static inline void set_mfa_outbound(void __iomem *base_address, u32 mfa)
  75. {
  76. writel(mfa, base_address + OUTBOUND_QUEUE_PORT);
  77. }
  78. static inline u32 get_mfa_inbound(void __iomem *base_address)
  79. {
  80. u32 mfa = readl(base_address + INBOUND_QUEUE_PORT);
  81. if (MAILBOX_FULL(mfa))
  82. return 0;
  83. return mfa;
  84. }
  85. static inline void set_mfa_inbound(void __iomem *base_address, u32 mfa)
  86. {
  87. writel(mfa, base_address + INBOUND_QUEUE_PORT);
  88. }
  89. static inline struct i2o_message *get_i2o_message(void __iomem *base_address, u32 mfa)
  90. {
  91. return (struct i2o_message *)(GET_MFA_ADDR(mfa) + base_address);
  92. }
  93. #endif /* __IBMASM_CONDOR_H__ */