hpilo.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * linux/drivers/char/hpilo.h
  4. *
  5. * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
  6. * David Altobelli <david.altobelli@hp.com>
  7. */
  8. #ifndef __HPILO_H
  9. #define __HPILO_H
  10. #define ILO_NAME "hpilo"
  11. /* max number of open channel control blocks per device, hw limited to 32 */
  12. #define MAX_CCB 24
  13. /* min number of open channel control blocks per device, hw limited to 32 */
  14. #define MIN_CCB 8
  15. /* max number of supported devices */
  16. #define MAX_ILO_DEV 1
  17. /* max number of files */
  18. #define MAX_OPEN (MAX_CCB * MAX_ILO_DEV)
  19. /* total wait time in usec */
  20. #define MAX_WAIT_TIME 10000
  21. /* per spin wait time in usec */
  22. #define WAIT_TIME 10
  23. /* spin counter for open/close delay */
  24. #define MAX_WAIT (MAX_WAIT_TIME / WAIT_TIME)
  25. /*
  26. * Per device, used to track global memory allocations.
  27. */
  28. struct ilo_hwinfo {
  29. /* mmio registers on device */
  30. char __iomem *mmio_vaddr;
  31. /* doorbell registers on device */
  32. char __iomem *db_vaddr;
  33. /* shared memory on device used for channel control blocks */
  34. char __iomem *ram_vaddr;
  35. /* files corresponding to this device */
  36. struct ccb_data *ccb_alloc[MAX_CCB];
  37. struct pci_dev *ilo_dev;
  38. /*
  39. * open_lock serializes ccb_cnt during open and close
  40. * [ irq disabled ]
  41. * -> alloc_lock used when adding/removing/searching ccb_alloc,
  42. * which represents all ccbs open on the device
  43. * --> fifo_lock controls access to fifo queues shared with hw
  44. *
  45. * Locks must be taken in this order, but open_lock and alloc_lock
  46. * are optional, they do not need to be held in order to take a
  47. * lower level lock.
  48. */
  49. spinlock_t open_lock;
  50. spinlock_t alloc_lock;
  51. spinlock_t fifo_lock;
  52. struct cdev cdev;
  53. };
  54. /* offset from mmio_vaddr for enabling doorbell interrupts */
  55. #define DB_IRQ 0xB2
  56. /* offset from mmio_vaddr for outbound communications */
  57. #define DB_OUT 0xD4
  58. /* DB_OUT reset bit */
  59. #define DB_RESET 26
  60. /*
  61. * Channel control block. Used to manage hardware queues.
  62. * The format must match hw's version. The hw ccb is 128 bytes,
  63. * but the context area shouldn't be touched by the driver.
  64. */
  65. #define ILOSW_CCB_SZ 64
  66. #define ILOHW_CCB_SZ 128
  67. struct ccb {
  68. union {
  69. char *send_fifobar;
  70. u64 send_fifobar_pa;
  71. } ccb_u1;
  72. union {
  73. char *send_desc;
  74. u64 send_desc_pa;
  75. } ccb_u2;
  76. u64 send_ctrl;
  77. union {
  78. char *recv_fifobar;
  79. u64 recv_fifobar_pa;
  80. } ccb_u3;
  81. union {
  82. char *recv_desc;
  83. u64 recv_desc_pa;
  84. } ccb_u4;
  85. u64 recv_ctrl;
  86. union {
  87. char __iomem *db_base;
  88. u64 padding5;
  89. } ccb_u5;
  90. u64 channel;
  91. /* unused context area (64 bytes) */
  92. };
  93. /* ccb queue parameters */
  94. #define SENDQ 1
  95. #define RECVQ 2
  96. #define NR_QENTRY 4
  97. #define L2_QENTRY_SZ 12
  98. /* ccb ctrl bitfields */
  99. #define CTRL_BITPOS_L2SZ 0
  100. #define CTRL_BITPOS_FIFOINDEXMASK 4
  101. #define CTRL_BITPOS_DESCLIMIT 18
  102. #define CTRL_BITPOS_A 30
  103. #define CTRL_BITPOS_G 31
  104. /* ccb doorbell macros */
  105. #define L2_DB_SIZE 14
  106. #define ONE_DB_SIZE (1 << L2_DB_SIZE)
  107. /*
  108. * Per fd structure used to track the ccb allocated to that dev file.
  109. */
  110. struct ccb_data {
  111. /* software version of ccb, using virtual addrs */
  112. struct ccb driver_ccb;
  113. /* hardware version of ccb, using physical addrs */
  114. struct ccb ilo_ccb;
  115. /* hardware ccb is written to this shared mapped device memory */
  116. struct ccb __iomem *mapped_ccb;
  117. /* dma'able memory used for send/recv queues */
  118. void *dma_va;
  119. dma_addr_t dma_pa;
  120. size_t dma_size;
  121. /* pointer to hardware device info */
  122. struct ilo_hwinfo *ilo_hw;
  123. /* queue for this ccb to wait for recv data */
  124. wait_queue_head_t ccb_waitq;
  125. /* usage count, to allow for shared ccb's */
  126. int ccb_cnt;
  127. /* open wanted exclusive access to this ccb */
  128. int ccb_excl;
  129. };
  130. /*
  131. * FIFO queue structure, shared with hw.
  132. */
  133. #define ILO_START_ALIGN 4096
  134. #define ILO_CACHE_SZ 128
  135. struct fifo {
  136. u64 nrents; /* user requested number of fifo entries */
  137. u64 imask; /* mask to extract valid fifo index */
  138. u64 merge; /* O/C bits to merge in during enqueue operation */
  139. u64 reset; /* set to non-zero when the target device resets */
  140. u8 pad_0[ILO_CACHE_SZ - (sizeof(u64) * 4)];
  141. u64 head;
  142. u8 pad_1[ILO_CACHE_SZ - (sizeof(u64))];
  143. u64 tail;
  144. u8 pad_2[ILO_CACHE_SZ - (sizeof(u64))];
  145. u64 fifobar[];
  146. };
  147. /* convert between struct fifo, and the fifobar, which is saved in the ccb */
  148. #define FIFOHANDLESIZE (sizeof(struct fifo))
  149. #define FIFOBARTOHANDLE(_fifo) \
  150. ((struct fifo *)(((char *)(_fifo)) - FIFOHANDLESIZE))
  151. /* the number of qwords to consume from the entry descriptor */
  152. #define ENTRY_BITPOS_QWORDS 0
  153. /* descriptor index number (within a specified queue) */
  154. #define ENTRY_BITPOS_DESCRIPTOR 10
  155. /* state bit, fifo entry consumed by consumer */
  156. #define ENTRY_BITPOS_C 22
  157. /* state bit, fifo entry is occupied */
  158. #define ENTRY_BITPOS_O 23
  159. #define ENTRY_BITS_QWORDS 10
  160. #define ENTRY_BITS_DESCRIPTOR 12
  161. #define ENTRY_BITS_C 1
  162. #define ENTRY_BITS_O 1
  163. #define ENTRY_BITS_TOTAL \
  164. (ENTRY_BITS_C + ENTRY_BITS_O + \
  165. ENTRY_BITS_QWORDS + ENTRY_BITS_DESCRIPTOR)
  166. /* extract various entry fields */
  167. #define ENTRY_MASK ((1 << ENTRY_BITS_TOTAL) - 1)
  168. #define ENTRY_MASK_C (((1 << ENTRY_BITS_C) - 1) << ENTRY_BITPOS_C)
  169. #define ENTRY_MASK_O (((1 << ENTRY_BITS_O) - 1) << ENTRY_BITPOS_O)
  170. #define ENTRY_MASK_QWORDS \
  171. (((1 << ENTRY_BITS_QWORDS) - 1) << ENTRY_BITPOS_QWORDS)
  172. #define ENTRY_MASK_DESCRIPTOR \
  173. (((1 << ENTRY_BITS_DESCRIPTOR) - 1) << ENTRY_BITPOS_DESCRIPTOR)
  174. #define ENTRY_MASK_NOSTATE (ENTRY_MASK >> (ENTRY_BITS_C + ENTRY_BITS_O))
  175. #endif /* __HPILO_H */