eeprom_93xx46.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for 93xx46 EEPROMs
  4. *
  5. * (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/device.h>
  9. #include <linux/gpio/consumer.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/mutex.h>
  13. #include <linux/of.h>
  14. #include <linux/of_device.h>
  15. #include <linux/of_gpio.h>
  16. #include <linux/slab.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/nvmem-provider.h>
  19. #include <linux/eeprom_93xx46.h>
  20. #define OP_START 0x4
  21. #define OP_WRITE (OP_START | 0x1)
  22. #define OP_READ (OP_START | 0x2)
  23. #define ADDR_EWDS 0x00
  24. #define ADDR_ERAL 0x20
  25. #define ADDR_EWEN 0x30
  26. struct eeprom_93xx46_devtype_data {
  27. unsigned int quirks;
  28. };
  29. static const struct eeprom_93xx46_devtype_data atmel_at93c46d_data = {
  30. .quirks = EEPROM_93XX46_QUIRK_SINGLE_WORD_READ |
  31. EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH,
  32. };
  33. static const struct eeprom_93xx46_devtype_data microchip_93lc46b_data = {
  34. .quirks = EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE,
  35. };
  36. struct eeprom_93xx46_dev {
  37. struct spi_device *spi;
  38. struct eeprom_93xx46_platform_data *pdata;
  39. struct mutex lock;
  40. struct nvmem_config nvmem_config;
  41. struct nvmem_device *nvmem;
  42. int addrlen;
  43. int size;
  44. };
  45. static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev)
  46. {
  47. return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ;
  48. }
  49. static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev)
  50. {
  51. return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH;
  52. }
  53. static inline bool has_quirk_extra_read_cycle(struct eeprom_93xx46_dev *edev)
  54. {
  55. return edev->pdata->quirks & EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE;
  56. }
  57. static int eeprom_93xx46_read(void *priv, unsigned int off,
  58. void *val, size_t count)
  59. {
  60. struct eeprom_93xx46_dev *edev = priv;
  61. char *buf = val;
  62. int err = 0;
  63. if (unlikely(off >= edev->size))
  64. return 0;
  65. if ((off + count) > edev->size)
  66. count = edev->size - off;
  67. if (unlikely(!count))
  68. return count;
  69. mutex_lock(&edev->lock);
  70. if (edev->pdata->prepare)
  71. edev->pdata->prepare(edev);
  72. while (count) {
  73. struct spi_message m;
  74. struct spi_transfer t[2] = { { 0 } };
  75. u16 cmd_addr = OP_READ << edev->addrlen;
  76. size_t nbytes = count;
  77. int bits;
  78. if (edev->addrlen == 7) {
  79. cmd_addr |= off & 0x7f;
  80. bits = 10;
  81. if (has_quirk_single_word_read(edev))
  82. nbytes = 1;
  83. } else {
  84. cmd_addr |= (off >> 1) & 0x3f;
  85. bits = 9;
  86. if (has_quirk_single_word_read(edev))
  87. nbytes = 2;
  88. }
  89. dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n",
  90. cmd_addr, edev->spi->max_speed_hz);
  91. if (has_quirk_extra_read_cycle(edev)) {
  92. cmd_addr <<= 1;
  93. bits += 1;
  94. }
  95. spi_message_init(&m);
  96. t[0].tx_buf = (char *)&cmd_addr;
  97. t[0].len = 2;
  98. t[0].bits_per_word = bits;
  99. spi_message_add_tail(&t[0], &m);
  100. t[1].rx_buf = buf;
  101. t[1].len = count;
  102. t[1].bits_per_word = 8;
  103. spi_message_add_tail(&t[1], &m);
  104. err = spi_sync(edev->spi, &m);
  105. /* have to wait at least Tcsl ns */
  106. ndelay(250);
  107. if (err) {
  108. dev_err(&edev->spi->dev, "read %zu bytes at %d: err. %d\n",
  109. nbytes, (int)off, err);
  110. break;
  111. }
  112. buf += nbytes;
  113. off += nbytes;
  114. count -= nbytes;
  115. }
  116. if (edev->pdata->finish)
  117. edev->pdata->finish(edev);
  118. mutex_unlock(&edev->lock);
  119. return err;
  120. }
  121. static int eeprom_93xx46_ew(struct eeprom_93xx46_dev *edev, int is_on)
  122. {
  123. struct spi_message m;
  124. struct spi_transfer t;
  125. int bits, ret;
  126. u16 cmd_addr;
  127. cmd_addr = OP_START << edev->addrlen;
  128. if (edev->addrlen == 7) {
  129. cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS) << 1;
  130. bits = 10;
  131. } else {
  132. cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS);
  133. bits = 9;
  134. }
  135. if (has_quirk_instruction_length(edev)) {
  136. cmd_addr <<= 2;
  137. bits += 2;
  138. }
  139. dev_dbg(&edev->spi->dev, "ew%s cmd 0x%04x, %d bits\n",
  140. is_on ? "en" : "ds", cmd_addr, bits);
  141. spi_message_init(&m);
  142. memset(&t, 0, sizeof(t));
  143. t.tx_buf = &cmd_addr;
  144. t.len = 2;
  145. t.bits_per_word = bits;
  146. spi_message_add_tail(&t, &m);
  147. mutex_lock(&edev->lock);
  148. if (edev->pdata->prepare)
  149. edev->pdata->prepare(edev);
  150. ret = spi_sync(edev->spi, &m);
  151. /* have to wait at least Tcsl ns */
  152. ndelay(250);
  153. if (ret)
  154. dev_err(&edev->spi->dev, "erase/write %sable error %d\n",
  155. is_on ? "en" : "dis", ret);
  156. if (edev->pdata->finish)
  157. edev->pdata->finish(edev);
  158. mutex_unlock(&edev->lock);
  159. return ret;
  160. }
  161. static ssize_t
  162. eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev,
  163. const char *buf, unsigned off)
  164. {
  165. struct spi_message m;
  166. struct spi_transfer t[2];
  167. int bits, data_len, ret;
  168. u16 cmd_addr;
  169. cmd_addr = OP_WRITE << edev->addrlen;
  170. if (edev->addrlen == 7) {
  171. cmd_addr |= off & 0x7f;
  172. bits = 10;
  173. data_len = 1;
  174. } else {
  175. cmd_addr |= (off >> 1) & 0x3f;
  176. bits = 9;
  177. data_len = 2;
  178. }
  179. dev_dbg(&edev->spi->dev, "write cmd 0x%x\n", cmd_addr);
  180. spi_message_init(&m);
  181. memset(t, 0, sizeof(t));
  182. t[0].tx_buf = (char *)&cmd_addr;
  183. t[0].len = 2;
  184. t[0].bits_per_word = bits;
  185. spi_message_add_tail(&t[0], &m);
  186. t[1].tx_buf = buf;
  187. t[1].len = data_len;
  188. t[1].bits_per_word = 8;
  189. spi_message_add_tail(&t[1], &m);
  190. ret = spi_sync(edev->spi, &m);
  191. /* have to wait program cycle time Twc ms */
  192. mdelay(6);
  193. return ret;
  194. }
  195. static int eeprom_93xx46_write(void *priv, unsigned int off,
  196. void *val, size_t count)
  197. {
  198. struct eeprom_93xx46_dev *edev = priv;
  199. char *buf = val;
  200. int i, ret, step = 1;
  201. if (unlikely(off >= edev->size))
  202. return -EFBIG;
  203. if ((off + count) > edev->size)
  204. count = edev->size - off;
  205. if (unlikely(!count))
  206. return count;
  207. /* only write even number of bytes on 16-bit devices */
  208. if (edev->addrlen == 6) {
  209. step = 2;
  210. count &= ~1;
  211. }
  212. /* erase/write enable */
  213. ret = eeprom_93xx46_ew(edev, 1);
  214. if (ret)
  215. return ret;
  216. mutex_lock(&edev->lock);
  217. if (edev->pdata->prepare)
  218. edev->pdata->prepare(edev);
  219. for (i = 0; i < count; i += step) {
  220. ret = eeprom_93xx46_write_word(edev, &buf[i], off + i);
  221. if (ret) {
  222. dev_err(&edev->spi->dev, "write failed at %d: %d\n",
  223. (int)off + i, ret);
  224. break;
  225. }
  226. }
  227. if (edev->pdata->finish)
  228. edev->pdata->finish(edev);
  229. mutex_unlock(&edev->lock);
  230. /* erase/write disable */
  231. eeprom_93xx46_ew(edev, 0);
  232. return ret;
  233. }
  234. static int eeprom_93xx46_eral(struct eeprom_93xx46_dev *edev)
  235. {
  236. struct eeprom_93xx46_platform_data *pd = edev->pdata;
  237. struct spi_message m;
  238. struct spi_transfer t;
  239. int bits, ret;
  240. u16 cmd_addr;
  241. cmd_addr = OP_START << edev->addrlen;
  242. if (edev->addrlen == 7) {
  243. cmd_addr |= ADDR_ERAL << 1;
  244. bits = 10;
  245. } else {
  246. cmd_addr |= ADDR_ERAL;
  247. bits = 9;
  248. }
  249. if (has_quirk_instruction_length(edev)) {
  250. cmd_addr <<= 2;
  251. bits += 2;
  252. }
  253. dev_dbg(&edev->spi->dev, "eral cmd 0x%04x, %d bits\n", cmd_addr, bits);
  254. spi_message_init(&m);
  255. memset(&t, 0, sizeof(t));
  256. t.tx_buf = &cmd_addr;
  257. t.len = 2;
  258. t.bits_per_word = bits;
  259. spi_message_add_tail(&t, &m);
  260. mutex_lock(&edev->lock);
  261. if (edev->pdata->prepare)
  262. edev->pdata->prepare(edev);
  263. ret = spi_sync(edev->spi, &m);
  264. if (ret)
  265. dev_err(&edev->spi->dev, "erase error %d\n", ret);
  266. /* have to wait erase cycle time Tec ms */
  267. mdelay(6);
  268. if (pd->finish)
  269. pd->finish(edev);
  270. mutex_unlock(&edev->lock);
  271. return ret;
  272. }
  273. static ssize_t eeprom_93xx46_store_erase(struct device *dev,
  274. struct device_attribute *attr,
  275. const char *buf, size_t count)
  276. {
  277. struct eeprom_93xx46_dev *edev = dev_get_drvdata(dev);
  278. int erase = 0, ret;
  279. sscanf(buf, "%d", &erase);
  280. if (erase) {
  281. ret = eeprom_93xx46_ew(edev, 1);
  282. if (ret)
  283. return ret;
  284. ret = eeprom_93xx46_eral(edev);
  285. if (ret)
  286. return ret;
  287. ret = eeprom_93xx46_ew(edev, 0);
  288. if (ret)
  289. return ret;
  290. }
  291. return count;
  292. }
  293. static DEVICE_ATTR(erase, S_IWUSR, NULL, eeprom_93xx46_store_erase);
  294. static void select_assert(void *context)
  295. {
  296. struct eeprom_93xx46_dev *edev = context;
  297. gpiod_set_value_cansleep(edev->pdata->select, 1);
  298. }
  299. static void select_deassert(void *context)
  300. {
  301. struct eeprom_93xx46_dev *edev = context;
  302. gpiod_set_value_cansleep(edev->pdata->select, 0);
  303. }
  304. static const struct of_device_id eeprom_93xx46_of_table[] = {
  305. { .compatible = "eeprom-93xx46", },
  306. { .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, },
  307. { .compatible = "microchip,93lc46b", .data = &microchip_93lc46b_data, },
  308. {}
  309. };
  310. MODULE_DEVICE_TABLE(of, eeprom_93xx46_of_table);
  311. static int eeprom_93xx46_probe_dt(struct spi_device *spi)
  312. {
  313. const struct of_device_id *of_id =
  314. of_match_device(eeprom_93xx46_of_table, &spi->dev);
  315. struct device_node *np = spi->dev.of_node;
  316. struct eeprom_93xx46_platform_data *pd;
  317. u32 tmp;
  318. int ret;
  319. pd = devm_kzalloc(&spi->dev, sizeof(*pd), GFP_KERNEL);
  320. if (!pd)
  321. return -ENOMEM;
  322. ret = of_property_read_u32(np, "data-size", &tmp);
  323. if (ret < 0) {
  324. dev_err(&spi->dev, "data-size property not found\n");
  325. return ret;
  326. }
  327. if (tmp == 8) {
  328. pd->flags |= EE_ADDR8;
  329. } else if (tmp == 16) {
  330. pd->flags |= EE_ADDR16;
  331. } else {
  332. dev_err(&spi->dev, "invalid data-size (%d)\n", tmp);
  333. return -EINVAL;
  334. }
  335. if (of_property_read_bool(np, "read-only"))
  336. pd->flags |= EE_READONLY;
  337. pd->select = devm_gpiod_get_optional(&spi->dev, "select",
  338. GPIOD_OUT_LOW);
  339. if (IS_ERR(pd->select))
  340. return PTR_ERR(pd->select);
  341. pd->prepare = select_assert;
  342. pd->finish = select_deassert;
  343. gpiod_direction_output(pd->select, 0);
  344. if (of_id->data) {
  345. const struct eeprom_93xx46_devtype_data *data = of_id->data;
  346. pd->quirks = data->quirks;
  347. }
  348. spi->dev.platform_data = pd;
  349. return 0;
  350. }
  351. static int eeprom_93xx46_probe(struct spi_device *spi)
  352. {
  353. struct eeprom_93xx46_platform_data *pd;
  354. struct eeprom_93xx46_dev *edev;
  355. int err;
  356. if (spi->dev.of_node) {
  357. err = eeprom_93xx46_probe_dt(spi);
  358. if (err < 0)
  359. return err;
  360. }
  361. pd = spi->dev.platform_data;
  362. if (!pd) {
  363. dev_err(&spi->dev, "missing platform data\n");
  364. return -ENODEV;
  365. }
  366. edev = devm_kzalloc(&spi->dev, sizeof(*edev), GFP_KERNEL);
  367. if (!edev)
  368. return -ENOMEM;
  369. if (pd->flags & EE_ADDR8)
  370. edev->addrlen = 7;
  371. else if (pd->flags & EE_ADDR16)
  372. edev->addrlen = 6;
  373. else {
  374. dev_err(&spi->dev, "unspecified address type\n");
  375. return -EINVAL;
  376. }
  377. mutex_init(&edev->lock);
  378. edev->spi = spi;
  379. edev->pdata = pd;
  380. edev->size = 128;
  381. edev->nvmem_config.type = NVMEM_TYPE_EEPROM;
  382. edev->nvmem_config.name = dev_name(&spi->dev);
  383. edev->nvmem_config.dev = &spi->dev;
  384. edev->nvmem_config.read_only = pd->flags & EE_READONLY;
  385. edev->nvmem_config.root_only = true;
  386. edev->nvmem_config.owner = THIS_MODULE;
  387. edev->nvmem_config.compat = true;
  388. edev->nvmem_config.base_dev = &spi->dev;
  389. edev->nvmem_config.reg_read = eeprom_93xx46_read;
  390. edev->nvmem_config.reg_write = eeprom_93xx46_write;
  391. edev->nvmem_config.priv = edev;
  392. edev->nvmem_config.stride = 4;
  393. edev->nvmem_config.word_size = 1;
  394. edev->nvmem_config.size = edev->size;
  395. edev->nvmem = devm_nvmem_register(&spi->dev, &edev->nvmem_config);
  396. if (IS_ERR(edev->nvmem))
  397. return PTR_ERR(edev->nvmem);
  398. dev_info(&spi->dev, "%d-bit eeprom %s\n",
  399. (pd->flags & EE_ADDR8) ? 8 : 16,
  400. (pd->flags & EE_READONLY) ? "(readonly)" : "");
  401. if (!(pd->flags & EE_READONLY)) {
  402. if (device_create_file(&spi->dev, &dev_attr_erase))
  403. dev_err(&spi->dev, "can't create erase interface\n");
  404. }
  405. spi_set_drvdata(spi, edev);
  406. return 0;
  407. }
  408. static int eeprom_93xx46_remove(struct spi_device *spi)
  409. {
  410. struct eeprom_93xx46_dev *edev = spi_get_drvdata(spi);
  411. if (!(edev->pdata->flags & EE_READONLY))
  412. device_remove_file(&spi->dev, &dev_attr_erase);
  413. return 0;
  414. }
  415. static struct spi_driver eeprom_93xx46_driver = {
  416. .driver = {
  417. .name = "93xx46",
  418. .of_match_table = of_match_ptr(eeprom_93xx46_of_table),
  419. },
  420. .probe = eeprom_93xx46_probe,
  421. .remove = eeprom_93xx46_remove,
  422. };
  423. module_spi_driver(eeprom_93xx46_driver);
  424. MODULE_LICENSE("GPL");
  425. MODULE_DESCRIPTION("Driver for 93xx46 EEPROMs");
  426. MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
  427. MODULE_ALIAS("spi:93xx46");
  428. MODULE_ALIAS("spi:eeprom-93xx46");