at25.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
  4. *
  5. * Copyright (C) 2006 David Brownell
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/slab.h>
  10. #include <linux/delay.h>
  11. #include <linux/device.h>
  12. #include <linux/sched.h>
  13. #include <linux/nvmem-provider.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/spi/eeprom.h>
  16. #include <linux/property.h>
  17. /*
  18. * NOTE: this is an *EEPROM* driver. The vagaries of product naming
  19. * mean that some AT25 products are EEPROMs, and others are FLASH.
  20. * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
  21. * not this one!
  22. */
  23. struct at25_data {
  24. struct spi_device *spi;
  25. struct mutex lock;
  26. struct spi_eeprom chip;
  27. unsigned addrlen;
  28. struct nvmem_config nvmem_config;
  29. struct nvmem_device *nvmem;
  30. };
  31. #define AT25_WREN 0x06 /* latch the write enable */
  32. #define AT25_WRDI 0x04 /* reset the write enable */
  33. #define AT25_RDSR 0x05 /* read status register */
  34. #define AT25_WRSR 0x01 /* write status register */
  35. #define AT25_READ 0x03 /* read byte(s) */
  36. #define AT25_WRITE 0x02 /* write byte(s)/sector */
  37. #define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
  38. #define AT25_SR_WEN 0x02 /* write enable (latched) */
  39. #define AT25_SR_BP0 0x04 /* BP for software writeprotect */
  40. #define AT25_SR_BP1 0x08
  41. #define AT25_SR_WPEN 0x80 /* writeprotect enable */
  42. #define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */
  43. #define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
  44. /* Specs often allow 5 msec for a page write, sometimes 20 msec;
  45. * it's important to recover from write timeouts.
  46. */
  47. #define EE_TIMEOUT 25
  48. /*-------------------------------------------------------------------------*/
  49. #define io_limit PAGE_SIZE /* bytes */
  50. static int at25_ee_read(void *priv, unsigned int offset,
  51. void *val, size_t count)
  52. {
  53. struct at25_data *at25 = priv;
  54. char *buf = val;
  55. u8 command[EE_MAXADDRLEN + 1];
  56. u8 *cp;
  57. ssize_t status;
  58. struct spi_transfer t[2];
  59. struct spi_message m;
  60. u8 instr;
  61. if (unlikely(offset >= at25->chip.byte_len))
  62. return -EINVAL;
  63. if ((offset + count) > at25->chip.byte_len)
  64. count = at25->chip.byte_len - offset;
  65. if (unlikely(!count))
  66. return -EINVAL;
  67. cp = command;
  68. instr = AT25_READ;
  69. if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
  70. if (offset >= (1U << (at25->addrlen * 8)))
  71. instr |= AT25_INSTR_BIT3;
  72. *cp++ = instr;
  73. /* 8/16/24-bit address is written MSB first */
  74. switch (at25->addrlen) {
  75. default: /* case 3 */
  76. *cp++ = offset >> 16;
  77. fallthrough;
  78. case 2:
  79. *cp++ = offset >> 8;
  80. fallthrough;
  81. case 1:
  82. case 0: /* can't happen: for better codegen */
  83. *cp++ = offset >> 0;
  84. }
  85. spi_message_init(&m);
  86. memset(t, 0, sizeof(t));
  87. t[0].tx_buf = command;
  88. t[0].len = at25->addrlen + 1;
  89. spi_message_add_tail(&t[0], &m);
  90. t[1].rx_buf = buf;
  91. t[1].len = count;
  92. spi_message_add_tail(&t[1], &m);
  93. mutex_lock(&at25->lock);
  94. /* Read it all at once.
  95. *
  96. * REVISIT that's potentially a problem with large chips, if
  97. * other devices on the bus need to be accessed regularly or
  98. * this chip is clocked very slowly
  99. */
  100. status = spi_sync(at25->spi, &m);
  101. dev_dbg(&at25->spi->dev, "read %zu bytes at %d --> %zd\n",
  102. count, offset, status);
  103. mutex_unlock(&at25->lock);
  104. return status;
  105. }
  106. static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
  107. {
  108. struct at25_data *at25 = priv;
  109. const char *buf = val;
  110. int status = 0;
  111. unsigned buf_size;
  112. u8 *bounce;
  113. if (unlikely(off >= at25->chip.byte_len))
  114. return -EFBIG;
  115. if ((off + count) > at25->chip.byte_len)
  116. count = at25->chip.byte_len - off;
  117. if (unlikely(!count))
  118. return -EINVAL;
  119. /* Temp buffer starts with command and address */
  120. buf_size = at25->chip.page_size;
  121. if (buf_size > io_limit)
  122. buf_size = io_limit;
  123. bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
  124. if (!bounce)
  125. return -ENOMEM;
  126. /* For write, rollover is within the page ... so we write at
  127. * most one page, then manually roll over to the next page.
  128. */
  129. mutex_lock(&at25->lock);
  130. do {
  131. unsigned long timeout, retries;
  132. unsigned segment;
  133. unsigned offset = (unsigned) off;
  134. u8 *cp = bounce;
  135. int sr;
  136. u8 instr;
  137. *cp = AT25_WREN;
  138. status = spi_write(at25->spi, cp, 1);
  139. if (status < 0) {
  140. dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
  141. break;
  142. }
  143. instr = AT25_WRITE;
  144. if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
  145. if (offset >= (1U << (at25->addrlen * 8)))
  146. instr |= AT25_INSTR_BIT3;
  147. *cp++ = instr;
  148. /* 8/16/24-bit address is written MSB first */
  149. switch (at25->addrlen) {
  150. default: /* case 3 */
  151. *cp++ = offset >> 16;
  152. fallthrough;
  153. case 2:
  154. *cp++ = offset >> 8;
  155. fallthrough;
  156. case 1:
  157. case 0: /* can't happen: for better codegen */
  158. *cp++ = offset >> 0;
  159. }
  160. /* Write as much of a page as we can */
  161. segment = buf_size - (offset % buf_size);
  162. if (segment > count)
  163. segment = count;
  164. memcpy(cp, buf, segment);
  165. status = spi_write(at25->spi, bounce,
  166. segment + at25->addrlen + 1);
  167. dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
  168. segment, offset, status);
  169. if (status < 0)
  170. break;
  171. /* REVISIT this should detect (or prevent) failed writes
  172. * to readonly sections of the EEPROM...
  173. */
  174. /* Wait for non-busy status */
  175. timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
  176. retries = 0;
  177. do {
  178. sr = spi_w8r8(at25->spi, AT25_RDSR);
  179. if (sr < 0 || (sr & AT25_SR_nRDY)) {
  180. dev_dbg(&at25->spi->dev,
  181. "rdsr --> %d (%02x)\n", sr, sr);
  182. /* at HZ=100, this is sloooow */
  183. msleep(1);
  184. continue;
  185. }
  186. if (!(sr & AT25_SR_nRDY))
  187. break;
  188. } while (retries++ < 3 || time_before_eq(jiffies, timeout));
  189. if ((sr < 0) || (sr & AT25_SR_nRDY)) {
  190. dev_err(&at25->spi->dev,
  191. "write %u bytes offset %u, timeout after %u msecs\n",
  192. segment, offset,
  193. jiffies_to_msecs(jiffies -
  194. (timeout - EE_TIMEOUT)));
  195. status = -ETIMEDOUT;
  196. break;
  197. }
  198. off += segment;
  199. buf += segment;
  200. count -= segment;
  201. } while (count > 0);
  202. mutex_unlock(&at25->lock);
  203. kfree(bounce);
  204. return status;
  205. }
  206. /*-------------------------------------------------------------------------*/
  207. static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
  208. {
  209. u32 val;
  210. memset(chip, 0, sizeof(*chip));
  211. strncpy(chip->name, "at25", sizeof(chip->name));
  212. if (device_property_read_u32(dev, "size", &val) == 0 ||
  213. device_property_read_u32(dev, "at25,byte-len", &val) == 0) {
  214. chip->byte_len = val;
  215. } else {
  216. dev_err(dev, "Error: missing \"size\" property\n");
  217. return -ENODEV;
  218. }
  219. if (device_property_read_u32(dev, "pagesize", &val) == 0 ||
  220. device_property_read_u32(dev, "at25,page-size", &val) == 0) {
  221. chip->page_size = val;
  222. } else {
  223. dev_err(dev, "Error: missing \"pagesize\" property\n");
  224. return -ENODEV;
  225. }
  226. if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) {
  227. chip->flags = (u16)val;
  228. } else {
  229. if (device_property_read_u32(dev, "address-width", &val)) {
  230. dev_err(dev,
  231. "Error: missing \"address-width\" property\n");
  232. return -ENODEV;
  233. }
  234. switch (val) {
  235. case 9:
  236. chip->flags |= EE_INSTR_BIT3_IS_ADDR;
  237. fallthrough;
  238. case 8:
  239. chip->flags |= EE_ADDR1;
  240. break;
  241. case 16:
  242. chip->flags |= EE_ADDR2;
  243. break;
  244. case 24:
  245. chip->flags |= EE_ADDR3;
  246. break;
  247. default:
  248. dev_err(dev,
  249. "Error: bad \"address-width\" property: %u\n",
  250. val);
  251. return -ENODEV;
  252. }
  253. if (device_property_present(dev, "read-only"))
  254. chip->flags |= EE_READONLY;
  255. }
  256. return 0;
  257. }
  258. static int at25_probe(struct spi_device *spi)
  259. {
  260. struct at25_data *at25 = NULL;
  261. struct spi_eeprom chip;
  262. int err;
  263. int sr;
  264. int addrlen;
  265. /* Chip description */
  266. if (!spi->dev.platform_data) {
  267. err = at25_fw_to_chip(&spi->dev, &chip);
  268. if (err)
  269. return err;
  270. } else
  271. chip = *(struct spi_eeprom *)spi->dev.platform_data;
  272. /* For now we only support 8/16/24 bit addressing */
  273. if (chip.flags & EE_ADDR1)
  274. addrlen = 1;
  275. else if (chip.flags & EE_ADDR2)
  276. addrlen = 2;
  277. else if (chip.flags & EE_ADDR3)
  278. addrlen = 3;
  279. else {
  280. dev_dbg(&spi->dev, "unsupported address type\n");
  281. return -EINVAL;
  282. }
  283. /* Ping the chip ... the status register is pretty portable,
  284. * unlike probing manufacturer IDs. We do expect that system
  285. * firmware didn't write it in the past few milliseconds!
  286. */
  287. sr = spi_w8r8(spi, AT25_RDSR);
  288. if (sr < 0 || sr & AT25_SR_nRDY) {
  289. dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
  290. return -ENXIO;
  291. }
  292. at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL);
  293. if (!at25)
  294. return -ENOMEM;
  295. mutex_init(&at25->lock);
  296. at25->chip = chip;
  297. at25->spi = spi;
  298. spi_set_drvdata(spi, at25);
  299. at25->addrlen = addrlen;
  300. at25->nvmem_config.type = NVMEM_TYPE_EEPROM;
  301. at25->nvmem_config.name = dev_name(&spi->dev);
  302. at25->nvmem_config.dev = &spi->dev;
  303. at25->nvmem_config.read_only = chip.flags & EE_READONLY;
  304. at25->nvmem_config.root_only = true;
  305. at25->nvmem_config.owner = THIS_MODULE;
  306. at25->nvmem_config.compat = true;
  307. at25->nvmem_config.base_dev = &spi->dev;
  308. at25->nvmem_config.reg_read = at25_ee_read;
  309. at25->nvmem_config.reg_write = at25_ee_write;
  310. at25->nvmem_config.priv = at25;
  311. at25->nvmem_config.stride = 1;
  312. at25->nvmem_config.word_size = 1;
  313. at25->nvmem_config.size = chip.byte_len;
  314. at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
  315. if (IS_ERR(at25->nvmem))
  316. return PTR_ERR(at25->nvmem);
  317. dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n",
  318. (chip.byte_len < 1024) ? chip.byte_len : (chip.byte_len / 1024),
  319. (chip.byte_len < 1024) ? "Byte" : "KByte",
  320. at25->chip.name,
  321. (chip.flags & EE_READONLY) ? " (readonly)" : "",
  322. at25->chip.page_size);
  323. return 0;
  324. }
  325. /*-------------------------------------------------------------------------*/
  326. static const struct of_device_id at25_of_match[] = {
  327. { .compatible = "atmel,at25", },
  328. { }
  329. };
  330. MODULE_DEVICE_TABLE(of, at25_of_match);
  331. static struct spi_driver at25_driver = {
  332. .driver = {
  333. .name = "at25",
  334. .of_match_table = at25_of_match,
  335. },
  336. .probe = at25_probe,
  337. };
  338. module_spi_driver(at25_driver);
  339. MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
  340. MODULE_AUTHOR("David Brownell");
  341. MODULE_LICENSE("GPL");
  342. MODULE_ALIAS("spi:at25");