dsmart_card.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. #include <linux/clk.h>
  3. #include <linux/delay.h>
  4. #include <linux/dsmart_card_interface.h>
  5. #include <asm/io.h>
  6. #include <linux/kernel.h>
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/fs.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/init.h>
  12. #include <linux/miscdevice.h>
  13. #include <linux/module.h>
  14. #include <linux/of_device.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/types.h>
  17. #include <linux/uaccess.h>
  18. #include <asm/uaccess.h>
  19. #define MAX_TRY_TIME_COUNT 100000
  20. #define MAX_INT_TIMEOUT (msecs_to_jiffies(1000))
  21. #define RX_TX_FIFO 0x00
  22. #define CONTROL 0x04
  23. #define MSTATUS_MMASK 0x08 /* Each bit of the MSTATUS register is a source of a maskable interrupt. Writing logic '1' to the corresponding bit of MMASK register,
  24. enables pending interrupt from the given source. */
  25. #define CSTATUS 0x0c
  26. #define CONFIG 0x10
  27. #define MISC 0x14
  28. #define CCLK_DIV 0x18
  29. #define ETU 0x1c
  30. #define EGT 0x20
  31. #define WT0_BGT 0x24
  32. #define WT1_CWT 0x28
  33. #define WT2 0x2c
  34. #define WT3 0x30
  35. #define ERROR_MERROR 0x34
  36. #define LENGTH 0x38
  37. /* bit definition for CONFIG */
  38. #define MIE BIT(7) /* This bit is set to HIGH to globally enable interrupts, and cleared to LOW disables interrupts */
  39. #define DMA_EN BIT(6) /* HIGH state written into this bit enables the DMA mode */
  40. #define BLOCK_ON BIT(5) /* Active HIGH bit which is responsible for block mode activation. See 9.15 LENGTH register for details */
  41. #define CLOCK_STOP BIT(4) /* The value in which card clock (cclk pin) will be stopped in the power down mode. Automatically cleared when CRD_ERR is detected or STOP asserted */
  42. #define C BIT(3) /* These bits work as GPIO for pins c5v3 and c18. Used for class setting */
  43. #define AB BIT(2) /* These bits work as GPIO for pins c5v3 and c18. Used for class setting */
  44. #define TMOD BIT(1) /* HIGH state of this bit indicates that the T=1 protocol is used, else T=0 protocol. In the DSMART, it changes the error signaling of character repetition */
  45. #define CRD_DET_EN BIT(0) /* When this bit is HIGH CRD_DET bit in Card Status register will follow the state of the cdet pin */
  46. /* bit definition for MSTATUS/MMASK */
  47. #define CRD_EV_IRQ BIT(7)
  48. #define ERR_EV_IRQ BIT(6)
  49. #define TX_EV_IRQ BIT(5)
  50. #define RX_EV_IRQ BIT(4)
  51. #define TX_EM_IRQ BIT(3)
  52. #define BREAK_IRQ BIT(2)
  53. #define BLK_FIN_IRQ BIT(1)
  54. #define RX_AV_IRQ BIT(0)
  55. /* bit definition for CSTATUS */
  56. #define ODDP BIT(7)
  57. #define SES_END_CARD_STATE BIT(6)
  58. #define TIMEOUT_CARD_STATE BIT(5)
  59. #define SYNC_ERR_CARD_STATE BIT(4)
  60. #define CONV_CARD_STATE BIT(3)
  61. #define CRD_ERR_CARD_STATE BIT(2)
  62. #define CRD_ACT_CARD_STATE BIT(1)
  63. #define CRD_DET_CARD_STATE BIT(0)
  64. /* bit definition for MISC */
  65. #define TX_TR BIT(6)
  66. #define RX_TR BIT(4)
  67. #define TXFIFO_ON BIT(3)
  68. #define RXFIFO_ON BIT(2)
  69. #define CRC_MOD BIT(1)
  70. #define CRC_EN BIT(0)
  71. #define RX_TR_OFF 4
  72. #define TX_TR_OFF 6
  73. #define RX_TR_MSK 0x3
  74. #define TX_TR_MSK 0x3
  75. /* bit definition for CONTROL */
  76. #define TX_END BIT(7)
  77. #define LAST BIT(6)
  78. #define PWD BIT(5)
  79. #define RT BIT(4)
  80. #define STOP BIT(3)
  81. #define CLR_ERR BIT(2)
  82. #define WRST BIT(1)
  83. #define START BIT(0)
  84. /* bit definition for WT0/BGT */
  85. #define BIT_WT2 BIT(7)
  86. #define WT1 BIT(6)
  87. #define WT0 BIT(5)
  88. #define BGT4 BIT(4)
  89. #define BGT3 BIT(3)
  90. #define BGT2 BIT(2)
  91. #define BGT1 BIT(1)
  92. #define BGT0 BIT(0)
  93. #define WT0_OFF 5
  94. #define BGT_OFF 0
  95. #define WT0_MSK 0x7
  96. #define BGT_MSK 0x1f
  97. /* bit definition for WT1/CWT */
  98. #define WT6 BIT(7)
  99. #define WT5 BIT(6)
  100. #define WT4 BIT(5)
  101. #define BIT_WT3 BIT(4)
  102. #define CWT3 BIT(3)
  103. #define CWT2 BIT(2)
  104. #define CWT1 BIT(1)
  105. #define CWT0 BIT(0)
  106. #define WT3_OFF 4
  107. #define CWT_OFF 0
  108. #define WT3_MSK 0xf
  109. #define CWT_MSK 0xf
  110. /* bit definition for ERROR/MERROR */
  111. #define PAR_ERR_STATE BIT(0)
  112. #define CRC_ERR_STATE BIT(1)
  113. #define REP_ERR_STATE BIT(2)
  114. #define RX_OVER_ERR_STATE BIT(3)
  115. #define TX_FULL_ERR_STATE BIT(4)
  116. #define CWT_TIM_ERR_STATE BIT(5)
  117. #define RX_FULL_ERR_STATE BIT(6)
  118. #define MAX_DSMART_CARD_CWT 10080 /* in ETU */
  119. #define CVOL_CLASS_MSK 0x3
  120. #define DSMART_CARD_RCV_BUFFER_SIZE 400
  121. #define DSMART_CARD_XMT_BUFFER_SIZE 300
  122. #define DSMART_CARD_PRESENT_REMOVED 0
  123. #define DSMART_CARD_PRESENT_DETECTED 1
  124. #define DSMART_CARD_STATE_REMOVED 0
  125. #define DSMART_CARD_STATE_DETECTED 1
  126. #define DSMART_CARD_STATE_ACTIVATED 2
  127. #define DSMART_CARD_STATE_RECEIVING 3
  128. #define DSMART_CARD_STATE_RECEIVE_DONE 4
  129. #define DSMART_CARD_STATE_ATR_RECEIVING 5
  130. #define DSMART_CARD_STATE_ATR_RECEIVE_DONE 6
  131. #define DSMART_CARD_STATE_XMTING 7
  132. #define DSMART_CARD_FIFO_SIZE 16
  133. enum trans_direction {
  134. RECEIVER_MOD,
  135. TRANSMITTER_MOD,
  136. };
  137. enum card_staus {
  138. DEACTIVATE,
  139. ACTIVATING,
  140. PSS_TRF,
  141. PSS_RECV,
  142. ACTIVATE,
  143. };
  144. enum dsmart_card_event {
  145. EVENT_CARD_DETECTED,
  146. EVENT_READ_COMPLETE,
  147. EVENT_WRITE_COMPLETE,
  148. EVENT_READ_ERROR,
  149. EVENT_WRITE_ERROR,
  150. EVENT_ACTIVATE_SUCCESS,
  151. EVENT_ACTIVATE_FAILED,
  152. EVENT_CARD_ERROR_DEACTIVATE,
  153. EVENT_CARD_SESSION_CLOSED,
  154. EVENT_RX_FULL,
  155. EVENT_CWT_TIME_OUT,
  156. EVENT_RX_OVER,
  157. EVENT_CRC_ERR,
  158. EVENT_PARITY_ERR,
  159. EVENT_SLAVE_ATR_DETECTED,
  160. EVENT_SLAVE_ATR_DONE,
  161. };
  162. struct dsmart_card {
  163. struct device *dev;
  164. void __iomem *base;
  165. struct clk *clk;
  166. int irq;
  167. spinlock_t lock;
  168. u8 rcv_buffer[DSMART_CARD_RCV_BUFFER_SIZE];
  169. u8 xmt_buffer[DSMART_CARD_XMT_BUFFER_SIZE];
  170. struct completion xfer_done;
  171. enum card_staus card_sta;
  172. int protocol_type;
  173. int present;
  174. u32 expected_rcv_cnt;
  175. u32 rx_threshold;
  176. u32 tx_threshold;
  177. bool is_fixed_len;
  178. int rcv_head;
  179. int rcv_count;
  180. int xmt_head;
  181. int xmt_count;
  182. int xmt_remainning_count;
  183. int errval;
  184. struct dsmart_card_timing timing_data;
  185. int state;
  186. struct dsmart_card_baud baud_rate;
  187. };
  188. static inline void card_clk_div_set(void __iomem *base, u32 val)
  189. {
  190. writel(val, base + CCLK_DIV);
  191. }
  192. static inline void card_vol_class_set(void __iomem *base, u32 val)
  193. {
  194. u32 data = readl(base + CONFIG);
  195. data &= ~(CVOL_CLASS_MSK << AB);
  196. data |= val << AB;
  197. writel(data, base + CONFIG);
  198. }
  199. static inline void card_det_enable(void __iomem *base, bool en)
  200. {
  201. u32 data = readl(base + CONFIG);
  202. if (en)
  203. data |= CRD_DET_EN;
  204. else
  205. data &= ~CRD_DET_EN;
  206. writel(data, base + CONFIG);
  207. }
  208. static inline void card_event_interrupt_enable(void __iomem *base, u32 mask, bool en)
  209. {
  210. u32 data = readl(base + MSTATUS_MMASK);
  211. if (en)
  212. data |= mask;
  213. else
  214. data &= ~mask;
  215. writel(data, base + MSTATUS_MMASK);
  216. }
  217. static inline void card_glb_interrupt_enable(void __iomem *base, bool en)
  218. {
  219. u32 data = readl(base + CONFIG);
  220. if (en)
  221. data |= MIE;
  222. else
  223. data &= ~MIE;
  224. writel(data, base + CONFIG);
  225. }
  226. static inline void card_odd_parity_set(void __iomem *base, bool en)
  227. {
  228. u32 data = readl(base + CSTATUS);
  229. if (en)
  230. data |= ODDP;
  231. else /* EVEN Parity */
  232. data &= ~ODDP;
  233. writel(data, base + CSTATUS);
  234. }
  235. static inline void card_trans_protocol_set(void __iomem *base, int proto)
  236. {
  237. u32 data = readl(base + CONFIG);
  238. if (proto == CARD_PROTOCOL_T0)
  239. data &= ~TMOD;
  240. else
  241. data |= TMOD;
  242. writel(data, base + CONFIG);
  243. }
  244. static inline void card_tx_fifo_enable(void __iomem *base, bool en)
  245. {
  246. u32 data = readl(base + MISC);
  247. if (en)
  248. data |= TXFIFO_ON;
  249. else
  250. data &= ~TXFIFO_ON;
  251. writel(data, base + MISC);
  252. }
  253. static inline void card_rx_fifo_enable(void __iomem *base, bool en)
  254. {
  255. u32 data = readl(base + MISC);
  256. if (en)
  257. data |= RXFIFO_ON;
  258. else
  259. data &= ~RXFIFO_ON;
  260. writel(data, base + MISC);
  261. }
  262. static inline void card_trans_direction_set(void __iomem *base, enum trans_direction dire)
  263. {
  264. u32 data = readl(base + CONTROL);
  265. if (dire == RECEIVER_MOD)
  266. data &= ~RT;
  267. else
  268. data |= RT;
  269. writel(data, base + CONTROL);
  270. }
  271. static inline void card_warm_reset(void __iomem *base)
  272. {
  273. u32 data = readl(base + CONTROL);
  274. data |= WRST;
  275. writel(data, base + CONTROL);
  276. }
  277. /*
  278. * shall not exceed WWT={960xDxWI}x1etu, where D=TA1 interface byte, WI=TC2 interface byte.
  279. * WWT value should be a priori converted to current ETU value written to the WT0-WT3 register
  280. */
  281. static inline void card_wwt_time_set(void __iomem *base, u32 time)
  282. {
  283. u32 data = readl(base + WT0_BGT);
  284. data &= ~(WT0_MSK << WT0_OFF);
  285. data |= ((time >> 0) & WT0_MSK) << WT0_OFF;
  286. writel(data, base + WT0_BGT);
  287. data = readl(base + WT1_CWT);
  288. data &= ~(WT3_MSK << WT3_OFF);
  289. data |= ((time >> 3) & WT3_MSK) << WT3_OFF;
  290. writel(data, base + WT1_CWT);
  291. data = ~0xff;
  292. data |= (time >> 7) & 0xff;
  293. writel(data, base + WT2);
  294. data = ~0xff;
  295. data |= (time >> 15) & 0xff;
  296. writel(data, base + WT3);
  297. }
  298. static inline void card_trans_start(void __iomem *base)
  299. {
  300. writel(readl(base + CONTROL) | START, base + CONTROL);
  301. }
  302. /*
  303. *When set HIGH the interface begins the deactivation procedure. After card deactivation this signal is automatically cleared.
  304. *It can be also used to clear card detection or session end interrupt without invoking the activation procedure
  305. */
  306. static inline void card_trans_stop(void __iomem *base)
  307. {
  308. writel(readl(base + CONTROL) | STOP, base + CONTROL);
  309. }
  310. static inline void card_rx_threshold_set(void __iomem *base, u32 val)
  311. {
  312. u32 data = readl(base + MISC);
  313. data &= ~(RX_TR_MSK << RX_TR_OFF);
  314. data |= (val & RX_TR_MSK) << RX_TR_OFF;
  315. writel(data, base + MISC);
  316. }
  317. static inline void card_tx_threshold_set(void __iomem *base, u32 val)
  318. {
  319. u32 data = readl(base + MISC);
  320. data &= ~(TX_TR_MSK << TX_TR_OFF);
  321. data |= (val & TX_TR_MSK) << TX_TR_OFF;
  322. writel(data, base + MISC);
  323. }
  324. static inline u32 card_mstatus_get(void __iomem *base)
  325. {
  326. return readl(base + MSTATUS_MMASK);
  327. }
  328. static inline u32 card_status_get(void __iomem *base)
  329. {
  330. return readl(base + CSTATUS);
  331. }
  332. static inline void card_error_clear(void __iomem *base)
  333. {
  334. writel(readl(base + CONTROL) | CLR_ERR, base + CONTROL);
  335. }
  336. static inline u32 card_error_status_get(void __iomem *base)
  337. {
  338. return readl(base + ERROR_MERROR);
  339. }
  340. static inline void card_bgt_time_set(void __iomem *base, u32 time)
  341. {
  342. u32 data = readl(base + WT0_BGT);
  343. data &= ~0x1f;
  344. data |= time & 0x1f;
  345. writel(data, base + WT0_BGT);
  346. }
  347. static inline void card_cwt_time_set(void __iomem *base, u32 time)
  348. {
  349. u32 data = readl(base + WT1_CWT);
  350. data &= ~0xf;
  351. data |= time & 0xf;
  352. writel(data, base + WT1_CWT);
  353. }
  354. /* BWT={(2BWIx960)+11}x1etu. The result should be written into the WT0-WT3 registers */
  355. static inline void card_bwt_time_set(void __iomem *base, u32 time)
  356. {
  357. card_wwt_time_set(base, time);
  358. }
  359. /*
  360. * The value of 255 indicates that the minimum GUARD TIME (2 ETU for T=0 protocol and 1 ETU for T=1 protocol) should be used,
  361. * then the minimum character to character duration for subsequent transmissions shall be 12 ETUs if T=0 protocol is used,
  362. * or 11 ETUs if T=1 protocol is used. The exact value of EXTRA GUARD TIME (from 0 to 254) should be written into the guard time register.
  363. * Default value after reset is 1
  364. */
  365. static inline void card_egt_time_set(void __iomem *base, u32 time) /* means char guard time */
  366. {
  367. writel(time, base + EGT);
  368. }
  369. /* 1etu={1/f}x{Fi/Di} */
  370. static inline void card_baud_rate_set(void __iomem *base, u32 fi, u32 di)
  371. {
  372. u32 data = (fi & 0xf) << 4 | (di & 0xf);
  373. writel(data, base + ETU);
  374. }
  375. static inline u32 card_data_length_get(void __iomem *base)
  376. {
  377. return readl(base + LENGTH);
  378. }
  379. static inline u32 card_fifo_data_get(void __iomem *base)
  380. {
  381. return readl(base + RX_TX_FIFO);
  382. }
  383. static inline void card_fifo_data_set(void __iomem *base, u8 data)
  384. {
  385. writel(data, base + RX_TX_FIFO);
  386. }
  387. static struct miscdevice dsmart_card_dev;
  388. static void dsmart_card_rcv_read_fifo(struct dsmart_card *card)
  389. {
  390. u32 i, data, len = card_data_length_get(card->base);
  391. pr_debug("%s, %d: len = %d\n", __func__, __LINE__, len);
  392. if (!len)
  393. card_fifo_data_get(card->base); //clear the fifo
  394. spin_lock(&card->lock);
  395. for (i = 0; i < len; i++) {
  396. data = card_fifo_data_get(card->base);
  397. card->rcv_buffer[card->rcv_head + card->rcv_count] = (u8)data;
  398. pr_debug("data%d = 0x%x , card->rcv_buffer[%d] = 0x%x ", i, data, card->rcv_head + card->rcv_count,
  399. card->rcv_buffer[card->rcv_head + card->rcv_count]);
  400. card->rcv_count++;
  401. if (card->rcv_head + card->rcv_count >= DSMART_CARD_RCV_BUFFER_SIZE) {
  402. pr_err("the software fifo is full, head:%d, count:%d\n", card->rcv_head,
  403. card->rcv_count);
  404. break;
  405. }
  406. }
  407. spin_unlock(&card->lock);
  408. }
  409. static void dsmart_card_xmt_write_fifo(struct dsmart_card *card)
  410. {
  411. u32 i, data, len = card_data_length_get(card->base);
  412. u32 avail_size = 0;
  413. spin_lock(&card->lock);
  414. avail_size = DSMART_CARD_FIFO_SIZE - len;
  415. for (i = 0; i < avail_size; i++) {
  416. data = card->xmt_buffer[card->xmt_head + card->xmt_count];
  417. card_fifo_data_set(card->base, data);
  418. card->xmt_count++;
  419. if (card->xmt_head + card->xmt_count >= DSMART_CARD_XMT_BUFFER_SIZE) {
  420. pr_err("the software fifo is empty, head:%d, count:%d\n", card->xmt_head,
  421. card->xmt_count);
  422. break;
  423. }
  424. }
  425. spin_unlock(&card->lock);
  426. }
  427. static void dsmart_error_event_handle(struct dsmart_card *card)
  428. {
  429. u32 err_status = card_error_status_get(card->base);
  430. if (err_status & RX_FULL_ERR_STATE) {
  431. dsmart_card_rcv_read_fifo(card);
  432. card->state = DSMART_CARD_STATE_RECEIVE_DONE;
  433. return;
  434. }
  435. if (err_status & TX_FULL_ERR_STATE) {
  436. //card->errval = -DSMART_CARD_E_TX_FULL;
  437. card->errval = DSMART_CARD_OK;
  438. return;
  439. }
  440. if (err_status & PAR_ERR_STATE) {
  441. card->errval = -DSMART_CARD_E_PAR_ERR;
  442. pr_err("par error occured\n");
  443. } else if (err_status & CRC_ERR_STATE) {
  444. card->errval = -DSMART_CARD_E_CRC_ERR;
  445. pr_err("crc error occured\n");
  446. } else if (err_status & REP_ERR_STATE) {
  447. card->errval = -DSMART_CARD_E_REP_ERR;
  448. pr_err("rep error occured\n");
  449. } else if (err_status & CWT_TIM_ERR_STATE) {
  450. card->errval = -DSMART_CARD_E_CWT_TIM;
  451. pr_err("cwt_tim error occured\n");
  452. } else if (err_status & RX_OVER_ERR_STATE) {
  453. card->errval = -DSMART_CARD_E_RX_OVER;
  454. pr_err("rx_over error occured\n");
  455. } else {
  456. pr_err("invalid error event number\n");
  457. return;
  458. }
  459. /* clear the error to stop interrupt */
  460. card_error_clear(card->base);
  461. card_event_interrupt_enable(card->base, ERR_EV_IRQ, false);
  462. }
  463. static void dsmart_card_event_handle(struct dsmart_card *card)
  464. {
  465. u32 card_status = card_status_get(card->base);
  466. pr_debug("%s:%d, card event status = 0x%x\n", __func__, __LINE__, card_status);
  467. if (card_status & CRD_DET_CARD_STATE) {
  468. card->present = DSMART_CARD_PRESENT_DETECTED;
  469. card->state = DSMART_CARD_STATE_DETECTED;
  470. card->errval = DSMART_CARD_OK;
  471. pr_debug("%s:%d\n", __func__, __LINE__);
  472. card_event_interrupt_enable(card->base, CRD_EV_IRQ, false);
  473. complete(&card->xfer_done);
  474. /* just clear the card detection interrupt without invoking the activation procedure */
  475. //card_trans_stop(card->base);
  476. } else if (card_status & CRD_ACT_CARD_STATE) {
  477. pr_debug("%s:%d\n", __func__, __LINE__);
  478. complete(&card->xfer_done);
  479. } else if (card_status & TIMEOUT_CARD_STATE) {
  480. card->errval = -DSMART_CARD_E_ACT_TIMEOUT;
  481. card_error_clear(card->base);
  482. pr_debug("%s:%d\n", __func__, __LINE__);
  483. } else if (card_status & CRD_ERR_CARD_STATE) {
  484. card->errval = -DSMART_CARD_E_REMOVED;
  485. card_error_clear(card->base);
  486. pr_debug("%s:%d\n", __func__, __LINE__);
  487. } else if (card_status & SES_END_CARD_STATE) {
  488. pr_debug("the session is terminated\n");
  489. }
  490. }
  491. static irqreturn_t dsmart_card_handler(int irq, void *p)
  492. {
  493. struct dsmart_card *card = (struct dsmart_card *)p;
  494. u32 card_event = card_mstatus_get(card->base);
  495. pr_debug("%s:%d, irq status = 0x%x\n", __func__, __LINE__, card_event);
  496. if (card_event & CRD_EV_IRQ) {
  497. dsmart_card_event_handle(card);
  498. }
  499. if (card_event & ERR_EV_IRQ) {
  500. dsmart_error_event_handle(card);
  501. }
  502. if (card_event & RX_AV_IRQ) {
  503. dsmart_card_rcv_read_fifo(card);
  504. pr_debug("%s:%d\n", __func__, __LINE__);
  505. }
  506. if (card_event & TX_EM_IRQ) {
  507. dsmart_card_xmt_write_fifo(card);
  508. pr_debug("%s:%d\n", __func__, __LINE__);
  509. }
  510. if (card_event & RX_EV_IRQ) {
  511. dsmart_card_rcv_read_fifo(card);
  512. pr_debug("%s:%d\n", __func__, __LINE__);
  513. }
  514. if (card_event & TX_EV_IRQ) {
  515. dsmart_card_xmt_write_fifo(card);
  516. pr_debug("%s:%d\n", __func__, __LINE__);
  517. }
  518. //complete(&card->xfer_done);
  519. return IRQ_HANDLED;
  520. }
  521. static int dsmart_card_check_timing_data(struct dsmart_card_timing *timing_data)
  522. {
  523. pr_debug("wwt = 0x%d, cwt = 0x%d, bwt = 0x%d, bgt = 0x%d, egt = 0x%d\n",
  524. timing_data->wwt, timing_data->cwt, timing_data->bwt, timing_data->bgt, timing_data->egt);
  525. if (timing_data->wwt > 0x7fffff ||
  526. timing_data->cwt > 0xf ||
  527. timing_data->bwt > 0x7fffff ||
  528. timing_data->bgt > 0x1f ||
  529. timing_data->egt > 0xf) {
  530. pr_err("the timing value is out of scope\n");
  531. return -EINVAL;
  532. }
  533. return 0;
  534. }
  535. static int dsmart_card_baud_rate_check(struct dsmart_card_baud *rate)
  536. {
  537. /*
  538. * According to Table: The clock rate conversion Fi integer & Table: The baud rate dividion Di integer
  539. */
  540. if (rate->fi == 7 || rate->fi >= 0xe || rate->di >= 0xa)
  541. return -EINVAL;
  542. return 0;
  543. }
  544. static void dsmart_card_baud_rate_set(struct dsmart_card *card)
  545. {
  546. if (card->baud_rate.fi && card->baud_rate.di)
  547. card_baud_rate_set(card->base, card->baud_rate.fi, card->baud_rate.di);
  548. }
  549. static void dsmart_card_data_reset(struct dsmart_card *card)
  550. {
  551. card->errval = DSMART_CARD_OK;
  552. card->rcv_count = 0;
  553. card->rcv_head = 0;
  554. card->xmt_count = 0;
  555. card->xmt_remainning_count = 0;
  556. card->xmt_head = 0;
  557. card->protocol_type = CARD_PROTOCOL_T0;
  558. card_event_interrupt_enable(card->base, 0xff, false);
  559. card_tx_fifo_enable(card->base, false);
  560. card_rx_fifo_enable(card->base, false);
  561. card_rx_threshold_set(card->base, 2); /* set minimum threshold for receiving atr */
  562. card_event_interrupt_enable(card->base, CRD_EV_IRQ, true); /* enable card & error event occur first */
  563. card_glb_interrupt_enable(card->base, true);
  564. /* set card working frequency as 1M clk, clk = pclk / {(CLK_DIV + 1) * 2}*/
  565. #ifdef CONFIG_MAX_CCLK
  566. card_clk_div_set(card->base, 1); //7
  567. #else
  568. card_clk_div_set(card->base, 29);
  569. #endif
  570. memset(card->rcv_buffer, 0, DSMART_CARD_RCV_BUFFER_SIZE);
  571. memset(card->xmt_buffer, 0, DSMART_CARD_XMT_BUFFER_SIZE);
  572. memset(&card->timing_data, 0, sizeof(card->timing_data));
  573. memset(&card->baud_rate, 0, sizeof(card->baud_rate));
  574. reinit_completion(&card->xfer_done);
  575. }
  576. static int dsmart_card_detect(struct dsmart_card *card)
  577. {
  578. reinit_completion(&card->xfer_done);
  579. card_det_enable(card->base, true);
  580. /* check the card if detected */
  581. if (wait_for_completion_interruptible(&card->xfer_done)) {/* wait for CRD_DET bit set */
  582. pr_err("%s, %d: dsmart card detected timeout\n", __func__, __LINE__);
  583. return -ETIMEDOUT;
  584. }
  585. card->state = DSMART_CARD_STATE_DETECTED;
  586. pr_debug("%s:%d\n", __func__, __LINE__);
  587. return 0;
  588. }
  589. static int dsmart_card_start_data_rcv(struct dsmart_card *card, unsigned long arg)
  590. {
  591. dsmart_card_baud_rate_set(card);
  592. card_trans_protocol_set(card->base, card->protocol_type);
  593. card_rx_fifo_enable(card->base, true);
  594. card_trans_direction_set(card->base, RECEIVER_MOD);
  595. card->state = DSMART_CARD_STATE_RECEIVING;
  596. card_event_interrupt_enable(card->base, RX_EV_IRQ | RX_AV_IRQ, true);
  597. card_trans_start(card->base);
  598. #if 0
  599. reinit_completion(&card->xfer_done);
  600. pr_debug("%s:%d\n", __func__, __LINE__);
  601. /* wait RX_TD interrupt */
  602. if (wait_for_completion_interruptible(&card->xfer_done)) {
  603. pr_err("%s,%d: timeout in receiving normal data\n", __func__, __LINE__);
  604. return -DSMART_CARD_E_DATA_TIMEOUT;
  605. }
  606. #endif
  607. pr_debug("%s:%d\n", __func__, __LINE__);
  608. return 0;
  609. }
  610. static int dsmart_card_atr_rcv(struct dsmart_card *card, unsigned long arg)
  611. {
  612. int __maybe_unused i;
  613. u32 delay_cnt = 0;
  614. u32 card_status = card_status_get(card->base);
  615. card_tx_fifo_enable(card->base, true);
  616. card_trans_direction_set(card->base, RECEIVER_MOD);
  617. /*Set the cwt timer.Refer the setting of ATR on EMV4.3 book*/
  618. //card_wwt_time_set(card->base, MAX_DSMART_CARD_CWT);
  619. /* Set 12 ETUS */
  620. //card_egt_time_set(card->base, 0xff);
  621. card_trans_start(card->base); /* activate the secquence */
  622. card_fifo_data_set(card->base, 0x1);
  623. card_fifo_data_set(card->base, 0x2);
  624. card_fifo_data_set(card->base, 0x3);
  625. card_trans_direction_set(card->base, TRANSMITTER_MOD);
  626. pr_debug("%s:%d\n", __func__, __LINE__);
  627. #if 1
  628. while ((card_status & CRD_ACT_CARD_STATE) != CRD_ACT_CARD_STATE) {
  629. card_status = card_status_get(card->base);
  630. mdelay(1);
  631. delay_cnt++;
  632. }
  633. #else
  634. card_event_interrupt_enable(card->base, CRD_EV_IRQ, true);
  635. reinit_completion(&card->xfer_done);
  636. if (wait_for_completion_interruptible(&card->xfer_done)) { /* wait for successful activation */
  637. pr_err("%s, %d: dsmart card activate timeout\n", __func__, __LINE__);
  638. return -ETIMEDOUT;
  639. }
  640. #endif
  641. pr_debug("delay_cnt = %d ms\n", delay_cnt);
  642. card->state = DSMART_CARD_STATE_ACTIVATED;
  643. pr_debug("%s:%d\n", __func__, __LINE__);
  644. card_event_interrupt_enable(card->base, RX_EV_IRQ, true);
  645. card_rx_fifo_enable(card->base, true);
  646. card->state = DSMART_CARD_STATE_ATR_RECEIVING;
  647. pr_debug("%s:%d\n", __func__, __LINE__);
  648. card_trans_direction_set(card->base, RECEIVER_MOD);
  649. pr_debug("%s:%d\n", __func__, __LINE__);
  650. msleep(5000); //how to confirm the atr length ?
  651. card->state = DSMART_CARD_STATE_ATR_RECEIVE_DONE;
  652. #ifdef CONFIG_ATR_DATA_PRINT
  653. for (i = 0; i < card->rcv_count; i++) {
  654. pr_debug("0x%02x ", card->rcv_buffer[i]);
  655. }
  656. #endif
  657. pr_info("[%s:%d]set fcclk as 15M\n", __func__, __LINE__);
  658. card_clk_div_set(card->base, 1);
  659. return 0;
  660. }
  661. static int dsmart_card_start_data_xmt(struct dsmart_card *card, unsigned long arg)
  662. {
  663. dsmart_card_baud_rate_set(card);
  664. card_trans_protocol_set(card->base, card->protocol_type);
  665. card_tx_fifo_enable(card->base, true);
  666. card_trans_direction_set(card->base, TRANSMITTER_MOD);
  667. card->state = DSMART_CARD_STATE_XMTING;
  668. card_event_interrupt_enable(card->base, TX_EV_IRQ | TX_EM_IRQ, true);
  669. card_trans_start(card->base);
  670. reinit_completion(&card->xfer_done);
  671. pr_debug("%s:%d\n", __func__, __LINE__);
  672. /* wait RX_TD interrupt */
  673. if (wait_for_completion_interruptible(&card->xfer_done)) {
  674. pr_err("%s,%d: timeout in receiving normal data\n", __func__, __LINE__);
  675. return -DSMART_CARD_E_DATA_TIMEOUT;
  676. }
  677. pr_debug("%s:%d\n", __func__, __LINE__);
  678. return 0;
  679. }
  680. static void dsmart_card_deactivate(struct dsmart_card *card)
  681. {
  682. card_trans_stop(card);
  683. }
  684. static int dsmart_card_warm_reset(struct dsmart_card *card)
  685. {
  686. card_warm_reset(card->base);
  687. pr_info("[%s:%d]set fcclk as 1M\n", __func__, __LINE__);
  688. card_clk_div_set(card->base, 29);
  689. card->errval = DSMART_CARD_OK;
  690. return dsmart_card_atr_rcv(card, 0);
  691. }
  692. static void dsmart_card_timing_counter_set(struct dsmart_card *card)
  693. {
  694. if (card->timing_data.wwt && card->protocol_type == CARD_PROTOCOL_T0) {
  695. card->timing_data.cwt = card->timing_data.wwt;
  696. card->timing_data.bwt = card->timing_data.wwt;
  697. card_wwt_time_set(card->base, card->timing_data.cwt);
  698. }
  699. if (card->timing_data.bgt && card->protocol_type == CARD_PROTOCOL_T1)
  700. card_bgt_time_set(card->base, card->timing_data.bgt);
  701. if (card->timing_data.cwt && card->protocol_type == CARD_PROTOCOL_T1)
  702. card_cwt_time_set(card->base, card->timing_data.cwt);
  703. if (card->timing_data.egt)
  704. card_egt_time_set(card->base, card->timing_data.egt);
  705. }
  706. static int dsmart_card_open(struct inode *inode, struct file *filp)
  707. {
  708. struct dsmart_card *dsmart_card = dev_get_drvdata(dsmart_card_dev.parent);
  709. filp->private_data = dsmart_card;
  710. spin_lock_init(&dsmart_card->lock);
  711. //dsmart_card_data_reset(dsmart_card);
  712. return 0;
  713. }
  714. static int dsmart_card_release(struct inode *inode, struct file *filp)
  715. {
  716. /* struct dsmart_card *dsmart_card = (struct dsmart_card *)filp->private_data; */
  717. return 0;
  718. }
  719. static long dsmart_card_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
  720. {
  721. int ret = 0;
  722. int __maybe_unused i;
  723. struct dsmart_card *card = (struct dsmart_card *)filp->private_data;
  724. u32 copy_cnt;
  725. unsigned long flags;
  726. u32 xmt_size = 0;
  727. pr_debug("%s entering, cmd = 0x%x\n", __func__, cmd);
  728. switch (cmd) {
  729. case DSMART_CARD_IOCTL_SET_PROTOCOL:
  730. pr_debug("%s:%d\n", __func__, __LINE__);
  731. ret = copy_from_user(&card->protocol_type, (int *)arg, sizeof(int));
  732. if (ret)
  733. pr_err("protocol copy error\n");
  734. break;
  735. case DSMART_CARD_IOCTL_DEACTIVATE:
  736. pr_debug("%s:%d\n", __func__, __LINE__);
  737. dsmart_card_deactivate(card);
  738. break;
  739. case DSMART_CARD_IOCTL_COLD_RESET:
  740. pr_debug("%s:%d\n", __func__, __LINE__);
  741. card->present = DSMART_CARD_PRESENT_REMOVED;
  742. card->state = DSMART_CARD_STATE_REMOVED;
  743. dsmart_card_data_reset(card);
  744. ret = dsmart_card_detect(card);
  745. if (ret) {
  746. pr_err("no card found\n");
  747. ret = -DSMART_CARD_E_DATA_TIMEOUT;
  748. break;
  749. }
  750. pr_debug("%s:%d\n", __func__, __LINE__);
  751. ret = dsmart_card_atr_rcv(card, arg);
  752. break;
  753. case DSMART_CARD_IOCTL_WARM_RESET:
  754. pr_debug("%s:%d\n", __func__, __LINE__);
  755. card_clk_div_set(card->base, 29);
  756. ret = dsmart_card_warm_reset(card);
  757. break;
  758. case DSMART_CARD_IOCTL_SET_TIMING:
  759. pr_debug("%s:%d\n", __func__, __LINE__);
  760. ret = copy_from_user(&card->timing_data, (struct dsmart_card_timing *)arg,
  761. sizeof(struct dsmart_card_timing));
  762. if (ret) {
  763. pr_err("timing copy error\n");
  764. break;
  765. }
  766. ret = dsmart_card_check_timing_data(&card->timing_data);
  767. break;
  768. case DSMART_CARD_IOCTL_SET_BAUD:
  769. pr_debug("%s:%d\n", __func__, __LINE__);
  770. ret = copy_from_user(&card->baud_rate, (struct dsmart_card_baud *)arg,
  771. sizeof(struct dsmart_card_baud));
  772. if (ret) {
  773. pr_err("baud rate copy error\n");
  774. break;
  775. }
  776. ret = dsmart_card_baud_rate_check(&card->baud_rate);
  777. if (ret)
  778. pr_err("invalid baud rate value\n");
  779. break;
  780. case DSMART_CARD_IOCTL_SET_RX_THRESHOLD:
  781. pr_debug("%s:%d\n", __func__, __LINE__);
  782. ret = copy_from_user(&card->rx_threshold, (int *)arg, sizeof(int));
  783. if (ret) {
  784. pr_err("threshold copy error\n");
  785. break;
  786. }
  787. break;
  788. case DSMART_CARD_IOCTL_SET_TX_THRESHOLD:
  789. pr_debug("%s:%d\n", __func__, __LINE__);
  790. break;
  791. case DSMART_CARD_IOCTL_ATR_RCV:
  792. pr_debug("%s:%d\n", __func__, __LINE__);
  793. if (card->state != DSMART_CARD_STATE_ATR_RECEIVE_DONE) {
  794. pr_err("failed to activate sequence\n");
  795. ret = -DSMART_CARD_E_ACTIVATE_FAILED;
  796. goto report_error;
  797. }
  798. ret = copy_to_user(&(((struct dsmart_card_atr *)arg)->len), &card->rcv_count,
  799. sizeof(card->rcv_count));
  800. if (ret) {
  801. pr_err("len copy error\n");
  802. ret = -DSMART_CARD_E_ACCESS;
  803. goto report_error;
  804. }
  805. ret = copy_to_user(((struct dsmart_card_atr __user *)arg)->atr_buffer, card->rcv_buffer, card->rcv_count);
  806. if (ret) {
  807. pr_err("failed to copy atr data to user\n");
  808. ret = -DSMART_CARD_E_ACCESS;
  809. goto report_error;
  810. }
  811. #ifdef CONFIG_ATR_DATA_PRINT
  812. for (i = 0; i < card->rcv_count; i++) {
  813. pr_info("0x%02x ", card->rcv_buffer[i]);
  814. }
  815. #endif
  816. pr_debug("%s:%d\n", __func__, __LINE__);
  817. report_error:
  818. pr_debug("%s:%d\n", __func__, __LINE__);
  819. ret = copy_to_user(&(((struct dsmart_card_atr __user *)arg)->errval), &card->errval,
  820. sizeof(card->errval));
  821. if (ret) {
  822. pr_err("ATR error value copy error\n");
  823. ret = -DSMART_CARD_E_ACCESS;
  824. break;
  825. }
  826. card->rcv_count = 0;
  827. card->rcv_head = 0;
  828. card->errval = 0;
  829. break;
  830. case DSMART_CARD_IOCTL_XMT:
  831. /*ret = dsmart_card_xmt(card);*/
  832. xmt_size = 0;
  833. pr_debug("%s:%d\n", __func__, __LINE__);
  834. ret = copy_from_user(&card->xmt_remainning_count, &(((struct dsmart_card_xmt __user *)arg)->xmt_length),
  835. sizeof(card->xmt_remainning_count));
  836. if (ret) {
  837. pr_err("get user xmt length error\n");
  838. ret = -DSMART_CARD_E_ACCESS;
  839. break;
  840. }
  841. if (card->xmt_remainning_count > DSMART_CARD_XMT_BUFFER_SIZE) {
  842. pr_err("the data to send is too big\n");
  843. ret = -EINVAL;
  844. break;
  845. }
  846. ret = copy_from_user(&card->xmt_buffer[card->xmt_head], ((struct dsmart_card_xmt __user *)arg)->xmt_buffer, xmt_size);
  847. if (ret) {
  848. pr_err("get user buffer data error\n");
  849. ret = -DSMART_CARD_E_ACCESS;
  850. break;
  851. }
  852. if (card->state != DSMART_CARD_STATE_XMTING) {
  853. dsmart_card_timing_counter_set(card);
  854. ret = dsmart_card_start_data_xmt(card, arg);
  855. if (ret) {
  856. pr_err("failed to xmt normal data\n");
  857. break;
  858. }
  859. }
  860. spin_lock_irqsave(&card->lock, flags);
  861. card->xmt_head += card->xmt_count;
  862. card->xmt_remainning_count -= card->xmt_count;
  863. card->xmt_count = 0;
  864. card->errval = 0;
  865. spin_unlock_irqrestore(&card->lock, flags);
  866. //dsmart_card_start_data_rcv(card, 0);
  867. break;
  868. case DSMART_CARD_IOCTL_RCV:
  869. pr_debug("%s:%d\n", __func__, __LINE__);
  870. ret = copy_from_user(&card->expected_rcv_cnt, &(((struct dsmart_card_rcv __user *)arg)->rcv_length),
  871. sizeof(card->expected_rcv_cnt));
  872. if (ret) {
  873. pr_err("rcv data error\n");
  874. ret = -DSMART_CARD_E_ACCESS;
  875. break;
  876. }
  877. if (card->expected_rcv_cnt)
  878. card->is_fixed_len = true;
  879. if ((card->rcv_count >= card->expected_rcv_cnt) && card->rcv_count)
  880. goto copy_data;
  881. if (card->state != DSMART_CARD_STATE_RECEIVING) {
  882. dsmart_card_timing_counter_set(card);
  883. ret = dsmart_card_start_data_rcv(card, arg);
  884. if (ret) {
  885. pr_err("failed to receive normal data\n");
  886. break;
  887. }
  888. msleep(5000);
  889. }
  890. pr_debug("%s:%d\n", __func__, __LINE__);
  891. copy_data:
  892. pr_debug("%s:%d\n", __func__, __LINE__);
  893. if (card->is_fixed_len)
  894. copy_cnt = card->rcv_count >= card->expected_rcv_cnt ? card->expected_rcv_cnt : card->rcv_count;
  895. else
  896. copy_cnt = card->rcv_count;
  897. ret = copy_to_user(&(((struct dsmart_card_rcv __user *)arg)->rcv_length), &copy_cnt, sizeof(copy_cnt));
  898. if (ret) {
  899. pr_err("length copy error\n");
  900. ret = -DSMART_CARD_E_ACCESS;
  901. break;
  902. }
  903. ret = copy_to_user(((struct dsmart_card_rcv __user *)arg)->rcv_buffer, &card->rcv_buffer[card->rcv_head], copy_cnt);
  904. if (ret) {
  905. pr_err("buffer copy error\n");
  906. ret = -DSMART_CARD_E_ACCESS;
  907. break;
  908. }
  909. ret = copy_to_user(&(((struct dsmart_card_rcv __user *)arg)->errval), &card->errval, sizeof(card->errval));
  910. if (ret) {
  911. pr_err("error value copy error\n");
  912. ret = -DSMART_CARD_E_ACCESS;
  913. break;
  914. }
  915. pr_debug("%s:%d, copy_cnt = %d, rcv_head = %d, rcv_count = %d\n", __func__, __LINE__, copy_cnt, card->rcv_head, card->rcv_count);
  916. #ifdef CONFIG_ATR_DATA_PRINT
  917. for (i = 0; i < copy_cnt; i++) {
  918. pr_info("%s, %d, 0x%x ", __func__, __LINE__, card->rcv_buffer[card->rcv_head + i]);
  919. }
  920. #endif
  921. spin_lock_irqsave(&card->lock, flags);
  922. card->rcv_head += copy_cnt;
  923. card->rcv_count -= copy_cnt;
  924. card->errval = 0;
  925. spin_unlock_irqrestore(&card->lock, flags);
  926. break;
  927. default:
  928. pr_err("invalid ioctol command\n");
  929. return -EINVAL;
  930. }
  931. pr_debug("%s:%d\n", __func__, __LINE__);
  932. return ret;
  933. }
  934. static const struct file_operations dsmart_card_fops = {
  935. .owner = THIS_MODULE,
  936. .open = dsmart_card_open,
  937. .release = dsmart_card_release,
  938. .unlocked_ioctl = dsmart_card_ioctl,
  939. };
  940. static struct miscdevice dsmart_card_dev = {
  941. MISC_DYNAMIC_MINOR,
  942. "dsmart_card",
  943. &dsmart_card_fops,
  944. };
  945. static int dsmart_card_probe(struct platform_device *pdev)
  946. {
  947. struct resource *res;
  948. struct dsmart_card *priv;
  949. int ret;
  950. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  951. if (!priv)
  952. return -ENOMEM;
  953. priv->irq = platform_get_irq(pdev, 0);
  954. if (priv->irq < 0) {
  955. dev_err(&pdev->dev, "failed to get irq for dsmart card\n");
  956. return priv->irq;
  957. }
  958. /* optional clock, default open */
  959. priv->clk = devm_clk_get(&pdev->dev, "dsmart_card");
  960. if(IS_ERR(priv->clk))
  961. priv->clk = NULL;
  962. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  963. priv->base = devm_ioremap_resource(&pdev->dev, res);
  964. if (IS_ERR(priv->base))
  965. return PTR_ERR(priv->base);
  966. platform_set_drvdata(pdev, priv);
  967. dsmart_card_dev.parent = &(pdev->dev);
  968. card_event_interrupt_enable(priv->base, 0xff, false);
  969. init_completion(&priv->xfer_done);
  970. ret = devm_request_irq(&pdev->dev, priv->irq, dsmart_card_handler, 0,
  971. "dsmart_card", priv);
  972. if (ret) {
  973. dev_err(&pdev->dev, "failed to register a dsmart card IRQ handler(%d)\n", ret);
  974. return ret;
  975. }
  976. ret = misc_register(&dsmart_card_dev);
  977. if (ret) {
  978. dev_err(&pdev->dev, "failed to register a misc device\n");
  979. return ret;
  980. }
  981. dev_info(&pdev->dev, "initialized iso7816 smart card driver\n");
  982. return 0;
  983. }
  984. static int dsmart_card_remove(struct platform_device *pdev)
  985. {
  986. misc_deregister(&dsmart_card_dev);
  987. return 0;
  988. }
  989. static const struct of_device_id dsmart_card_of_match[] = {
  990. {.compatible = "thead,light-iso7816-card"},
  991. {/* sentinel */},
  992. };
  993. MODULE_DEVICE_TABLE(of, dsmart_card_of_match);
  994. static struct platform_driver dsmart_card_driver = {
  995. .driver = {
  996. .name = "iso7816-card-drv",
  997. .owner = THIS_MODULE,
  998. .of_match_table = dsmart_card_of_match,
  999. },
  1000. .probe = dsmart_card_probe,
  1001. .remove = dsmart_card_remove,
  1002. };
  1003. module_platform_driver(dsmart_card_driver);
  1004. MODULE_AUTHOR("wei.liu <lw32886@linux.alibaba.com>");
  1005. MODULE_DESCRIPTION("iso7816 smart card platform driver");
  1006. MODULE_LICENSE("GPL v2");