cs5535-mfgpt.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for the CS5535/CS5536 Multi-Function General Purpose Timers (MFGPT)
  4. *
  5. * Copyright (C) 2006, Advanced Micro Devices, Inc.
  6. * Copyright (C) 2007 Andres Salomon <dilinger@debian.org>
  7. * Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk>
  8. *
  9. * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/cs5535.h>
  17. #include <linux/slab.h>
  18. #define DRV_NAME "cs5535-mfgpt"
  19. static int mfgpt_reset_timers;
  20. module_param_named(mfgptfix, mfgpt_reset_timers, int, 0644);
  21. MODULE_PARM_DESC(mfgptfix, "Try to reset the MFGPT timers during init; "
  22. "required by some broken BIOSes (ie, TinyBIOS < 0.99) or kexec "
  23. "(1 = reset the MFGPT using an undocumented bit, "
  24. "2 = perform a soft reset by unconfiguring all timers); "
  25. "use what works best for you.");
  26. struct cs5535_mfgpt_timer {
  27. struct cs5535_mfgpt_chip *chip;
  28. int nr;
  29. };
  30. static struct cs5535_mfgpt_chip {
  31. DECLARE_BITMAP(avail, MFGPT_MAX_TIMERS);
  32. resource_size_t base;
  33. struct platform_device *pdev;
  34. spinlock_t lock;
  35. int initialized;
  36. } cs5535_mfgpt_chip;
  37. int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
  38. int event, int enable)
  39. {
  40. uint32_t msr, mask, value, dummy;
  41. int shift = (cmp == MFGPT_CMP1) ? 0 : 8;
  42. if (!timer) {
  43. WARN_ON(1);
  44. return -EIO;
  45. }
  46. /*
  47. * The register maps for these are described in sections 6.17.1.x of
  48. * the AMD Geode CS5536 Companion Device Data Book.
  49. */
  50. switch (event) {
  51. case MFGPT_EVENT_RESET:
  52. /*
  53. * XXX: According to the docs, we cannot reset timers above
  54. * 6; that is, resets for 7 and 8 will be ignored. Is this
  55. * a problem? -dilinger
  56. */
  57. msr = MSR_MFGPT_NR;
  58. mask = 1 << (timer->nr + 24);
  59. break;
  60. case MFGPT_EVENT_NMI:
  61. msr = MSR_MFGPT_NR;
  62. mask = 1 << (timer->nr + shift);
  63. break;
  64. case MFGPT_EVENT_IRQ:
  65. msr = MSR_MFGPT_IRQ;
  66. mask = 1 << (timer->nr + shift);
  67. break;
  68. default:
  69. return -EIO;
  70. }
  71. rdmsr(msr, value, dummy);
  72. if (enable)
  73. value |= mask;
  74. else
  75. value &= ~mask;
  76. wrmsr(msr, value, dummy);
  77. return 0;
  78. }
  79. EXPORT_SYMBOL_GPL(cs5535_mfgpt_toggle_event);
  80. int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq,
  81. int enable)
  82. {
  83. uint32_t zsel, lpc, dummy;
  84. int shift;
  85. if (!timer) {
  86. WARN_ON(1);
  87. return -EIO;
  88. }
  89. /*
  90. * Unfortunately, MFGPTs come in pairs sharing their IRQ lines. If VSA
  91. * is using the same CMP of the timer's Siamese twin, the IRQ is set to
  92. * 2, and we mustn't use nor change it.
  93. * XXX: Likewise, 2 Linux drivers might clash if the 2nd overwrites the
  94. * IRQ of the 1st. This can only happen if forcing an IRQ, calling this
  95. * with *irq==0 is safe. Currently there _are_ no 2 drivers.
  96. */
  97. rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
  98. shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer->nr % 4) * 4;
  99. if (((zsel >> shift) & 0xF) == 2)
  100. return -EIO;
  101. /* Choose IRQ: if none supplied, keep IRQ already set or use default */
  102. if (!*irq)
  103. *irq = (zsel >> shift) & 0xF;
  104. if (!*irq)
  105. *irq = CONFIG_CS5535_MFGPT_DEFAULT_IRQ;
  106. /* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */
  107. if (*irq < 1 || *irq == 2 || *irq > 15)
  108. return -EIO;
  109. rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy);
  110. if (lpc & (1 << *irq))
  111. return -EIO;
  112. /* All chosen and checked - go for it */
  113. if (cs5535_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable))
  114. return -EIO;
  115. if (enable) {
  116. zsel = (zsel & ~(0xF << shift)) | (*irq << shift);
  117. wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
  118. }
  119. return 0;
  120. }
  121. EXPORT_SYMBOL_GPL(cs5535_mfgpt_set_irq);
  122. struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer_nr, int domain)
  123. {
  124. struct cs5535_mfgpt_chip *mfgpt = &cs5535_mfgpt_chip;
  125. struct cs5535_mfgpt_timer *timer = NULL;
  126. unsigned long flags;
  127. int max;
  128. if (!mfgpt->initialized)
  129. goto done;
  130. /* only allocate timers from the working domain if requested */
  131. if (domain == MFGPT_DOMAIN_WORKING)
  132. max = 6;
  133. else
  134. max = MFGPT_MAX_TIMERS;
  135. if (timer_nr >= max) {
  136. /* programmer error. silly programmers! */
  137. WARN_ON(1);
  138. goto done;
  139. }
  140. spin_lock_irqsave(&mfgpt->lock, flags);
  141. if (timer_nr < 0) {
  142. unsigned long t;
  143. /* try to find any available timer */
  144. t = find_first_bit(mfgpt->avail, max);
  145. /* set timer_nr to -1 if no timers available */
  146. timer_nr = t < max ? (int) t : -1;
  147. } else {
  148. /* check if the requested timer's available */
  149. if (!test_bit(timer_nr, mfgpt->avail))
  150. timer_nr = -1;
  151. }
  152. if (timer_nr >= 0)
  153. /* if timer_nr is not -1, it's an available timer */
  154. __clear_bit(timer_nr, mfgpt->avail);
  155. spin_unlock_irqrestore(&mfgpt->lock, flags);
  156. if (timer_nr < 0)
  157. goto done;
  158. timer = kmalloc(sizeof(*timer), GFP_KERNEL);
  159. if (!timer) {
  160. /* aw hell */
  161. spin_lock_irqsave(&mfgpt->lock, flags);
  162. __set_bit(timer_nr, mfgpt->avail);
  163. spin_unlock_irqrestore(&mfgpt->lock, flags);
  164. goto done;
  165. }
  166. timer->chip = mfgpt;
  167. timer->nr = timer_nr;
  168. dev_info(&mfgpt->pdev->dev, "registered timer %d\n", timer_nr);
  169. done:
  170. return timer;
  171. }
  172. EXPORT_SYMBOL_GPL(cs5535_mfgpt_alloc_timer);
  173. /*
  174. * XXX: This frees the timer memory, but never resets the actual hardware
  175. * timer. The old geode_mfgpt code did this; it would be good to figure
  176. * out a way to actually release the hardware timer. See comments below.
  177. */
  178. void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer)
  179. {
  180. unsigned long flags;
  181. uint16_t val;
  182. /* timer can be made available again only if never set up */
  183. val = cs5535_mfgpt_read(timer, MFGPT_REG_SETUP);
  184. if (!(val & MFGPT_SETUP_SETUP)) {
  185. spin_lock_irqsave(&timer->chip->lock, flags);
  186. __set_bit(timer->nr, timer->chip->avail);
  187. spin_unlock_irqrestore(&timer->chip->lock, flags);
  188. }
  189. kfree(timer);
  190. }
  191. EXPORT_SYMBOL_GPL(cs5535_mfgpt_free_timer);
  192. uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer, uint16_t reg)
  193. {
  194. return inw(timer->chip->base + reg + (timer->nr * 8));
  195. }
  196. EXPORT_SYMBOL_GPL(cs5535_mfgpt_read);
  197. void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
  198. uint16_t value)
  199. {
  200. outw(value, timer->chip->base + reg + (timer->nr * 8));
  201. }
  202. EXPORT_SYMBOL_GPL(cs5535_mfgpt_write);
  203. /*
  204. * This is a sledgehammer that resets all MFGPT timers. This is required by
  205. * some broken BIOSes which leave the system in an unstable state
  206. * (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to
  207. * whether or not this secret MSR can be used to release individual timers.
  208. * Jordan tells me that he and Mitch once played w/ it, but it's unclear
  209. * what the results of that were (and they experienced some instability).
  210. */
  211. static void reset_all_timers(void)
  212. {
  213. uint32_t val, dummy;
  214. /* The following undocumented bit resets the MFGPT timers */
  215. val = 0xFF; dummy = 0;
  216. wrmsr(MSR_MFGPT_SETUP, val, dummy);
  217. }
  218. /*
  219. * This is another sledgehammer to reset all MFGPT timers.
  220. * Instead of using the undocumented bit method it clears
  221. * IRQ, NMI and RESET settings.
  222. */
  223. static void soft_reset(void)
  224. {
  225. int i;
  226. struct cs5535_mfgpt_timer t;
  227. for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
  228. t.nr = i;
  229. cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_RESET, 0);
  230. cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_RESET, 0);
  231. cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_NMI, 0);
  232. cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_NMI, 0);
  233. cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_IRQ, 0);
  234. cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_IRQ, 0);
  235. }
  236. }
  237. /*
  238. * Check whether any MFGPTs are available for the kernel to use. In most
  239. * cases, firmware that uses AMD's VSA code will claim all timers during
  240. * bootup; we certainly don't want to take them if they're already in use.
  241. * In other cases (such as with VSAless OpenFirmware), the system firmware
  242. * leaves timers available for us to use.
  243. */
  244. static int scan_timers(struct cs5535_mfgpt_chip *mfgpt)
  245. {
  246. struct cs5535_mfgpt_timer timer = { .chip = mfgpt };
  247. unsigned long flags;
  248. int timers = 0;
  249. uint16_t val;
  250. int i;
  251. /* bios workaround */
  252. if (mfgpt_reset_timers == 1)
  253. reset_all_timers();
  254. else if (mfgpt_reset_timers == 2)
  255. soft_reset();
  256. /* just to be safe, protect this section w/ lock */
  257. spin_lock_irqsave(&mfgpt->lock, flags);
  258. for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
  259. timer.nr = i;
  260. val = cs5535_mfgpt_read(&timer, MFGPT_REG_SETUP);
  261. if (!(val & MFGPT_SETUP_SETUP) || mfgpt_reset_timers == 2) {
  262. __set_bit(i, mfgpt->avail);
  263. timers++;
  264. }
  265. }
  266. spin_unlock_irqrestore(&mfgpt->lock, flags);
  267. return timers;
  268. }
  269. static int cs5535_mfgpt_probe(struct platform_device *pdev)
  270. {
  271. struct resource *res;
  272. int err = -EIO, t;
  273. if (mfgpt_reset_timers < 0 || mfgpt_reset_timers > 2) {
  274. dev_err(&pdev->dev, "Bad mfgpt_reset_timers value: %i\n",
  275. mfgpt_reset_timers);
  276. goto done;
  277. }
  278. /* There are two ways to get the MFGPT base address; one is by
  279. * fetching it from MSR_LBAR_MFGPT, the other is by reading the
  280. * PCI BAR info. The latter method is easier (especially across
  281. * different architectures), so we'll stick with that for now. If
  282. * it turns out to be unreliable in the face of crappy BIOSes, we
  283. * can always go back to using MSRs.. */
  284. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  285. if (!res) {
  286. dev_err(&pdev->dev, "can't fetch device resource info\n");
  287. goto done;
  288. }
  289. if (!request_region(res->start, resource_size(res), pdev->name)) {
  290. dev_err(&pdev->dev, "can't request region\n");
  291. goto done;
  292. }
  293. /* set up the driver-specific struct */
  294. cs5535_mfgpt_chip.base = res->start;
  295. cs5535_mfgpt_chip.pdev = pdev;
  296. spin_lock_init(&cs5535_mfgpt_chip.lock);
  297. dev_info(&pdev->dev, "reserved resource region %pR\n", res);
  298. /* detect the available timers */
  299. t = scan_timers(&cs5535_mfgpt_chip);
  300. dev_info(&pdev->dev, "%d MFGPT timers available\n", t);
  301. cs5535_mfgpt_chip.initialized = 1;
  302. return 0;
  303. done:
  304. return err;
  305. }
  306. static struct platform_driver cs5535_mfgpt_driver = {
  307. .driver = {
  308. .name = DRV_NAME,
  309. },
  310. .probe = cs5535_mfgpt_probe,
  311. };
  312. static int __init cs5535_mfgpt_init(void)
  313. {
  314. return platform_driver_register(&cs5535_mfgpt_driver);
  315. }
  316. module_init(cs5535_mfgpt_init);
  317. MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
  318. MODULE_DESCRIPTION("CS5535/CS5536 MFGPT timer driver");
  319. MODULE_LICENSE("GPL");
  320. MODULE_ALIAS("platform:" DRV_NAME);