ad525x_dpot.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ad525x_dpot: Driver for the Analog Devices digital potentiometers
  4. * Copyright (c) 2009-2010 Analog Devices, Inc.
  5. * Author: Michael Hennerich <michael.hennerich@analog.com>
  6. *
  7. * DEVID #Wipers #Positions Resistor Options (kOhm)
  8. * AD5258 1 64 1, 10, 50, 100
  9. * AD5259 1 256 5, 10, 50, 100
  10. * AD5251 2 64 1, 10, 50, 100
  11. * AD5252 2 256 1, 10, 50, 100
  12. * AD5255 3 512 25, 250
  13. * AD5253 4 64 1, 10, 50, 100
  14. * AD5254 4 256 1, 10, 50, 100
  15. * AD5160 1 256 5, 10, 50, 100
  16. * AD5161 1 256 5, 10, 50, 100
  17. * AD5162 2 256 2.5, 10, 50, 100
  18. * AD5165 1 256 100
  19. * AD5200 1 256 10, 50
  20. * AD5201 1 33 10, 50
  21. * AD5203 4 64 10, 100
  22. * AD5204 4 256 10, 50, 100
  23. * AD5206 6 256 10, 50, 100
  24. * AD5207 2 256 10, 50, 100
  25. * AD5231 1 1024 10, 50, 100
  26. * AD5232 2 256 10, 50, 100
  27. * AD5233 4 64 10, 50, 100
  28. * AD5235 2 1024 25, 250
  29. * AD5260 1 256 20, 50, 200
  30. * AD5262 2 256 20, 50, 200
  31. * AD5263 4 256 20, 50, 200
  32. * AD5290 1 256 10, 50, 100
  33. * AD5291 1 256 20, 50, 100 (20-TP)
  34. * AD5292 1 1024 20, 50, 100 (20-TP)
  35. * AD5293 1 1024 20, 50, 100
  36. * AD7376 1 128 10, 50, 100, 1M
  37. * AD8400 1 256 1, 10, 50, 100
  38. * AD8402 2 256 1, 10, 50, 100
  39. * AD8403 4 256 1, 10, 50, 100
  40. * ADN2850 3 512 25, 250
  41. * AD5241 1 256 10, 100, 1M
  42. * AD5246 1 128 5, 10, 50, 100
  43. * AD5247 1 128 5, 10, 50, 100
  44. * AD5245 1 256 5, 10, 50, 100
  45. * AD5243 2 256 2.5, 10, 50, 100
  46. * AD5248 2 256 2.5, 10, 50, 100
  47. * AD5242 2 256 20, 50, 200
  48. * AD5280 1 256 20, 50, 200
  49. * AD5282 2 256 20, 50, 200
  50. * ADN2860 3 512 25, 250
  51. * AD5273 1 64 1, 10, 50, 100 (OTP)
  52. * AD5171 1 64 5, 10, 50, 100 (OTP)
  53. * AD5170 1 256 2.5, 10, 50, 100 (OTP)
  54. * AD5172 2 256 2.5, 10, 50, 100 (OTP)
  55. * AD5173 2 256 2.5, 10, 50, 100 (OTP)
  56. * AD5270 1 1024 20, 50, 100 (50-TP)
  57. * AD5271 1 256 20, 50, 100 (50-TP)
  58. * AD5272 1 1024 20, 50, 100 (50-TP)
  59. * AD5274 1 256 20, 50, 100 (50-TP)
  60. *
  61. * See Documentation/misc-devices/ad525x_dpot.rst for more info.
  62. *
  63. * derived from ad5258.c
  64. * Copyright (c) 2009 Cyber Switching, Inc.
  65. * Author: Chris Verges <chrisv@cyberswitching.com>
  66. *
  67. * derived from ad5252.c
  68. * Copyright (c) 2006-2011 Michael Hennerich <michael.hennerich@analog.com>
  69. */
  70. #include <linux/module.h>
  71. #include <linux/device.h>
  72. #include <linux/kernel.h>
  73. #include <linux/delay.h>
  74. #include <linux/slab.h>
  75. #include "ad525x_dpot.h"
  76. /*
  77. * Client data (each client gets its own)
  78. */
  79. struct dpot_data {
  80. struct ad_dpot_bus_data bdata;
  81. struct mutex update_lock;
  82. unsigned int rdac_mask;
  83. unsigned int max_pos;
  84. unsigned long devid;
  85. unsigned int uid;
  86. unsigned int feat;
  87. unsigned int wipers;
  88. u16 rdac_cache[MAX_RDACS];
  89. DECLARE_BITMAP(otp_en_mask, MAX_RDACS);
  90. };
  91. static inline int dpot_read_d8(struct dpot_data *dpot)
  92. {
  93. return dpot->bdata.bops->read_d8(dpot->bdata.client);
  94. }
  95. static inline int dpot_read_r8d8(struct dpot_data *dpot, u8 reg)
  96. {
  97. return dpot->bdata.bops->read_r8d8(dpot->bdata.client, reg);
  98. }
  99. static inline int dpot_read_r8d16(struct dpot_data *dpot, u8 reg)
  100. {
  101. return dpot->bdata.bops->read_r8d16(dpot->bdata.client, reg);
  102. }
  103. static inline int dpot_write_d8(struct dpot_data *dpot, u8 val)
  104. {
  105. return dpot->bdata.bops->write_d8(dpot->bdata.client, val);
  106. }
  107. static inline int dpot_write_r8d8(struct dpot_data *dpot, u8 reg, u16 val)
  108. {
  109. return dpot->bdata.bops->write_r8d8(dpot->bdata.client, reg, val);
  110. }
  111. static inline int dpot_write_r8d16(struct dpot_data *dpot, u8 reg, u16 val)
  112. {
  113. return dpot->bdata.bops->write_r8d16(dpot->bdata.client, reg, val);
  114. }
  115. static s32 dpot_read_spi(struct dpot_data *dpot, u8 reg)
  116. {
  117. unsigned int ctrl = 0;
  118. int value;
  119. if (!(reg & (DPOT_ADDR_EEPROM | DPOT_ADDR_CMD))) {
  120. if (dpot->feat & F_RDACS_WONLY)
  121. return dpot->rdac_cache[reg & DPOT_RDAC_MASK];
  122. if (dpot->uid == DPOT_UID(AD5291_ID) ||
  123. dpot->uid == DPOT_UID(AD5292_ID) ||
  124. dpot->uid == DPOT_UID(AD5293_ID)) {
  125. value = dpot_read_r8d8(dpot,
  126. DPOT_AD5291_READ_RDAC << 2);
  127. if (dpot->uid == DPOT_UID(AD5291_ID))
  128. value = value >> 2;
  129. return value;
  130. } else if (dpot->uid == DPOT_UID(AD5270_ID) ||
  131. dpot->uid == DPOT_UID(AD5271_ID)) {
  132. value = dpot_read_r8d8(dpot,
  133. DPOT_AD5270_1_2_4_READ_RDAC << 2);
  134. if (value < 0)
  135. return value;
  136. if (dpot->uid == DPOT_UID(AD5271_ID))
  137. value = value >> 2;
  138. return value;
  139. }
  140. ctrl = DPOT_SPI_READ_RDAC;
  141. } else if (reg & DPOT_ADDR_EEPROM) {
  142. ctrl = DPOT_SPI_READ_EEPROM;
  143. }
  144. if (dpot->feat & F_SPI_16BIT)
  145. return dpot_read_r8d8(dpot, ctrl);
  146. else if (dpot->feat & F_SPI_24BIT)
  147. return dpot_read_r8d16(dpot, ctrl);
  148. return -EFAULT;
  149. }
  150. static s32 dpot_read_i2c(struct dpot_data *dpot, u8 reg)
  151. {
  152. int value;
  153. unsigned int ctrl = 0;
  154. switch (dpot->uid) {
  155. case DPOT_UID(AD5246_ID):
  156. case DPOT_UID(AD5247_ID):
  157. return dpot_read_d8(dpot);
  158. case DPOT_UID(AD5245_ID):
  159. case DPOT_UID(AD5241_ID):
  160. case DPOT_UID(AD5242_ID):
  161. case DPOT_UID(AD5243_ID):
  162. case DPOT_UID(AD5248_ID):
  163. case DPOT_UID(AD5280_ID):
  164. case DPOT_UID(AD5282_ID):
  165. ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
  166. 0 : DPOT_AD5282_RDAC_AB;
  167. return dpot_read_r8d8(dpot, ctrl);
  168. case DPOT_UID(AD5170_ID):
  169. case DPOT_UID(AD5171_ID):
  170. case DPOT_UID(AD5273_ID):
  171. return dpot_read_d8(dpot);
  172. case DPOT_UID(AD5172_ID):
  173. case DPOT_UID(AD5173_ID):
  174. ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
  175. 0 : DPOT_AD5172_3_A0;
  176. return dpot_read_r8d8(dpot, ctrl);
  177. case DPOT_UID(AD5272_ID):
  178. case DPOT_UID(AD5274_ID):
  179. dpot_write_r8d8(dpot,
  180. (DPOT_AD5270_1_2_4_READ_RDAC << 2), 0);
  181. value = dpot_read_r8d16(dpot, DPOT_AD5270_1_2_4_RDAC << 2);
  182. if (value < 0)
  183. return value;
  184. /*
  185. * AD5272/AD5274 returns high byte first, however
  186. * underling smbus expects low byte first.
  187. */
  188. value = swab16(value);
  189. if (dpot->uid == DPOT_UID(AD5274_ID))
  190. value = value >> 2;
  191. return value;
  192. default:
  193. if ((reg & DPOT_REG_TOL) || (dpot->max_pos > 256))
  194. return dpot_read_r8d16(dpot, (reg & 0xF8) |
  195. ((reg & 0x7) << 1));
  196. else
  197. return dpot_read_r8d8(dpot, reg);
  198. }
  199. }
  200. static s32 dpot_read(struct dpot_data *dpot, u8 reg)
  201. {
  202. if (dpot->feat & F_SPI)
  203. return dpot_read_spi(dpot, reg);
  204. else
  205. return dpot_read_i2c(dpot, reg);
  206. }
  207. static s32 dpot_write_spi(struct dpot_data *dpot, u8 reg, u16 value)
  208. {
  209. unsigned int val = 0;
  210. if (!(reg & (DPOT_ADDR_EEPROM | DPOT_ADDR_CMD | DPOT_ADDR_OTP))) {
  211. if (dpot->feat & F_RDACS_WONLY)
  212. dpot->rdac_cache[reg & DPOT_RDAC_MASK] = value;
  213. if (dpot->feat & F_AD_APPDATA) {
  214. if (dpot->feat & F_SPI_8BIT) {
  215. val = ((reg & DPOT_RDAC_MASK) <<
  216. DPOT_MAX_POS(dpot->devid)) |
  217. value;
  218. return dpot_write_d8(dpot, val);
  219. } else if (dpot->feat & F_SPI_16BIT) {
  220. val = ((reg & DPOT_RDAC_MASK) <<
  221. DPOT_MAX_POS(dpot->devid)) |
  222. value;
  223. return dpot_write_r8d8(dpot, val >> 8,
  224. val & 0xFF);
  225. } else
  226. BUG();
  227. } else {
  228. if (dpot->uid == DPOT_UID(AD5291_ID) ||
  229. dpot->uid == DPOT_UID(AD5292_ID) ||
  230. dpot->uid == DPOT_UID(AD5293_ID)) {
  231. dpot_write_r8d8(dpot, DPOT_AD5291_CTRLREG << 2,
  232. DPOT_AD5291_UNLOCK_CMD);
  233. if (dpot->uid == DPOT_UID(AD5291_ID))
  234. value = value << 2;
  235. return dpot_write_r8d8(dpot,
  236. (DPOT_AD5291_RDAC << 2) |
  237. (value >> 8), value & 0xFF);
  238. } else if (dpot->uid == DPOT_UID(AD5270_ID) ||
  239. dpot->uid == DPOT_UID(AD5271_ID)) {
  240. dpot_write_r8d8(dpot,
  241. DPOT_AD5270_1_2_4_CTRLREG << 2,
  242. DPOT_AD5270_1_2_4_UNLOCK_CMD);
  243. if (dpot->uid == DPOT_UID(AD5271_ID))
  244. value = value << 2;
  245. return dpot_write_r8d8(dpot,
  246. (DPOT_AD5270_1_2_4_RDAC << 2) |
  247. (value >> 8), value & 0xFF);
  248. }
  249. val = DPOT_SPI_RDAC | (reg & DPOT_RDAC_MASK);
  250. }
  251. } else if (reg & DPOT_ADDR_EEPROM) {
  252. val = DPOT_SPI_EEPROM | (reg & DPOT_RDAC_MASK);
  253. } else if (reg & DPOT_ADDR_CMD) {
  254. switch (reg) {
  255. case DPOT_DEC_ALL_6DB:
  256. val = DPOT_SPI_DEC_ALL_6DB;
  257. break;
  258. case DPOT_INC_ALL_6DB:
  259. val = DPOT_SPI_INC_ALL_6DB;
  260. break;
  261. case DPOT_DEC_ALL:
  262. val = DPOT_SPI_DEC_ALL;
  263. break;
  264. case DPOT_INC_ALL:
  265. val = DPOT_SPI_INC_ALL;
  266. break;
  267. }
  268. } else if (reg & DPOT_ADDR_OTP) {
  269. if (dpot->uid == DPOT_UID(AD5291_ID) ||
  270. dpot->uid == DPOT_UID(AD5292_ID)) {
  271. return dpot_write_r8d8(dpot,
  272. DPOT_AD5291_STORE_XTPM << 2, 0);
  273. } else if (dpot->uid == DPOT_UID(AD5270_ID) ||
  274. dpot->uid == DPOT_UID(AD5271_ID)) {
  275. return dpot_write_r8d8(dpot,
  276. DPOT_AD5270_1_2_4_STORE_XTPM << 2, 0);
  277. }
  278. } else
  279. BUG();
  280. if (dpot->feat & F_SPI_16BIT)
  281. return dpot_write_r8d8(dpot, val, value);
  282. else if (dpot->feat & F_SPI_24BIT)
  283. return dpot_write_r8d16(dpot, val, value);
  284. return -EFAULT;
  285. }
  286. static s32 dpot_write_i2c(struct dpot_data *dpot, u8 reg, u16 value)
  287. {
  288. /* Only write the instruction byte for certain commands */
  289. unsigned int tmp = 0, ctrl = 0;
  290. switch (dpot->uid) {
  291. case DPOT_UID(AD5246_ID):
  292. case DPOT_UID(AD5247_ID):
  293. return dpot_write_d8(dpot, value);
  294. case DPOT_UID(AD5245_ID):
  295. case DPOT_UID(AD5241_ID):
  296. case DPOT_UID(AD5242_ID):
  297. case DPOT_UID(AD5243_ID):
  298. case DPOT_UID(AD5248_ID):
  299. case DPOT_UID(AD5280_ID):
  300. case DPOT_UID(AD5282_ID):
  301. ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
  302. 0 : DPOT_AD5282_RDAC_AB;
  303. return dpot_write_r8d8(dpot, ctrl, value);
  304. case DPOT_UID(AD5171_ID):
  305. case DPOT_UID(AD5273_ID):
  306. if (reg & DPOT_ADDR_OTP) {
  307. tmp = dpot_read_d8(dpot);
  308. if (tmp >> 6) /* Ready to Program? */
  309. return -EFAULT;
  310. ctrl = DPOT_AD5273_FUSE;
  311. }
  312. return dpot_write_r8d8(dpot, ctrl, value);
  313. case DPOT_UID(AD5172_ID):
  314. case DPOT_UID(AD5173_ID):
  315. ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
  316. 0 : DPOT_AD5172_3_A0;
  317. if (reg & DPOT_ADDR_OTP) {
  318. tmp = dpot_read_r8d16(dpot, ctrl);
  319. if (tmp >> 14) /* Ready to Program? */
  320. return -EFAULT;
  321. ctrl |= DPOT_AD5170_2_3_FUSE;
  322. }
  323. return dpot_write_r8d8(dpot, ctrl, value);
  324. case DPOT_UID(AD5170_ID):
  325. if (reg & DPOT_ADDR_OTP) {
  326. tmp = dpot_read_r8d16(dpot, tmp);
  327. if (tmp >> 14) /* Ready to Program? */
  328. return -EFAULT;
  329. ctrl = DPOT_AD5170_2_3_FUSE;
  330. }
  331. return dpot_write_r8d8(dpot, ctrl, value);
  332. case DPOT_UID(AD5272_ID):
  333. case DPOT_UID(AD5274_ID):
  334. dpot_write_r8d8(dpot, DPOT_AD5270_1_2_4_CTRLREG << 2,
  335. DPOT_AD5270_1_2_4_UNLOCK_CMD);
  336. if (reg & DPOT_ADDR_OTP)
  337. return dpot_write_r8d8(dpot,
  338. DPOT_AD5270_1_2_4_STORE_XTPM << 2, 0);
  339. if (dpot->uid == DPOT_UID(AD5274_ID))
  340. value = value << 2;
  341. return dpot_write_r8d8(dpot, (DPOT_AD5270_1_2_4_RDAC << 2) |
  342. (value >> 8), value & 0xFF);
  343. default:
  344. if (reg & DPOT_ADDR_CMD)
  345. return dpot_write_d8(dpot, reg);
  346. if (dpot->max_pos > 256)
  347. return dpot_write_r8d16(dpot, (reg & 0xF8) |
  348. ((reg & 0x7) << 1), value);
  349. else
  350. /* All other registers require instruction + data bytes */
  351. return dpot_write_r8d8(dpot, reg, value);
  352. }
  353. }
  354. static s32 dpot_write(struct dpot_data *dpot, u8 reg, u16 value)
  355. {
  356. if (dpot->feat & F_SPI)
  357. return dpot_write_spi(dpot, reg, value);
  358. else
  359. return dpot_write_i2c(dpot, reg, value);
  360. }
  361. /* sysfs functions */
  362. static ssize_t sysfs_show_reg(struct device *dev,
  363. struct device_attribute *attr,
  364. char *buf, u32 reg)
  365. {
  366. struct dpot_data *data = dev_get_drvdata(dev);
  367. s32 value;
  368. if (reg & DPOT_ADDR_OTP_EN)
  369. return sprintf(buf, "%s\n",
  370. test_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask) ?
  371. "enabled" : "disabled");
  372. mutex_lock(&data->update_lock);
  373. value = dpot_read(data, reg);
  374. mutex_unlock(&data->update_lock);
  375. if (value < 0)
  376. return -EINVAL;
  377. /*
  378. * Let someone else deal with converting this ...
  379. * the tolerance is a two-byte value where the MSB
  380. * is a sign + integer value, and the LSB is a
  381. * decimal value. See page 18 of the AD5258
  382. * datasheet (Rev. A) for more details.
  383. */
  384. if (reg & DPOT_REG_TOL)
  385. return sprintf(buf, "0x%04x\n", value & 0xFFFF);
  386. else
  387. return sprintf(buf, "%u\n", value & data->rdac_mask);
  388. }
  389. static ssize_t sysfs_set_reg(struct device *dev,
  390. struct device_attribute *attr,
  391. const char *buf, size_t count, u32 reg)
  392. {
  393. struct dpot_data *data = dev_get_drvdata(dev);
  394. unsigned long value;
  395. int err;
  396. if (reg & DPOT_ADDR_OTP_EN) {
  397. if (sysfs_streq(buf, "enabled"))
  398. set_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask);
  399. else
  400. clear_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask);
  401. return count;
  402. }
  403. if ((reg & DPOT_ADDR_OTP) &&
  404. !test_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask))
  405. return -EPERM;
  406. err = kstrtoul(buf, 10, &value);
  407. if (err)
  408. return err;
  409. if (value > data->rdac_mask)
  410. value = data->rdac_mask;
  411. mutex_lock(&data->update_lock);
  412. dpot_write(data, reg, value);
  413. if (reg & DPOT_ADDR_EEPROM)
  414. msleep(26); /* Sleep while the EEPROM updates */
  415. else if (reg & DPOT_ADDR_OTP)
  416. msleep(400); /* Sleep while the OTP updates */
  417. mutex_unlock(&data->update_lock);
  418. return count;
  419. }
  420. static ssize_t sysfs_do_cmd(struct device *dev,
  421. struct device_attribute *attr,
  422. const char *buf, size_t count, u32 reg)
  423. {
  424. struct dpot_data *data = dev_get_drvdata(dev);
  425. mutex_lock(&data->update_lock);
  426. dpot_write(data, reg, 0);
  427. mutex_unlock(&data->update_lock);
  428. return count;
  429. }
  430. /* ------------------------------------------------------------------------- */
  431. #define DPOT_DEVICE_SHOW(_name, _reg) static ssize_t \
  432. show_##_name(struct device *dev, \
  433. struct device_attribute *attr, char *buf) \
  434. { \
  435. return sysfs_show_reg(dev, attr, buf, _reg); \
  436. }
  437. #define DPOT_DEVICE_SET(_name, _reg) static ssize_t \
  438. set_##_name(struct device *dev, \
  439. struct device_attribute *attr, \
  440. const char *buf, size_t count) \
  441. { \
  442. return sysfs_set_reg(dev, attr, buf, count, _reg); \
  443. }
  444. #define DPOT_DEVICE_SHOW_SET(name, reg) \
  445. DPOT_DEVICE_SHOW(name, reg) \
  446. DPOT_DEVICE_SET(name, reg) \
  447. static DEVICE_ATTR(name, S_IWUSR | S_IRUGO, show_##name, set_##name)
  448. #define DPOT_DEVICE_SHOW_ONLY(name, reg) \
  449. DPOT_DEVICE_SHOW(name, reg) \
  450. static DEVICE_ATTR(name, S_IWUSR | S_IRUGO, show_##name, NULL)
  451. DPOT_DEVICE_SHOW_SET(rdac0, DPOT_ADDR_RDAC | DPOT_RDAC0);
  452. DPOT_DEVICE_SHOW_SET(eeprom0, DPOT_ADDR_EEPROM | DPOT_RDAC0);
  453. DPOT_DEVICE_SHOW_ONLY(tolerance0, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC0);
  454. DPOT_DEVICE_SHOW_SET(otp0, DPOT_ADDR_OTP | DPOT_RDAC0);
  455. DPOT_DEVICE_SHOW_SET(otp0en, DPOT_ADDR_OTP_EN | DPOT_RDAC0);
  456. DPOT_DEVICE_SHOW_SET(rdac1, DPOT_ADDR_RDAC | DPOT_RDAC1);
  457. DPOT_DEVICE_SHOW_SET(eeprom1, DPOT_ADDR_EEPROM | DPOT_RDAC1);
  458. DPOT_DEVICE_SHOW_ONLY(tolerance1, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC1);
  459. DPOT_DEVICE_SHOW_SET(otp1, DPOT_ADDR_OTP | DPOT_RDAC1);
  460. DPOT_DEVICE_SHOW_SET(otp1en, DPOT_ADDR_OTP_EN | DPOT_RDAC1);
  461. DPOT_DEVICE_SHOW_SET(rdac2, DPOT_ADDR_RDAC | DPOT_RDAC2);
  462. DPOT_DEVICE_SHOW_SET(eeprom2, DPOT_ADDR_EEPROM | DPOT_RDAC2);
  463. DPOT_DEVICE_SHOW_ONLY(tolerance2, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC2);
  464. DPOT_DEVICE_SHOW_SET(otp2, DPOT_ADDR_OTP | DPOT_RDAC2);
  465. DPOT_DEVICE_SHOW_SET(otp2en, DPOT_ADDR_OTP_EN | DPOT_RDAC2);
  466. DPOT_DEVICE_SHOW_SET(rdac3, DPOT_ADDR_RDAC | DPOT_RDAC3);
  467. DPOT_DEVICE_SHOW_SET(eeprom3, DPOT_ADDR_EEPROM | DPOT_RDAC3);
  468. DPOT_DEVICE_SHOW_ONLY(tolerance3, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC3);
  469. DPOT_DEVICE_SHOW_SET(otp3, DPOT_ADDR_OTP | DPOT_RDAC3);
  470. DPOT_DEVICE_SHOW_SET(otp3en, DPOT_ADDR_OTP_EN | DPOT_RDAC3);
  471. DPOT_DEVICE_SHOW_SET(rdac4, DPOT_ADDR_RDAC | DPOT_RDAC4);
  472. DPOT_DEVICE_SHOW_SET(eeprom4, DPOT_ADDR_EEPROM | DPOT_RDAC4);
  473. DPOT_DEVICE_SHOW_ONLY(tolerance4, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC4);
  474. DPOT_DEVICE_SHOW_SET(otp4, DPOT_ADDR_OTP | DPOT_RDAC4);
  475. DPOT_DEVICE_SHOW_SET(otp4en, DPOT_ADDR_OTP_EN | DPOT_RDAC4);
  476. DPOT_DEVICE_SHOW_SET(rdac5, DPOT_ADDR_RDAC | DPOT_RDAC5);
  477. DPOT_DEVICE_SHOW_SET(eeprom5, DPOT_ADDR_EEPROM | DPOT_RDAC5);
  478. DPOT_DEVICE_SHOW_ONLY(tolerance5, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC5);
  479. DPOT_DEVICE_SHOW_SET(otp5, DPOT_ADDR_OTP | DPOT_RDAC5);
  480. DPOT_DEVICE_SHOW_SET(otp5en, DPOT_ADDR_OTP_EN | DPOT_RDAC5);
  481. static const struct attribute *dpot_attrib_wipers[] = {
  482. &dev_attr_rdac0.attr,
  483. &dev_attr_rdac1.attr,
  484. &dev_attr_rdac2.attr,
  485. &dev_attr_rdac3.attr,
  486. &dev_attr_rdac4.attr,
  487. &dev_attr_rdac5.attr,
  488. NULL
  489. };
  490. static const struct attribute *dpot_attrib_eeprom[] = {
  491. &dev_attr_eeprom0.attr,
  492. &dev_attr_eeprom1.attr,
  493. &dev_attr_eeprom2.attr,
  494. &dev_attr_eeprom3.attr,
  495. &dev_attr_eeprom4.attr,
  496. &dev_attr_eeprom5.attr,
  497. NULL
  498. };
  499. static const struct attribute *dpot_attrib_otp[] = {
  500. &dev_attr_otp0.attr,
  501. &dev_attr_otp1.attr,
  502. &dev_attr_otp2.attr,
  503. &dev_attr_otp3.attr,
  504. &dev_attr_otp4.attr,
  505. &dev_attr_otp5.attr,
  506. NULL
  507. };
  508. static const struct attribute *dpot_attrib_otp_en[] = {
  509. &dev_attr_otp0en.attr,
  510. &dev_attr_otp1en.attr,
  511. &dev_attr_otp2en.attr,
  512. &dev_attr_otp3en.attr,
  513. &dev_attr_otp4en.attr,
  514. &dev_attr_otp5en.attr,
  515. NULL
  516. };
  517. static const struct attribute *dpot_attrib_tolerance[] = {
  518. &dev_attr_tolerance0.attr,
  519. &dev_attr_tolerance1.attr,
  520. &dev_attr_tolerance2.attr,
  521. &dev_attr_tolerance3.attr,
  522. &dev_attr_tolerance4.attr,
  523. &dev_attr_tolerance5.attr,
  524. NULL
  525. };
  526. /* ------------------------------------------------------------------------- */
  527. #define DPOT_DEVICE_DO_CMD(_name, _cmd) static ssize_t \
  528. set_##_name(struct device *dev, \
  529. struct device_attribute *attr, \
  530. const char *buf, size_t count) \
  531. { \
  532. return sysfs_do_cmd(dev, attr, buf, count, _cmd); \
  533. } \
  534. static DEVICE_ATTR(_name, S_IWUSR | S_IRUGO, NULL, set_##_name)
  535. DPOT_DEVICE_DO_CMD(inc_all, DPOT_INC_ALL);
  536. DPOT_DEVICE_DO_CMD(dec_all, DPOT_DEC_ALL);
  537. DPOT_DEVICE_DO_CMD(inc_all_6db, DPOT_INC_ALL_6DB);
  538. DPOT_DEVICE_DO_CMD(dec_all_6db, DPOT_DEC_ALL_6DB);
  539. static struct attribute *ad525x_attributes_commands[] = {
  540. &dev_attr_inc_all.attr,
  541. &dev_attr_dec_all.attr,
  542. &dev_attr_inc_all_6db.attr,
  543. &dev_attr_dec_all_6db.attr,
  544. NULL
  545. };
  546. static const struct attribute_group ad525x_group_commands = {
  547. .attrs = ad525x_attributes_commands,
  548. };
  549. static int ad_dpot_add_files(struct device *dev,
  550. unsigned int features, unsigned int rdac)
  551. {
  552. int err = sysfs_create_file(&dev->kobj,
  553. dpot_attrib_wipers[rdac]);
  554. if (features & F_CMD_EEP)
  555. err |= sysfs_create_file(&dev->kobj,
  556. dpot_attrib_eeprom[rdac]);
  557. if (features & F_CMD_TOL)
  558. err |= sysfs_create_file(&dev->kobj,
  559. dpot_attrib_tolerance[rdac]);
  560. if (features & F_CMD_OTP) {
  561. err |= sysfs_create_file(&dev->kobj,
  562. dpot_attrib_otp_en[rdac]);
  563. err |= sysfs_create_file(&dev->kobj,
  564. dpot_attrib_otp[rdac]);
  565. }
  566. if (err)
  567. dev_err(dev, "failed to register sysfs hooks for RDAC%d\n",
  568. rdac);
  569. return err;
  570. }
  571. static inline void ad_dpot_remove_files(struct device *dev,
  572. unsigned int features, unsigned int rdac)
  573. {
  574. sysfs_remove_file(&dev->kobj,
  575. dpot_attrib_wipers[rdac]);
  576. if (features & F_CMD_EEP)
  577. sysfs_remove_file(&dev->kobj,
  578. dpot_attrib_eeprom[rdac]);
  579. if (features & F_CMD_TOL)
  580. sysfs_remove_file(&dev->kobj,
  581. dpot_attrib_tolerance[rdac]);
  582. if (features & F_CMD_OTP) {
  583. sysfs_remove_file(&dev->kobj,
  584. dpot_attrib_otp_en[rdac]);
  585. sysfs_remove_file(&dev->kobj,
  586. dpot_attrib_otp[rdac]);
  587. }
  588. }
  589. int ad_dpot_probe(struct device *dev,
  590. struct ad_dpot_bus_data *bdata, unsigned long devid,
  591. const char *name)
  592. {
  593. struct dpot_data *data;
  594. int i, err = 0;
  595. data = kzalloc(sizeof(struct dpot_data), GFP_KERNEL);
  596. if (!data) {
  597. err = -ENOMEM;
  598. goto exit;
  599. }
  600. dev_set_drvdata(dev, data);
  601. mutex_init(&data->update_lock);
  602. data->bdata = *bdata;
  603. data->devid = devid;
  604. data->max_pos = 1 << DPOT_MAX_POS(devid);
  605. data->rdac_mask = data->max_pos - 1;
  606. data->feat = DPOT_FEAT(devid);
  607. data->uid = DPOT_UID(devid);
  608. data->wipers = DPOT_WIPERS(devid);
  609. for (i = DPOT_RDAC0; i < MAX_RDACS; i++)
  610. if (data->wipers & (1 << i)) {
  611. err = ad_dpot_add_files(dev, data->feat, i);
  612. if (err)
  613. goto exit_remove_files;
  614. /* power-up midscale */
  615. if (data->feat & F_RDACS_WONLY)
  616. data->rdac_cache[i] = data->max_pos / 2;
  617. }
  618. if (data->feat & F_CMD_INC)
  619. err = sysfs_create_group(&dev->kobj, &ad525x_group_commands);
  620. if (err) {
  621. dev_err(dev, "failed to register sysfs hooks\n");
  622. goto exit_free;
  623. }
  624. dev_info(dev, "%s %d-Position Digital Potentiometer registered\n",
  625. name, data->max_pos);
  626. return 0;
  627. exit_remove_files:
  628. for (i = DPOT_RDAC0; i < MAX_RDACS; i++)
  629. if (data->wipers & (1 << i))
  630. ad_dpot_remove_files(dev, data->feat, i);
  631. exit_free:
  632. kfree(data);
  633. dev_set_drvdata(dev, NULL);
  634. exit:
  635. dev_err(dev, "failed to create client for %s ID 0x%lX\n",
  636. name, devid);
  637. return err;
  638. }
  639. EXPORT_SYMBOL(ad_dpot_probe);
  640. int ad_dpot_remove(struct device *dev)
  641. {
  642. struct dpot_data *data = dev_get_drvdata(dev);
  643. int i;
  644. for (i = DPOT_RDAC0; i < MAX_RDACS; i++)
  645. if (data->wipers & (1 << i))
  646. ad_dpot_remove_files(dev, data->feat, i);
  647. kfree(data);
  648. return 0;
  649. }
  650. EXPORT_SYMBOL(ad_dpot_remove);
  651. MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>, "
  652. "Michael Hennerich <michael.hennerich@analog.com>");
  653. MODULE_DESCRIPTION("Digital potentiometer driver");
  654. MODULE_LICENSE("GPL");