ti-emif-sram-pm.S 11 KB

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  1. /*
  2. * Low level PM code for TI EMIF
  3. *
  4. * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
  5. * Dave Gerlach
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/linkage.h>
  17. #include <asm/assembler.h>
  18. #include <asm/memory.h>
  19. #include "emif.h"
  20. #include "ti-emif-asm-offsets.h"
  21. #define EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES 0x00a0
  22. #define EMIF_POWER_MGMT_SR_TIMER_MASK 0x00f0
  23. #define EMIF_POWER_MGMT_SELF_REFRESH_MODE 0x0200
  24. #define EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK 0x0700
  25. #define EMIF_SDCFG_TYPE_DDR2 0x2 << SDRAM_TYPE_SHIFT
  26. #define EMIF_SDCFG_TYPE_DDR3 0x3 << SDRAM_TYPE_SHIFT
  27. #define EMIF_STATUS_READY 0x4
  28. #define AM43XX_EMIF_PHY_CTRL_REG_COUNT 0x120
  29. #define EMIF_AM437X_REGISTERS 0x1
  30. .arm
  31. .align 3
  32. ENTRY(ti_emif_sram)
  33. /*
  34. * void ti_emif_save_context(void)
  35. *
  36. * Used during suspend to save the context of all required EMIF registers
  37. * to local memory if the EMIF is going to lose context during the sleep
  38. * transition. Operates on the VIRTUAL address of the EMIF.
  39. */
  40. ENTRY(ti_emif_save_context)
  41. stmfd sp!, {r4 - r11, lr} @ save registers on stack
  42. adr r4, ti_emif_pm_sram_data
  43. ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
  44. ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
  45. /* Save EMIF configuration */
  46. ldr r1, [r0, #EMIF_SDRAM_CONFIG]
  47. str r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
  48. ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
  49. str r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
  50. ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
  51. str r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
  52. ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
  53. str r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
  54. ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
  55. str r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
  56. ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
  57. str r1, [r2, #EMIF_PMCR_VAL_OFFSET]
  58. ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
  59. str r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
  60. ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
  61. str r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
  62. ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
  63. str r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
  64. ldr r1, [r0, #EMIF_COS_CONFIG]
  65. str r1, [r2, #EMIF_COS_CONFIG_OFFSET]
  66. ldr r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
  67. str r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
  68. ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
  69. str r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
  70. ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
  71. str r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
  72. ldr r1, [r0, #EMIF_OCP_CONFIG]
  73. str r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
  74. ldr r5, [r4, #EMIF_PM_CONFIG_OFFSET]
  75. cmp r5, #EMIF_SRAM_AM43_REG_LAYOUT
  76. bne emif_skip_save_extra_regs
  77. ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
  78. str r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
  79. ldr r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
  80. str r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
  81. ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
  82. str r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
  83. ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
  84. str r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
  85. ldr r1, [r0, #EMIF_DLL_CALIB_CTRL]
  86. str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
  87. ldr r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
  88. str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
  89. /* Loop and save entire block of emif phy regs */
  90. mov r5, #0x0
  91. add r4, r2, #EMIF_EXT_PHY_CTRL_VALS_OFFSET
  92. add r3, r0, #EMIF_EXT_PHY_CTRL_1
  93. ddr_phy_ctrl_save:
  94. ldr r1, [r3, r5]
  95. str r1, [r4, r5]
  96. add r5, r5, #0x4
  97. cmp r5, #AM43XX_EMIF_PHY_CTRL_REG_COUNT
  98. bne ddr_phy_ctrl_save
  99. emif_skip_save_extra_regs:
  100. ldmfd sp!, {r4 - r11, pc} @ restore regs and return
  101. ENDPROC(ti_emif_save_context)
  102. /*
  103. * void ti_emif_restore_context(void)
  104. *
  105. * Used during resume to restore the context of all required EMIF registers
  106. * from local memory after the EMIF has lost context during a sleep transition.
  107. * Operates on the PHYSICAL address of the EMIF.
  108. */
  109. ENTRY(ti_emif_restore_context)
  110. adr r4, ti_emif_pm_sram_data
  111. ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
  112. ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
  113. /* Config EMIF Timings */
  114. ldr r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
  115. str r1, [r0, #EMIF_DDR_PHY_CTRL_1]
  116. str r1, [r0, #EMIF_DDR_PHY_CTRL_1_SHDW]
  117. ldr r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
  118. str r1, [r0, #EMIF_SDRAM_TIMING_1]
  119. str r1, [r0, #EMIF_SDRAM_TIMING_1_SHDW]
  120. ldr r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
  121. str r1, [r0, #EMIF_SDRAM_TIMING_2]
  122. str r1, [r0, #EMIF_SDRAM_TIMING_2_SHDW]
  123. ldr r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
  124. str r1, [r0, #EMIF_SDRAM_TIMING_3]
  125. str r1, [r0, #EMIF_SDRAM_TIMING_3_SHDW]
  126. ldr r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
  127. str r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
  128. str r1, [r0, #EMIF_SDRAM_REFRESH_CTRL_SHDW]
  129. ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
  130. str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
  131. ldr r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
  132. str r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
  133. ldr r1, [r2, #EMIF_COS_CONFIG_OFFSET]
  134. str r1, [r0, #EMIF_COS_CONFIG]
  135. ldr r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
  136. str r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
  137. ldr r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
  138. str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
  139. ldr r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
  140. str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
  141. ldr r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
  142. str r1, [r0, #EMIF_OCP_CONFIG]
  143. ldr r5, [r4, #EMIF_PM_CONFIG_OFFSET]
  144. cmp r5, #EMIF_SRAM_AM43_REG_LAYOUT
  145. bne emif_skip_restore_extra_regs
  146. ldr r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
  147. str r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
  148. ldr r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
  149. str r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
  150. ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
  151. str r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
  152. ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
  153. str r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
  154. ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
  155. str r1, [r0, #EMIF_DLL_CALIB_CTRL]
  156. ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
  157. str r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
  158. ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
  159. str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
  160. /* Loop and restore entire block of emif phy regs */
  161. mov r5, #0x0
  162. /* Load ti_emif_regs_amx3 + EMIF_EXT_PHY_CTRL_VALS_OFFSET for address
  163. * to phy register save space
  164. */
  165. add r3, r2, #EMIF_EXT_PHY_CTRL_VALS_OFFSET
  166. add r4, r0, #EMIF_EXT_PHY_CTRL_1
  167. ddr_phy_ctrl_restore:
  168. ldr r1, [r3, r5]
  169. str r1, [r4, r5]
  170. add r5, r5, #0x4
  171. cmp r5, #AM43XX_EMIF_PHY_CTRL_REG_COUNT
  172. bne ddr_phy_ctrl_restore
  173. emif_skip_restore_extra_regs:
  174. /*
  175. * Output impedence calib needed only for DDR3
  176. * but since the initial state of this will be
  177. * disabled for DDR2 no harm in restoring the
  178. * old configuration
  179. */
  180. ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
  181. str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
  182. /* Write to sdcfg last for DDR2 only */
  183. ldr r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
  184. and r2, r1, #SDRAM_TYPE_MASK
  185. cmp r2, #EMIF_SDCFG_TYPE_DDR2
  186. streq r1, [r0, #EMIF_SDRAM_CONFIG]
  187. mov pc, lr
  188. ENDPROC(ti_emif_restore_context)
  189. /*
  190. * void ti_emif_run_hw_leveling(void)
  191. *
  192. * Used during resume to run hardware leveling again and restore the
  193. * configuration of the EMIF PHY, only for DDR3.
  194. */
  195. ENTRY(ti_emif_run_hw_leveling)
  196. adr r4, ti_emif_pm_sram_data
  197. ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
  198. ldr r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
  199. orr r3, r3, #RDWRLVLFULL_START
  200. ldr r2, [r0, #EMIF_SDRAM_CONFIG]
  201. and r2, r2, #SDRAM_TYPE_MASK
  202. cmp r2, #EMIF_SDCFG_TYPE_DDR3
  203. bne skip_hwlvl
  204. str r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
  205. /*
  206. * If EMIF registers are touched during initial stage of HW
  207. * leveling sequence there will be an L3 NOC timeout error issued
  208. * as the EMIF will not respond, which is not fatal, but it is
  209. * avoidable. This small wait loop is enough time for this condition
  210. * to clear, even at worst case of CPU running at max speed of 1Ghz.
  211. */
  212. mov r2, #0x2000
  213. 1:
  214. subs r2, r2, #0x1
  215. bne 1b
  216. /* Bit clears when operation is complete */
  217. 2: ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
  218. tst r1, #RDWRLVLFULL_START
  219. bne 2b
  220. skip_hwlvl:
  221. mov pc, lr
  222. ENDPROC(ti_emif_run_hw_leveling)
  223. /*
  224. * void ti_emif_enter_sr(void)
  225. *
  226. * Programs the EMIF to tell the SDRAM to enter into self-refresh
  227. * mode during a sleep transition. Operates on the VIRTUAL address
  228. * of the EMIF.
  229. */
  230. ENTRY(ti_emif_enter_sr)
  231. stmfd sp!, {r4 - r11, lr} @ save registers on stack
  232. adr r4, ti_emif_pm_sram_data
  233. ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
  234. ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
  235. ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
  236. bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
  237. orr r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
  238. str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
  239. ldmfd sp!, {r4 - r11, pc} @ restore regs and return
  240. ENDPROC(ti_emif_enter_sr)
  241. /*
  242. * void ti_emif_exit_sr(void)
  243. *
  244. * Programs the EMIF to tell the SDRAM to exit self-refresh mode
  245. * after a sleep transition. Operates on the PHYSICAL address of
  246. * the EMIF.
  247. */
  248. ENTRY(ti_emif_exit_sr)
  249. adr r4, ti_emif_pm_sram_data
  250. ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
  251. ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
  252. /*
  253. * Toggle EMIF to exit refresh mode:
  254. * if EMIF lost context, PWR_MGT_CTRL is currently 0, writing disable
  255. * (0x0), wont do diddly squat! so do a toggle from SR(0x2) to disable
  256. * (0x0) here.
  257. * *If* EMIF did not lose context, nothing broken as we write the same
  258. * value(0x2) to reg before we write a disable (0x0).
  259. */
  260. ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
  261. bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
  262. orr r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
  263. str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
  264. bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
  265. str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
  266. /* Wait for EMIF to become ready */
  267. 1: ldr r1, [r0, #EMIF_STATUS]
  268. tst r1, #EMIF_STATUS_READY
  269. beq 1b
  270. mov pc, lr
  271. ENDPROC(ti_emif_exit_sr)
  272. /*
  273. * void ti_emif_abort_sr(void)
  274. *
  275. * Disables self-refresh after a failed transition to a low-power
  276. * state so the kernel can jump back to DDR and follow abort path.
  277. * Operates on the VIRTUAL address of the EMIF.
  278. */
  279. ENTRY(ti_emif_abort_sr)
  280. stmfd sp!, {r4 - r11, lr} @ save registers on stack
  281. adr r4, ti_emif_pm_sram_data
  282. ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
  283. ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
  284. ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
  285. bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
  286. str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
  287. /* Wait for EMIF to become ready */
  288. 1: ldr r1, [r0, #EMIF_STATUS]
  289. tst r1, #EMIF_STATUS_READY
  290. beq 1b
  291. ldmfd sp!, {r4 - r11, pc} @ restore regs and return
  292. ENDPROC(ti_emif_abort_sr)
  293. .align 3
  294. ENTRY(ti_emif_pm_sram_data)
  295. .space EMIF_PM_DATA_SIZE
  296. ENTRY(ti_emif_sram_sz)
  297. .word . - ti_emif_save_context