stm32-fmc2-ebi.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics 2020
  4. */
  5. #include <linux/bitfield.h>
  6. #include <linux/clk.h>
  7. #include <linux/mfd/syscon.h>
  8. #include <linux/module.h>
  9. #include <linux/of_platform.h>
  10. #include <linux/pinctrl/consumer.h>
  11. #include <linux/regmap.h>
  12. #include <linux/reset.h>
  13. /* FMC2 Controller Registers */
  14. #define FMC2_BCR1 0x0
  15. #define FMC2_BTR1 0x4
  16. #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1)
  17. #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1)
  18. #define FMC2_PCSCNTR 0x20
  19. #define FMC2_BWTR1 0x104
  20. #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1)
  21. /* Register: FMC2_BCR1 */
  22. #define FMC2_BCR1_CCLKEN BIT(20)
  23. #define FMC2_BCR1_FMC2EN BIT(31)
  24. /* Register: FMC2_BCRx */
  25. #define FMC2_BCR_MBKEN BIT(0)
  26. #define FMC2_BCR_MUXEN BIT(1)
  27. #define FMC2_BCR_MTYP GENMASK(3, 2)
  28. #define FMC2_BCR_MWID GENMASK(5, 4)
  29. #define FMC2_BCR_FACCEN BIT(6)
  30. #define FMC2_BCR_BURSTEN BIT(8)
  31. #define FMC2_BCR_WAITPOL BIT(9)
  32. #define FMC2_BCR_WAITCFG BIT(11)
  33. #define FMC2_BCR_WREN BIT(12)
  34. #define FMC2_BCR_WAITEN BIT(13)
  35. #define FMC2_BCR_EXTMOD BIT(14)
  36. #define FMC2_BCR_ASYNCWAIT BIT(15)
  37. #define FMC2_BCR_CPSIZE GENMASK(18, 16)
  38. #define FMC2_BCR_CBURSTRW BIT(19)
  39. #define FMC2_BCR_NBLSET GENMASK(23, 22)
  40. /* Register: FMC2_BTRx/FMC2_BWTRx */
  41. #define FMC2_BXTR_ADDSET GENMASK(3, 0)
  42. #define FMC2_BXTR_ADDHLD GENMASK(7, 4)
  43. #define FMC2_BXTR_DATAST GENMASK(15, 8)
  44. #define FMC2_BXTR_BUSTURN GENMASK(19, 16)
  45. #define FMC2_BTR_CLKDIV GENMASK(23, 20)
  46. #define FMC2_BTR_DATLAT GENMASK(27, 24)
  47. #define FMC2_BXTR_ACCMOD GENMASK(29, 28)
  48. #define FMC2_BXTR_DATAHLD GENMASK(31, 30)
  49. /* Register: FMC2_PCSCNTR */
  50. #define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0)
  51. #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16)
  52. #define FMC2_MAX_EBI_CE 4
  53. #define FMC2_MAX_BANKS 5
  54. #define FMC2_BCR_CPSIZE_0 0x0
  55. #define FMC2_BCR_CPSIZE_128 0x1
  56. #define FMC2_BCR_CPSIZE_256 0x2
  57. #define FMC2_BCR_CPSIZE_512 0x3
  58. #define FMC2_BCR_CPSIZE_1024 0x4
  59. #define FMC2_BCR_MWID_8 0x0
  60. #define FMC2_BCR_MWID_16 0x1
  61. #define FMC2_BCR_MTYP_SRAM 0x0
  62. #define FMC2_BCR_MTYP_PSRAM 0x1
  63. #define FMC2_BCR_MTYP_NOR 0x2
  64. #define FMC2_BXTR_EXTMOD_A 0x0
  65. #define FMC2_BXTR_EXTMOD_B 0x1
  66. #define FMC2_BXTR_EXTMOD_C 0x2
  67. #define FMC2_BXTR_EXTMOD_D 0x3
  68. #define FMC2_BCR_NBLSET_MAX 0x3
  69. #define FMC2_BXTR_ADDSET_MAX 0xf
  70. #define FMC2_BXTR_ADDHLD_MAX 0xf
  71. #define FMC2_BXTR_DATAST_MAX 0xff
  72. #define FMC2_BXTR_BUSTURN_MAX 0xf
  73. #define FMC2_BXTR_DATAHLD_MAX 0x3
  74. #define FMC2_BTR_CLKDIV_MAX 0xf
  75. #define FMC2_BTR_DATLAT_MAX 0xf
  76. #define FMC2_PCSCNTR_CSCOUNT_MAX 0xff
  77. enum stm32_fmc2_ebi_bank {
  78. FMC2_EBI1 = 0,
  79. FMC2_EBI2,
  80. FMC2_EBI3,
  81. FMC2_EBI4,
  82. FMC2_NAND
  83. };
  84. enum stm32_fmc2_ebi_register_type {
  85. FMC2_REG_BCR = 1,
  86. FMC2_REG_BTR,
  87. FMC2_REG_BWTR,
  88. FMC2_REG_PCSCNTR
  89. };
  90. enum stm32_fmc2_ebi_transaction_type {
  91. FMC2_ASYNC_MODE_1_SRAM = 0,
  92. FMC2_ASYNC_MODE_1_PSRAM,
  93. FMC2_ASYNC_MODE_A_SRAM,
  94. FMC2_ASYNC_MODE_A_PSRAM,
  95. FMC2_ASYNC_MODE_2_NOR,
  96. FMC2_ASYNC_MODE_B_NOR,
  97. FMC2_ASYNC_MODE_C_NOR,
  98. FMC2_ASYNC_MODE_D_NOR,
  99. FMC2_SYNC_READ_SYNC_WRITE_PSRAM,
  100. FMC2_SYNC_READ_ASYNC_WRITE_PSRAM,
  101. FMC2_SYNC_READ_SYNC_WRITE_NOR,
  102. FMC2_SYNC_READ_ASYNC_WRITE_NOR
  103. };
  104. enum stm32_fmc2_ebi_buswidth {
  105. FMC2_BUSWIDTH_8 = 8,
  106. FMC2_BUSWIDTH_16 = 16
  107. };
  108. enum stm32_fmc2_ebi_cpsize {
  109. FMC2_CPSIZE_0 = 0,
  110. FMC2_CPSIZE_128 = 128,
  111. FMC2_CPSIZE_256 = 256,
  112. FMC2_CPSIZE_512 = 512,
  113. FMC2_CPSIZE_1024 = 1024
  114. };
  115. struct stm32_fmc2_ebi {
  116. struct device *dev;
  117. struct clk *clk;
  118. struct regmap *regmap;
  119. u8 bank_assigned;
  120. u32 bcr[FMC2_MAX_EBI_CE];
  121. u32 btr[FMC2_MAX_EBI_CE];
  122. u32 bwtr[FMC2_MAX_EBI_CE];
  123. u32 pcscntr;
  124. };
  125. /*
  126. * struct stm32_fmc2_prop - STM32 FMC2 EBI property
  127. * @name: the device tree binding name of the property
  128. * @bprop: indicate that it is a boolean property
  129. * @mprop: indicate that it is a mandatory property
  130. * @reg_type: the register that have to be modified
  131. * @reg_mask: the bit that have to be modified in the selected register
  132. * in case of it is a boolean property
  133. * @reset_val: the default value that have to be set in case the property
  134. * has not been defined in the device tree
  135. * @check: this callback ckecks that the property is compliant with the
  136. * transaction type selected
  137. * @calculate: this callback is called to calculate for exemple a timing
  138. * set in nanoseconds in the device tree in clock cycles or in
  139. * clock period
  140. * @set: this callback applies the values in the registers
  141. */
  142. struct stm32_fmc2_prop {
  143. const char *name;
  144. bool bprop;
  145. bool mprop;
  146. int reg_type;
  147. u32 reg_mask;
  148. u32 reset_val;
  149. int (*check)(struct stm32_fmc2_ebi *ebi,
  150. const struct stm32_fmc2_prop *prop, int cs);
  151. u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
  152. int (*set)(struct stm32_fmc2_ebi *ebi,
  153. const struct stm32_fmc2_prop *prop,
  154. int cs, u32 setup);
  155. };
  156. static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi,
  157. const struct stm32_fmc2_prop *prop,
  158. int cs)
  159. {
  160. u32 bcr;
  161. regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
  162. if (bcr & FMC2_BCR_MTYP)
  163. return 0;
  164. return -EINVAL;
  165. }
  166. static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi,
  167. const struct stm32_fmc2_prop *prop,
  168. int cs)
  169. {
  170. u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  171. regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
  172. if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
  173. return 0;
  174. return -EINVAL;
  175. }
  176. static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi,
  177. const struct stm32_fmc2_prop *prop,
  178. int cs)
  179. {
  180. u32 bcr;
  181. regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
  182. if (bcr & FMC2_BCR_BURSTEN)
  183. return 0;
  184. return -EINVAL;
  185. }
  186. static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi,
  187. const struct stm32_fmc2_prop *prop,
  188. int cs)
  189. {
  190. u32 bcr;
  191. regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
  192. if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW))
  193. return 0;
  194. return -EINVAL;
  195. }
  196. static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi,
  197. const struct stm32_fmc2_prop *prop,
  198. int cs)
  199. {
  200. u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
  201. regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
  202. if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
  203. return 0;
  204. return -EINVAL;
  205. }
  206. static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi,
  207. const struct stm32_fmc2_prop *prop,
  208. int cs)
  209. {
  210. u32 bcr, bxtr, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
  211. regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
  212. if (prop->reg_type == FMC2_REG_BWTR)
  213. regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr);
  214. else
  215. regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr);
  216. if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) &&
  217. ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN))
  218. return 0;
  219. return -EINVAL;
  220. }
  221. static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi,
  222. const struct stm32_fmc2_prop *prop,
  223. int cs)
  224. {
  225. u32 bcr, bcr1;
  226. regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
  227. if (cs)
  228. regmap_read(ebi->regmap, FMC2_BCR1, &bcr1);
  229. else
  230. bcr1 = bcr;
  231. if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN)))
  232. return 0;
  233. return -EINVAL;
  234. }
  235. static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi,
  236. const struct stm32_fmc2_prop *prop,
  237. int cs)
  238. {
  239. if (cs)
  240. return -EINVAL;
  241. return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
  242. }
  243. static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi,
  244. int cs, u32 setup)
  245. {
  246. unsigned long hclk = clk_get_rate(ebi->clk);
  247. unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
  248. return DIV_ROUND_UP(setup * 1000, hclkp);
  249. }
  250. static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi,
  251. int cs, u32 setup)
  252. {
  253. u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup);
  254. u32 bcr, btr, clk_period;
  255. regmap_read(ebi->regmap, FMC2_BCR1, &bcr);
  256. if (bcr & FMC2_BCR1_CCLKEN || !cs)
  257. regmap_read(ebi->regmap, FMC2_BTR1, &btr);
  258. else
  259. regmap_read(ebi->regmap, FMC2_BTR(cs), &btr);
  260. clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1;
  261. return DIV_ROUND_UP(nb_clk_cycles, clk_period);
  262. }
  263. static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg)
  264. {
  265. switch (reg_type) {
  266. case FMC2_REG_BCR:
  267. *reg = FMC2_BCR(cs);
  268. break;
  269. case FMC2_REG_BTR:
  270. *reg = FMC2_BTR(cs);
  271. break;
  272. case FMC2_REG_BWTR:
  273. *reg = FMC2_BWTR(cs);
  274. break;
  275. case FMC2_REG_PCSCNTR:
  276. *reg = FMC2_PCSCNTR;
  277. break;
  278. default:
  279. return -EINVAL;
  280. }
  281. return 0;
  282. }
  283. static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi,
  284. const struct stm32_fmc2_prop *prop,
  285. int cs, u32 setup)
  286. {
  287. u32 reg;
  288. int ret;
  289. ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
  290. if (ret)
  291. return ret;
  292. regmap_update_bits(ebi->regmap, reg, prop->reg_mask,
  293. setup ? prop->reg_mask : 0);
  294. return 0;
  295. }
  296. static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi,
  297. const struct stm32_fmc2_prop *prop,
  298. int cs, u32 setup)
  299. {
  300. u32 bcr_mask, bcr = FMC2_BCR_WREN;
  301. u32 btr_mask, btr = 0;
  302. u32 bwtr_mask, bwtr = 0;
  303. bwtr_mask = FMC2_BXTR_ACCMOD;
  304. btr_mask = FMC2_BXTR_ACCMOD;
  305. bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN |
  306. FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN |
  307. FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW;
  308. switch (setup) {
  309. case FMC2_ASYNC_MODE_1_SRAM:
  310. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
  311. /*
  312. * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
  313. * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
  314. */
  315. break;
  316. case FMC2_ASYNC_MODE_1_PSRAM:
  317. /*
  318. * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
  319. * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
  320. */
  321. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
  322. break;
  323. case FMC2_ASYNC_MODE_A_SRAM:
  324. /*
  325. * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
  326. * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
  327. */
  328. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
  329. bcr |= FMC2_BCR_EXTMOD;
  330. btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
  331. bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
  332. break;
  333. case FMC2_ASYNC_MODE_A_PSRAM:
  334. /*
  335. * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
  336. * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
  337. */
  338. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
  339. bcr |= FMC2_BCR_EXTMOD;
  340. btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
  341. bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
  342. break;
  343. case FMC2_ASYNC_MODE_2_NOR:
  344. /*
  345. * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
  346. * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
  347. */
  348. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  349. bcr |= FMC2_BCR_FACCEN;
  350. break;
  351. case FMC2_ASYNC_MODE_B_NOR:
  352. /*
  353. * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
  354. * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1
  355. */
  356. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  357. bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
  358. btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
  359. bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
  360. break;
  361. case FMC2_ASYNC_MODE_C_NOR:
  362. /*
  363. * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
  364. * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2
  365. */
  366. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  367. bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
  368. btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
  369. bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
  370. break;
  371. case FMC2_ASYNC_MODE_D_NOR:
  372. /*
  373. * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
  374. * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3
  375. */
  376. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  377. bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
  378. btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
  379. bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
  380. break;
  381. case FMC2_SYNC_READ_SYNC_WRITE_PSRAM:
  382. /*
  383. * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
  384. * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
  385. */
  386. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
  387. bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
  388. break;
  389. case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM:
  390. /*
  391. * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
  392. * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
  393. */
  394. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
  395. bcr |= FMC2_BCR_BURSTEN;
  396. break;
  397. case FMC2_SYNC_READ_SYNC_WRITE_NOR:
  398. /*
  399. * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
  400. * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
  401. */
  402. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  403. bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
  404. break;
  405. case FMC2_SYNC_READ_ASYNC_WRITE_NOR:
  406. /*
  407. * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
  408. * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
  409. */
  410. bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
  411. bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN;
  412. break;
  413. default:
  414. /* Type of transaction not supported */
  415. return -EINVAL;
  416. }
  417. if (bcr & FMC2_BCR_EXTMOD)
  418. regmap_update_bits(ebi->regmap, FMC2_BWTR(cs),
  419. bwtr_mask, bwtr);
  420. regmap_update_bits(ebi->regmap, FMC2_BTR(cs), btr_mask, btr);
  421. regmap_update_bits(ebi->regmap, FMC2_BCR(cs), bcr_mask, bcr);
  422. return 0;
  423. }
  424. static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi,
  425. const struct stm32_fmc2_prop *prop,
  426. int cs, u32 setup)
  427. {
  428. u32 val;
  429. switch (setup) {
  430. case FMC2_BUSWIDTH_8:
  431. val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8);
  432. break;
  433. case FMC2_BUSWIDTH_16:
  434. val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16);
  435. break;
  436. default:
  437. /* Buswidth not supported */
  438. return -EINVAL;
  439. }
  440. regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MWID, val);
  441. return 0;
  442. }
  443. static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi,
  444. const struct stm32_fmc2_prop *prop,
  445. int cs, u32 setup)
  446. {
  447. u32 val;
  448. switch (setup) {
  449. case FMC2_CPSIZE_0:
  450. val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0);
  451. break;
  452. case FMC2_CPSIZE_128:
  453. val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128);
  454. break;
  455. case FMC2_CPSIZE_256:
  456. val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256);
  457. break;
  458. case FMC2_CPSIZE_512:
  459. val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512);
  460. break;
  461. case FMC2_CPSIZE_1024:
  462. val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024);
  463. break;
  464. default:
  465. /* Cpsize not supported */
  466. return -EINVAL;
  467. }
  468. regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);
  469. return 0;
  470. }
  471. static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi,
  472. const struct stm32_fmc2_prop *prop,
  473. int cs, u32 setup)
  474. {
  475. u32 val;
  476. val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX);
  477. val = FIELD_PREP(FMC2_BCR_NBLSET, val);
  478. regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_NBLSET, val);
  479. return 0;
  480. }
  481. static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi,
  482. const struct stm32_fmc2_prop *prop,
  483. int cs, u32 setup)
  484. {
  485. u32 bcr, bxtr, reg;
  486. u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
  487. int ret;
  488. ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
  489. if (ret)
  490. return ret;
  491. regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
  492. if (prop->reg_type == FMC2_REG_BWTR)
  493. regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr);
  494. else
  495. regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr);
  496. if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)
  497. val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX);
  498. else
  499. val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX);
  500. val = FIELD_PREP(FMC2_BXTR_ADDSET, val);
  501. regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDSET, val);
  502. return 0;
  503. }
  504. static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi,
  505. const struct stm32_fmc2_prop *prop,
  506. int cs, u32 setup)
  507. {
  508. u32 val, reg;
  509. int ret;
  510. ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
  511. if (ret)
  512. return ret;
  513. val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX);
  514. val = FIELD_PREP(FMC2_BXTR_ADDHLD, val);
  515. regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDHLD, val);
  516. return 0;
  517. }
  518. static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi,
  519. const struct stm32_fmc2_prop *prop,
  520. int cs, u32 setup)
  521. {
  522. u32 val, reg;
  523. int ret;
  524. ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
  525. if (ret)
  526. return ret;
  527. val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX);
  528. val = FIELD_PREP(FMC2_BXTR_DATAST, val);
  529. regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAST, val);
  530. return 0;
  531. }
  532. static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi,
  533. const struct stm32_fmc2_prop *prop,
  534. int cs, u32 setup)
  535. {
  536. u32 val, reg;
  537. int ret;
  538. ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
  539. if (ret)
  540. return ret;
  541. val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0;
  542. val = FIELD_PREP(FMC2_BXTR_BUSTURN, val);
  543. regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_BUSTURN, val);
  544. return 0;
  545. }
  546. static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi,
  547. const struct stm32_fmc2_prop *prop,
  548. int cs, u32 setup)
  549. {
  550. u32 val, reg;
  551. int ret;
  552. ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
  553. if (ret)
  554. return ret;
  555. if (prop->reg_type == FMC2_REG_BWTR)
  556. val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0;
  557. else
  558. val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX);
  559. val = FIELD_PREP(FMC2_BXTR_DATAHLD, val);
  560. regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAHLD, val);
  561. return 0;
  562. }
  563. static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi,
  564. const struct stm32_fmc2_prop *prop,
  565. int cs, u32 setup)
  566. {
  567. u32 val;
  568. val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1;
  569. val = FIELD_PREP(FMC2_BTR_CLKDIV, val);
  570. regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val);
  571. return 0;
  572. }
  573. static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi,
  574. const struct stm32_fmc2_prop *prop,
  575. int cs, u32 setup)
  576. {
  577. u32 val;
  578. val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0;
  579. val = FIELD_PREP(FMC2_BTR_DATLAT, val);
  580. regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_DATLAT, val);
  581. return 0;
  582. }
  583. static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi,
  584. const struct stm32_fmc2_prop *prop,
  585. int cs, u32 setup)
  586. {
  587. u32 old_val, new_val, pcscntr;
  588. if (setup < 1)
  589. return 0;
  590. regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr);
  591. /* Enable counter for the bank */
  592. regmap_update_bits(ebi->regmap, FMC2_PCSCNTR,
  593. FMC2_PCSCNTR_CNTBEN(cs),
  594. FMC2_PCSCNTR_CNTBEN(cs));
  595. new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX);
  596. old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr);
  597. if (old_val && new_val > old_val)
  598. /* Keep current counter value */
  599. return 0;
  600. new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val);
  601. regmap_update_bits(ebi->regmap, FMC2_PCSCNTR,
  602. FMC2_PCSCNTR_CSCOUNT, new_val);
  603. return 0;
  604. }
  605. static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = {
  606. /* st,fmc2-ebi-cs-trans-type must be the first property */
  607. {
  608. .name = "st,fmc2-ebi-cs-transaction-type",
  609. .mprop = true,
  610. .set = stm32_fmc2_ebi_set_trans_type,
  611. },
  612. {
  613. .name = "st,fmc2-ebi-cs-cclk-enable",
  614. .bprop = true,
  615. .reg_type = FMC2_REG_BCR,
  616. .reg_mask = FMC2_BCR1_CCLKEN,
  617. .check = stm32_fmc2_ebi_check_cclk,
  618. .set = stm32_fmc2_ebi_set_bit_field,
  619. },
  620. {
  621. .name = "st,fmc2-ebi-cs-mux-enable",
  622. .bprop = true,
  623. .reg_type = FMC2_REG_BCR,
  624. .reg_mask = FMC2_BCR_MUXEN,
  625. .check = stm32_fmc2_ebi_check_mux,
  626. .set = stm32_fmc2_ebi_set_bit_field,
  627. },
  628. {
  629. .name = "st,fmc2-ebi-cs-buswidth",
  630. .reset_val = FMC2_BUSWIDTH_16,
  631. .set = stm32_fmc2_ebi_set_buswidth,
  632. },
  633. {
  634. .name = "st,fmc2-ebi-cs-waitpol-high",
  635. .bprop = true,
  636. .reg_type = FMC2_REG_BCR,
  637. .reg_mask = FMC2_BCR_WAITPOL,
  638. .set = stm32_fmc2_ebi_set_bit_field,
  639. },
  640. {
  641. .name = "st,fmc2-ebi-cs-waitcfg-enable",
  642. .bprop = true,
  643. .reg_type = FMC2_REG_BCR,
  644. .reg_mask = FMC2_BCR_WAITCFG,
  645. .check = stm32_fmc2_ebi_check_waitcfg,
  646. .set = stm32_fmc2_ebi_set_bit_field,
  647. },
  648. {
  649. .name = "st,fmc2-ebi-cs-wait-enable",
  650. .bprop = true,
  651. .reg_type = FMC2_REG_BCR,
  652. .reg_mask = FMC2_BCR_WAITEN,
  653. .check = stm32_fmc2_ebi_check_sync_trans,
  654. .set = stm32_fmc2_ebi_set_bit_field,
  655. },
  656. {
  657. .name = "st,fmc2-ebi-cs-asyncwait-enable",
  658. .bprop = true,
  659. .reg_type = FMC2_REG_BCR,
  660. .reg_mask = FMC2_BCR_ASYNCWAIT,
  661. .check = stm32_fmc2_ebi_check_async_trans,
  662. .set = stm32_fmc2_ebi_set_bit_field,
  663. },
  664. {
  665. .name = "st,fmc2-ebi-cs-cpsize",
  666. .check = stm32_fmc2_ebi_check_cpsize,
  667. .set = stm32_fmc2_ebi_set_cpsize,
  668. },
  669. {
  670. .name = "st,fmc2-ebi-cs-byte-lane-setup-ns",
  671. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  672. .set = stm32_fmc2_ebi_set_bl_setup,
  673. },
  674. {
  675. .name = "st,fmc2-ebi-cs-address-setup-ns",
  676. .reg_type = FMC2_REG_BTR,
  677. .reset_val = FMC2_BXTR_ADDSET_MAX,
  678. .check = stm32_fmc2_ebi_check_async_trans,
  679. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  680. .set = stm32_fmc2_ebi_set_address_setup,
  681. },
  682. {
  683. .name = "st,fmc2-ebi-cs-address-hold-ns",
  684. .reg_type = FMC2_REG_BTR,
  685. .reset_val = FMC2_BXTR_ADDHLD_MAX,
  686. .check = stm32_fmc2_ebi_check_address_hold,
  687. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  688. .set = stm32_fmc2_ebi_set_address_hold,
  689. },
  690. {
  691. .name = "st,fmc2-ebi-cs-data-setup-ns",
  692. .reg_type = FMC2_REG_BTR,
  693. .reset_val = FMC2_BXTR_DATAST_MAX,
  694. .check = stm32_fmc2_ebi_check_async_trans,
  695. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  696. .set = stm32_fmc2_ebi_set_data_setup,
  697. },
  698. {
  699. .name = "st,fmc2-ebi-cs-bus-turnaround-ns",
  700. .reg_type = FMC2_REG_BTR,
  701. .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
  702. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  703. .set = stm32_fmc2_ebi_set_bus_turnaround,
  704. },
  705. {
  706. .name = "st,fmc2-ebi-cs-data-hold-ns",
  707. .reg_type = FMC2_REG_BTR,
  708. .check = stm32_fmc2_ebi_check_async_trans,
  709. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  710. .set = stm32_fmc2_ebi_set_data_hold,
  711. },
  712. {
  713. .name = "st,fmc2-ebi-cs-clk-period-ns",
  714. .reset_val = FMC2_BTR_CLKDIV_MAX + 1,
  715. .check = stm32_fmc2_ebi_check_clk_period,
  716. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  717. .set = stm32_fmc2_ebi_set_clk_period,
  718. },
  719. {
  720. .name = "st,fmc2-ebi-cs-data-latency-ns",
  721. .check = stm32_fmc2_ebi_check_sync_trans,
  722. .calculate = stm32_fmc2_ebi_ns_to_clk_period,
  723. .set = stm32_fmc2_ebi_set_data_latency,
  724. },
  725. {
  726. .name = "st,fmc2-ebi-cs-write-address-setup-ns",
  727. .reg_type = FMC2_REG_BWTR,
  728. .reset_val = FMC2_BXTR_ADDSET_MAX,
  729. .check = stm32_fmc2_ebi_check_async_trans,
  730. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  731. .set = stm32_fmc2_ebi_set_address_setup,
  732. },
  733. {
  734. .name = "st,fmc2-ebi-cs-write-address-hold-ns",
  735. .reg_type = FMC2_REG_BWTR,
  736. .reset_val = FMC2_BXTR_ADDHLD_MAX,
  737. .check = stm32_fmc2_ebi_check_address_hold,
  738. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  739. .set = stm32_fmc2_ebi_set_address_hold,
  740. },
  741. {
  742. .name = "st,fmc2-ebi-cs-write-data-setup-ns",
  743. .reg_type = FMC2_REG_BWTR,
  744. .reset_val = FMC2_BXTR_DATAST_MAX,
  745. .check = stm32_fmc2_ebi_check_async_trans,
  746. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  747. .set = stm32_fmc2_ebi_set_data_setup,
  748. },
  749. {
  750. .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns",
  751. .reg_type = FMC2_REG_BWTR,
  752. .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
  753. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  754. .set = stm32_fmc2_ebi_set_bus_turnaround,
  755. },
  756. {
  757. .name = "st,fmc2-ebi-cs-write-data-hold-ns",
  758. .reg_type = FMC2_REG_BWTR,
  759. .check = stm32_fmc2_ebi_check_async_trans,
  760. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  761. .set = stm32_fmc2_ebi_set_data_hold,
  762. },
  763. {
  764. .name = "st,fmc2-ebi-cs-max-low-pulse-ns",
  765. .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
  766. .set = stm32_fmc2_ebi_set_max_low_pulse,
  767. },
  768. };
  769. static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
  770. struct device_node *dev_node,
  771. const struct stm32_fmc2_prop *prop,
  772. int cs)
  773. {
  774. struct device *dev = ebi->dev;
  775. u32 setup = 0;
  776. if (!prop->set) {
  777. dev_err(dev, "property %s is not well defined\n", prop->name);
  778. return -EINVAL;
  779. }
  780. if (prop->check && prop->check(ebi, prop, cs))
  781. /* Skeep this property */
  782. return 0;
  783. if (prop->bprop) {
  784. bool bprop;
  785. bprop = of_property_read_bool(dev_node, prop->name);
  786. if (prop->mprop && !bprop) {
  787. dev_err(dev, "mandatory property %s not defined in the device tree\n",
  788. prop->name);
  789. return -EINVAL;
  790. }
  791. if (bprop)
  792. setup = 1;
  793. } else {
  794. u32 val;
  795. int ret;
  796. ret = of_property_read_u32(dev_node, prop->name, &val);
  797. if (prop->mprop && ret) {
  798. dev_err(dev, "mandatory property %s not defined in the device tree\n",
  799. prop->name);
  800. return ret;
  801. }
  802. if (ret)
  803. setup = prop->reset_val;
  804. else if (prop->calculate)
  805. setup = prop->calculate(ebi, cs, val);
  806. else
  807. setup = val;
  808. }
  809. return prop->set(ebi, prop, cs, setup);
  810. }
  811. static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs)
  812. {
  813. regmap_update_bits(ebi->regmap, FMC2_BCR(cs),
  814. FMC2_BCR_MBKEN, FMC2_BCR_MBKEN);
  815. }
  816. static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs)
  817. {
  818. regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MBKEN, 0);
  819. }
  820. static void stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi)
  821. {
  822. unsigned int cs;
  823. for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
  824. regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]);
  825. regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]);
  826. regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]);
  827. }
  828. regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr);
  829. }
  830. static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi)
  831. {
  832. unsigned int cs;
  833. for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
  834. regmap_write(ebi->regmap, FMC2_BCR(cs), ebi->bcr[cs]);
  835. regmap_write(ebi->regmap, FMC2_BTR(cs), ebi->btr[cs]);
  836. regmap_write(ebi->regmap, FMC2_BWTR(cs), ebi->bwtr[cs]);
  837. }
  838. regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr);
  839. }
  840. static void stm32_fmc2_ebi_disable_banks(struct stm32_fmc2_ebi *ebi)
  841. {
  842. unsigned int cs;
  843. for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
  844. if (!(ebi->bank_assigned & BIT(cs)))
  845. continue;
  846. stm32_fmc2_ebi_disable_bank(ebi, cs);
  847. }
  848. }
  849. /* NWAIT signal can not be connected to EBI controller and NAND controller */
  850. static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi)
  851. {
  852. unsigned int cs;
  853. u32 bcr;
  854. for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
  855. if (!(ebi->bank_assigned & BIT(cs)))
  856. continue;
  857. regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
  858. if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) &&
  859. ebi->bank_assigned & BIT(FMC2_NAND))
  860. return true;
  861. }
  862. return false;
  863. }
  864. static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi)
  865. {
  866. regmap_update_bits(ebi->regmap, FMC2_BCR1,
  867. FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
  868. }
  869. static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi)
  870. {
  871. regmap_update_bits(ebi->regmap, FMC2_BCR1, FMC2_BCR1_FMC2EN, 0);
  872. }
  873. static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi,
  874. struct device_node *dev_node,
  875. u32 cs)
  876. {
  877. unsigned int i;
  878. int ret;
  879. stm32_fmc2_ebi_disable_bank(ebi, cs);
  880. for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) {
  881. const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i];
  882. ret = stm32_fmc2_ebi_parse_prop(ebi, dev_node, p, cs);
  883. if (ret) {
  884. dev_err(ebi->dev, "property %s could not be set: %d\n",
  885. p->name, ret);
  886. return ret;
  887. }
  888. }
  889. stm32_fmc2_ebi_enable_bank(ebi, cs);
  890. return 0;
  891. }
  892. static int stm32_fmc2_ebi_parse_dt(struct stm32_fmc2_ebi *ebi)
  893. {
  894. struct device *dev = ebi->dev;
  895. struct device_node *child;
  896. bool child_found = false;
  897. u32 bank;
  898. int ret;
  899. for_each_available_child_of_node(dev->of_node, child) {
  900. ret = of_property_read_u32(child, "reg", &bank);
  901. if (ret) {
  902. dev_err(dev, "could not retrieve reg property: %d\n",
  903. ret);
  904. of_node_put(child);
  905. return ret;
  906. }
  907. if (bank >= FMC2_MAX_BANKS) {
  908. dev_err(dev, "invalid reg value: %d\n", bank);
  909. of_node_put(child);
  910. return -EINVAL;
  911. }
  912. if (ebi->bank_assigned & BIT(bank)) {
  913. dev_err(dev, "bank already assigned: %d\n", bank);
  914. of_node_put(child);
  915. return -EINVAL;
  916. }
  917. if (bank < FMC2_MAX_EBI_CE) {
  918. ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
  919. if (ret) {
  920. dev_err(dev, "setup chip select %d failed: %d\n",
  921. bank, ret);
  922. of_node_put(child);
  923. return ret;
  924. }
  925. }
  926. ebi->bank_assigned |= BIT(bank);
  927. child_found = true;
  928. }
  929. if (!child_found) {
  930. dev_warn(dev, "no subnodes found, disable the driver.\n");
  931. return -ENODEV;
  932. }
  933. if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
  934. dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n");
  935. return -EINVAL;
  936. }
  937. stm32_fmc2_ebi_enable(ebi);
  938. return of_platform_populate(dev->of_node, NULL, NULL, dev);
  939. }
  940. static int stm32_fmc2_ebi_probe(struct platform_device *pdev)
  941. {
  942. struct device *dev = &pdev->dev;
  943. struct stm32_fmc2_ebi *ebi;
  944. struct reset_control *rstc;
  945. int ret;
  946. ebi = devm_kzalloc(&pdev->dev, sizeof(*ebi), GFP_KERNEL);
  947. if (!ebi)
  948. return -ENOMEM;
  949. ebi->dev = dev;
  950. ebi->regmap = device_node_to_regmap(dev->of_node);
  951. if (IS_ERR(ebi->regmap))
  952. return PTR_ERR(ebi->regmap);
  953. ebi->clk = devm_clk_get(dev, NULL);
  954. if (IS_ERR(ebi->clk))
  955. return PTR_ERR(ebi->clk);
  956. rstc = devm_reset_control_get(dev, NULL);
  957. if (PTR_ERR(rstc) == -EPROBE_DEFER)
  958. return -EPROBE_DEFER;
  959. ret = clk_prepare_enable(ebi->clk);
  960. if (ret)
  961. return ret;
  962. if (!IS_ERR(rstc)) {
  963. reset_control_assert(rstc);
  964. reset_control_deassert(rstc);
  965. }
  966. ret = stm32_fmc2_ebi_parse_dt(ebi);
  967. if (ret)
  968. goto err_release;
  969. stm32_fmc2_ebi_save_setup(ebi);
  970. platform_set_drvdata(pdev, ebi);
  971. return 0;
  972. err_release:
  973. stm32_fmc2_ebi_disable_banks(ebi);
  974. stm32_fmc2_ebi_disable(ebi);
  975. clk_disable_unprepare(ebi->clk);
  976. return ret;
  977. }
  978. static int stm32_fmc2_ebi_remove(struct platform_device *pdev)
  979. {
  980. struct stm32_fmc2_ebi *ebi = platform_get_drvdata(pdev);
  981. of_platform_depopulate(&pdev->dev);
  982. stm32_fmc2_ebi_disable_banks(ebi);
  983. stm32_fmc2_ebi_disable(ebi);
  984. clk_disable_unprepare(ebi->clk);
  985. return 0;
  986. }
  987. static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev)
  988. {
  989. struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev);
  990. stm32_fmc2_ebi_disable(ebi);
  991. clk_disable_unprepare(ebi->clk);
  992. pinctrl_pm_select_sleep_state(dev);
  993. return 0;
  994. }
  995. static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev)
  996. {
  997. struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev);
  998. int ret;
  999. pinctrl_pm_select_default_state(dev);
  1000. ret = clk_prepare_enable(ebi->clk);
  1001. if (ret)
  1002. return ret;
  1003. stm32_fmc2_ebi_set_setup(ebi);
  1004. stm32_fmc2_ebi_enable(ebi);
  1005. return 0;
  1006. }
  1007. static SIMPLE_DEV_PM_OPS(stm32_fmc2_ebi_pm_ops, stm32_fmc2_ebi_suspend,
  1008. stm32_fmc2_ebi_resume);
  1009. static const struct of_device_id stm32_fmc2_ebi_match[] = {
  1010. {.compatible = "st,stm32mp1-fmc2-ebi"},
  1011. {}
  1012. };
  1013. MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match);
  1014. static struct platform_driver stm32_fmc2_ebi_driver = {
  1015. .probe = stm32_fmc2_ebi_probe,
  1016. .remove = stm32_fmc2_ebi_remove,
  1017. .driver = {
  1018. .name = "stm32_fmc2_ebi",
  1019. .of_match_table = stm32_fmc2_ebi_match,
  1020. .pm = &stm32_fmc2_ebi_pm_ops,
  1021. },
  1022. };
  1023. module_platform_driver(stm32_fmc2_ebi_driver);
  1024. MODULE_ALIAS("platform:stm32_fmc2_ebi");
  1025. MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>");
  1026. MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 ebi driver");
  1027. MODULE_LICENSE("GPL v2");