renesas-rpc-if.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas RPC-IF core driver
  4. *
  5. * Copyright (C) 2018-2019 Renesas Solutions Corp.
  6. * Copyright (C) 2019 Macronix International Co., Ltd.
  7. * Copyright (C) 2019-2020 Cogent Embedded, Inc.
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/of.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/regmap.h>
  16. #include <linux/reset.h>
  17. #include <memory/renesas-rpc-if.h>
  18. #define RPCIF_CMNCR 0x0000 /* R/W */
  19. #define RPCIF_CMNCR_MD BIT(31)
  20. #define RPCIF_CMNCR_SFDE BIT(24) /* undocumented but must be set */
  21. #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
  22. #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
  23. #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
  24. #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
  25. #define RPCIF_CMNCR_MOIIO_HIZ (RPCIF_CMNCR_MOIIO0(3) | \
  26. RPCIF_CMNCR_MOIIO1(3) | \
  27. RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3))
  28. #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */
  29. #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */
  30. #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
  31. #define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
  32. RPCIF_CMNCR_IO3FV(3))
  33. #define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
  34. #define RPCIF_SSLDR 0x0004 /* R/W */
  35. #define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
  36. #define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
  37. #define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
  38. #define RPCIF_DRCR 0x000C /* R/W */
  39. #define RPCIF_DRCR_SSLN BIT(24)
  40. #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
  41. #define RPCIF_DRCR_RCF BIT(9)
  42. #define RPCIF_DRCR_RBE BIT(8)
  43. #define RPCIF_DRCR_SSLE BIT(0)
  44. #define RPCIF_DRCMR 0x0010 /* R/W */
  45. #define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16)
  46. #define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
  47. #define RPCIF_DREAR 0x0014 /* R/W */
  48. #define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16)
  49. #define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0)
  50. #define RPCIF_DROPR 0x0018 /* R/W */
  51. #define RPCIF_DRENR 0x001C /* R/W */
  52. #define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
  53. #define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
  54. #define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24)
  55. #define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
  56. #define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
  57. #define RPCIF_DRENR_DME BIT(15)
  58. #define RPCIF_DRENR_CDE BIT(14)
  59. #define RPCIF_DRENR_OCDE BIT(12)
  60. #define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
  61. #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
  62. #define RPCIF_SMCR 0x0020 /* R/W */
  63. #define RPCIF_SMCR_SSLKP BIT(8)
  64. #define RPCIF_SMCR_SPIRE BIT(2)
  65. #define RPCIF_SMCR_SPIWE BIT(1)
  66. #define RPCIF_SMCR_SPIE BIT(0)
  67. #define RPCIF_SMCMR 0x0024 /* R/W */
  68. #define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16)
  69. #define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
  70. #define RPCIF_SMADR 0x0028 /* R/W */
  71. #define RPCIF_SMOPR 0x002C /* R/W */
  72. #define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
  73. #define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
  74. #define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
  75. #define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
  76. #define RPCIF_SMENR 0x0030 /* R/W */
  77. #define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30)
  78. #define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
  79. #define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24)
  80. #define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
  81. #define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16)
  82. #define RPCIF_SMENR_DME BIT(15)
  83. #define RPCIF_SMENR_CDE BIT(14)
  84. #define RPCIF_SMENR_OCDE BIT(12)
  85. #define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
  86. #define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
  87. #define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
  88. #define RPCIF_SMRDR0 0x0038 /* R */
  89. #define RPCIF_SMRDR1 0x003C /* R */
  90. #define RPCIF_SMWDR0 0x0040 /* W */
  91. #define RPCIF_SMWDR1 0x0044 /* W */
  92. #define RPCIF_CMNSR 0x0048 /* R */
  93. #define RPCIF_CMNSR_SSLF BIT(1)
  94. #define RPCIF_CMNSR_TEND BIT(0)
  95. #define RPCIF_DRDMCR 0x0058 /* R/W */
  96. #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
  97. #define RPCIF_DRDRENR 0x005C /* R/W */
  98. #define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
  99. #define RPCIF_DRDRENR_ADDRE BIT(8)
  100. #define RPCIF_DRDRENR_OPDRE BIT(4)
  101. #define RPCIF_DRDRENR_DRDRE BIT(0)
  102. #define RPCIF_SMDMCR 0x0060 /* R/W */
  103. #define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
  104. #define RPCIF_SMDRENR 0x0064 /* R/W */
  105. #define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
  106. #define RPCIF_SMDRENR_ADDRE BIT(8)
  107. #define RPCIF_SMDRENR_OPDRE BIT(4)
  108. #define RPCIF_SMDRENR_SPIDRE BIT(0)
  109. #define RPCIF_PHYCNT 0x007C /* R/W */
  110. #define RPCIF_PHYCNT_CAL BIT(31)
  111. #define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
  112. #define RPCIF_PHYCNT_EXDS BIT(21)
  113. #define RPCIF_PHYCNT_OCT BIT(20)
  114. #define RPCIF_PHYCNT_DDRCAL BIT(19)
  115. #define RPCIF_PHYCNT_HS BIT(18)
  116. #define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
  117. #define RPCIF_PHYCNT_WBUF2 BIT(4)
  118. #define RPCIF_PHYCNT_WBUF BIT(2)
  119. #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
  120. #define RPCIF_PHYOFFSET1 0x0080 /* R/W */
  121. #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
  122. #define RPCIF_PHYOFFSET2 0x0084 /* R/W */
  123. #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
  124. #define RPCIF_PHYINT 0x0088 /* R/W */
  125. #define RPCIF_PHYINT_WPVAL BIT(1)
  126. #define RPCIF_DIRMAP_SIZE 0x4000000
  127. static const struct regmap_range rpcif_volatile_ranges[] = {
  128. regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
  129. regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
  130. regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
  131. };
  132. static const struct regmap_access_table rpcif_volatile_table = {
  133. .yes_ranges = rpcif_volatile_ranges,
  134. .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges),
  135. };
  136. /*
  137. * Custom accessor functions to ensure SMRDR0 and SMWDR0 are always accessed
  138. * with proper width. Requires SMENR_SPIDE to be correctly set before!
  139. */
  140. static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
  141. {
  142. struct rpcif *rpc = context;
  143. if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
  144. u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
  145. if (spide == 0x8) {
  146. *val = readb(rpc->base + reg);
  147. return 0;
  148. } else if (spide == 0xC) {
  149. *val = readw(rpc->base + reg);
  150. return 0;
  151. } else if (spide != 0xF) {
  152. return -EILSEQ;
  153. }
  154. }
  155. *val = readl(rpc->base + reg);
  156. return 0;
  157. }
  158. static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
  159. {
  160. struct rpcif *rpc = context;
  161. if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
  162. u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
  163. if (spide == 0x8) {
  164. writeb(val, rpc->base + reg);
  165. return 0;
  166. } else if (spide == 0xC) {
  167. writew(val, rpc->base + reg);
  168. return 0;
  169. } else if (spide != 0xF) {
  170. return -EILSEQ;
  171. }
  172. }
  173. writel(val, rpc->base + reg);
  174. return 0;
  175. }
  176. static const struct regmap_config rpcif_regmap_config = {
  177. .reg_bits = 32,
  178. .val_bits = 32,
  179. .reg_stride = 4,
  180. .reg_read = rpcif_reg_read,
  181. .reg_write = rpcif_reg_write,
  182. .fast_io = true,
  183. .max_register = RPCIF_PHYINT,
  184. .volatile_table = &rpcif_volatile_table,
  185. };
  186. int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
  187. {
  188. struct platform_device *pdev = to_platform_device(dev);
  189. struct resource *res;
  190. rpc->dev = dev;
  191. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
  192. rpc->base = devm_ioremap_resource(&pdev->dev, res);
  193. if (IS_ERR(rpc->base))
  194. return PTR_ERR(rpc->base);
  195. rpc->regmap = devm_regmap_init(&pdev->dev, NULL, rpc, &rpcif_regmap_config);
  196. if (IS_ERR(rpc->regmap)) {
  197. dev_err(&pdev->dev,
  198. "failed to init regmap for rpcif, error %ld\n",
  199. PTR_ERR(rpc->regmap));
  200. return PTR_ERR(rpc->regmap);
  201. }
  202. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
  203. rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
  204. if (IS_ERR(rpc->dirmap))
  205. return PTR_ERR(rpc->dirmap);
  206. rpc->size = resource_size(res);
  207. rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
  208. return PTR_ERR_OR_ZERO(rpc->rstc);
  209. }
  210. EXPORT_SYMBOL(rpcif_sw_init);
  211. void rpcif_enable_rpm(struct rpcif *rpc)
  212. {
  213. pm_runtime_enable(rpc->dev);
  214. }
  215. EXPORT_SYMBOL(rpcif_enable_rpm);
  216. void rpcif_disable_rpm(struct rpcif *rpc)
  217. {
  218. pm_runtime_disable(rpc->dev);
  219. }
  220. EXPORT_SYMBOL(rpcif_disable_rpm);
  221. void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
  222. {
  223. u32 dummy;
  224. pm_runtime_get_sync(rpc->dev);
  225. /*
  226. * NOTE: The 0x260 are undocumented bits, but they must be set.
  227. * RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits,
  228. * 0x0 : the delay is biggest,
  229. * 0x1 : the delay is 2nd biggest,
  230. * On H3 ES1.x, the value should be 0, while on others,
  231. * the value should be 7.
  232. */
  233. regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
  234. RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
  235. /*
  236. * NOTE: The 0x1511144 are undocumented bits, but they must be set
  237. * for RPCIF_PHYOFFSET1.
  238. * The 0x31 are undocumented bits, but they must be set
  239. * for RPCIF_PHYOFFSET2.
  240. */
  241. regmap_write(rpc->regmap, RPCIF_PHYOFFSET1, 0x1511144 |
  242. RPCIF_PHYOFFSET1_DDRTMG(3));
  243. regmap_write(rpc->regmap, RPCIF_PHYOFFSET2, 0x31 |
  244. RPCIF_PHYOFFSET2_OCTTMG(4));
  245. if (hyperflash)
  246. regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
  247. RPCIF_PHYINT_WPVAL, 0);
  248. regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE |
  249. RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ |
  250. RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
  251. /* Set RCF after BSZ update */
  252. regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
  253. /* Dummy read according to spec */
  254. regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
  255. regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
  256. RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
  257. pm_runtime_put(rpc->dev);
  258. rpc->bus_size = hyperflash ? 2 : 1;
  259. }
  260. EXPORT_SYMBOL(rpcif_hw_init);
  261. static int wait_msg_xfer_end(struct rpcif *rpc)
  262. {
  263. u32 sts;
  264. return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
  265. sts & RPCIF_CMNSR_TEND, 0,
  266. USEC_PER_SEC);
  267. }
  268. static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes)
  269. {
  270. if (rpc->bus_size == 2)
  271. nbytes /= 2;
  272. nbytes = clamp(nbytes, 1U, 4U);
  273. return GENMASK(3, 4 - nbytes);
  274. }
  275. static u8 rpcif_bit_size(u8 buswidth)
  276. {
  277. return buswidth > 4 ? 2 : ilog2(buswidth);
  278. }
  279. void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
  280. size_t *len)
  281. {
  282. rpc->smcr = 0;
  283. rpc->smadr = 0;
  284. rpc->enable = 0;
  285. rpc->command = 0;
  286. rpc->option = 0;
  287. rpc->dummy = 0;
  288. rpc->ddr = 0;
  289. rpc->xferlen = 0;
  290. if (op->cmd.buswidth) {
  291. rpc->enable = RPCIF_SMENR_CDE |
  292. RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
  293. rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
  294. if (op->cmd.ddr)
  295. rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
  296. }
  297. if (op->ocmd.buswidth) {
  298. rpc->enable |= RPCIF_SMENR_OCDE |
  299. RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
  300. rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
  301. }
  302. if (op->addr.buswidth) {
  303. rpc->enable |=
  304. RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
  305. if (op->addr.nbytes == 4)
  306. rpc->enable |= RPCIF_SMENR_ADE(0xF);
  307. else
  308. rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
  309. 2, 3 - op->addr.nbytes));
  310. if (op->addr.ddr)
  311. rpc->ddr |= RPCIF_SMDRENR_ADDRE;
  312. if (offs && len)
  313. rpc->smadr = *offs;
  314. else
  315. rpc->smadr = op->addr.val;
  316. }
  317. if (op->dummy.buswidth) {
  318. rpc->enable |= RPCIF_SMENR_DME;
  319. rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
  320. op->dummy.buswidth);
  321. }
  322. if (op->option.buswidth) {
  323. rpc->enable |= RPCIF_SMENR_OPDE(
  324. rpcif_bits_set(rpc, op->option.nbytes)) |
  325. RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
  326. if (op->option.ddr)
  327. rpc->ddr |= RPCIF_SMDRENR_OPDRE;
  328. rpc->option = op->option.val;
  329. }
  330. rpc->dir = op->data.dir;
  331. if (op->data.buswidth) {
  332. u32 nbytes;
  333. rpc->buffer = op->data.buf.in;
  334. switch (op->data.dir) {
  335. case RPCIF_DATA_IN:
  336. rpc->smcr = RPCIF_SMCR_SPIRE;
  337. break;
  338. case RPCIF_DATA_OUT:
  339. rpc->smcr = RPCIF_SMCR_SPIWE;
  340. break;
  341. default:
  342. break;
  343. }
  344. if (op->data.ddr)
  345. rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
  346. if (offs && len)
  347. nbytes = *len;
  348. else
  349. nbytes = op->data.nbytes;
  350. rpc->xferlen = nbytes;
  351. rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
  352. }
  353. }
  354. EXPORT_SYMBOL(rpcif_prepare);
  355. int rpcif_manual_xfer(struct rpcif *rpc)
  356. {
  357. u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
  358. int ret = 0;
  359. pm_runtime_get_sync(rpc->dev);
  360. regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
  361. RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
  362. regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
  363. RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
  364. regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
  365. regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
  366. regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
  367. regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
  368. regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
  369. smenr = rpc->enable;
  370. switch (rpc->dir) {
  371. case RPCIF_DATA_OUT:
  372. while (pos < rpc->xferlen) {
  373. u32 bytes_left = rpc->xferlen - pos;
  374. u32 nbytes, data[2];
  375. smcr = rpc->smcr | RPCIF_SMCR_SPIE;
  376. /* nbytes may only be 1, 2, 4, or 8 */
  377. nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
  378. if (bytes_left > nbytes)
  379. smcr |= RPCIF_SMCR_SSLKP;
  380. smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
  381. regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
  382. memcpy(data, rpc->buffer + pos, nbytes);
  383. if (nbytes == 8) {
  384. regmap_write(rpc->regmap, RPCIF_SMWDR1,
  385. data[0]);
  386. regmap_write(rpc->regmap, RPCIF_SMWDR0,
  387. data[1]);
  388. } else {
  389. regmap_write(rpc->regmap, RPCIF_SMWDR0,
  390. data[0]);
  391. }
  392. regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
  393. ret = wait_msg_xfer_end(rpc);
  394. if (ret)
  395. goto err_out;
  396. pos += nbytes;
  397. smenr = rpc->enable &
  398. ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
  399. }
  400. break;
  401. case RPCIF_DATA_IN:
  402. /*
  403. * RPC-IF spoils the data for the commands without an address
  404. * phase (like RDID) in the manual mode, so we'll have to work
  405. * around this issue by using the external address space read
  406. * mode instead.
  407. */
  408. if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
  409. u32 dummy;
  410. regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
  411. RPCIF_CMNCR_MD, 0);
  412. regmap_write(rpc->regmap, RPCIF_DRCR,
  413. RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
  414. regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
  415. regmap_write(rpc->regmap, RPCIF_DREAR,
  416. RPCIF_DREAR_EAC(1));
  417. regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
  418. regmap_write(rpc->regmap, RPCIF_DRENR,
  419. smenr & ~RPCIF_SMENR_SPIDE(0xF));
  420. regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
  421. regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
  422. memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
  423. regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
  424. /* Dummy read according to spec */
  425. regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
  426. break;
  427. }
  428. while (pos < rpc->xferlen) {
  429. u32 bytes_left = rpc->xferlen - pos;
  430. u32 nbytes, data[2];
  431. /* nbytes may only be 1, 2, 4, or 8 */
  432. nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
  433. regmap_write(rpc->regmap, RPCIF_SMADR,
  434. rpc->smadr + pos);
  435. smenr &= ~RPCIF_SMENR_SPIDE(0xF);
  436. smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
  437. regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
  438. regmap_write(rpc->regmap, RPCIF_SMCR,
  439. rpc->smcr | RPCIF_SMCR_SPIE);
  440. ret = wait_msg_xfer_end(rpc);
  441. if (ret)
  442. goto err_out;
  443. if (nbytes == 8) {
  444. regmap_read(rpc->regmap, RPCIF_SMRDR1,
  445. &data[0]);
  446. regmap_read(rpc->regmap, RPCIF_SMRDR0,
  447. &data[1]);
  448. } else {
  449. regmap_read(rpc->regmap, RPCIF_SMRDR0,
  450. &data[0]);
  451. }
  452. memcpy(rpc->buffer + pos, data, nbytes);
  453. pos += nbytes;
  454. }
  455. break;
  456. default:
  457. regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
  458. regmap_write(rpc->regmap, RPCIF_SMCR,
  459. rpc->smcr | RPCIF_SMCR_SPIE);
  460. ret = wait_msg_xfer_end(rpc);
  461. if (ret)
  462. goto err_out;
  463. }
  464. exit:
  465. pm_runtime_put(rpc->dev);
  466. return ret;
  467. err_out:
  468. if (reset_control_reset(rpc->rstc))
  469. dev_err(rpc->dev, "Failed to reset HW\n");
  470. rpcif_hw_init(rpc, rpc->bus_size == 2);
  471. goto exit;
  472. }
  473. EXPORT_SYMBOL(rpcif_manual_xfer);
  474. ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
  475. {
  476. loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1);
  477. size_t size = RPCIF_DIRMAP_SIZE - from;
  478. if (len > size)
  479. len = size;
  480. pm_runtime_get_sync(rpc->dev);
  481. regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
  482. regmap_write(rpc->regmap, RPCIF_DRCR, 0);
  483. regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
  484. regmap_write(rpc->regmap, RPCIF_DREAR,
  485. RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
  486. regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
  487. regmap_write(rpc->regmap, RPCIF_DRENR,
  488. rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
  489. regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
  490. regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
  491. memcpy_fromio(buf, rpc->dirmap + from, len);
  492. pm_runtime_put(rpc->dev);
  493. return len;
  494. }
  495. EXPORT_SYMBOL(rpcif_dirmap_read);
  496. static int rpcif_probe(struct platform_device *pdev)
  497. {
  498. struct platform_device *vdev;
  499. struct device_node *flash;
  500. const char *name;
  501. int ret;
  502. flash = of_get_next_child(pdev->dev.of_node, NULL);
  503. if (!flash) {
  504. dev_warn(&pdev->dev, "no flash node found\n");
  505. return -ENODEV;
  506. }
  507. if (of_device_is_compatible(flash, "jedec,spi-nor")) {
  508. name = "rpc-if-spi";
  509. } else if (of_device_is_compatible(flash, "cfi-flash")) {
  510. name = "rpc-if-hyperflash";
  511. } else {
  512. of_node_put(flash);
  513. dev_warn(&pdev->dev, "unknown flash type\n");
  514. return -ENODEV;
  515. }
  516. of_node_put(flash);
  517. vdev = platform_device_alloc(name, pdev->id);
  518. if (!vdev)
  519. return -ENOMEM;
  520. vdev->dev.parent = &pdev->dev;
  521. platform_set_drvdata(pdev, vdev);
  522. ret = platform_device_add(vdev);
  523. if (ret) {
  524. platform_device_put(vdev);
  525. return ret;
  526. }
  527. return 0;
  528. }
  529. static int rpcif_remove(struct platform_device *pdev)
  530. {
  531. struct platform_device *vdev = platform_get_drvdata(pdev);
  532. platform_device_unregister(vdev);
  533. return 0;
  534. }
  535. static const struct of_device_id rpcif_of_match[] = {
  536. { .compatible = "renesas,rcar-gen3-rpc-if", },
  537. {},
  538. };
  539. MODULE_DEVICE_TABLE(of, rpcif_of_match);
  540. static struct platform_driver rpcif_driver = {
  541. .probe = rpcif_probe,
  542. .remove = rpcif_remove,
  543. .driver = {
  544. .name = "rpc-if",
  545. .of_match_table = rpcif_of_match,
  546. },
  547. };
  548. module_platform_driver(rpcif_driver);
  549. MODULE_DESCRIPTION("Renesas RPC-IF core driver");
  550. MODULE_LICENSE("GPL v2");