pl172.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Memory controller driver for ARM PrimeCell PL172
  4. * PrimeCell MultiPort Memory Controller (PL172)
  5. *
  6. * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
  7. *
  8. * Based on:
  9. * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
  10. */
  11. #include <linux/amba/bus.h>
  12. #include <linux/clk.h>
  13. #include <linux/device.h>
  14. #include <linux/err.h>
  15. #include <linux/init.h>
  16. #include <linux/io.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/of_platform.h>
  21. #include <linux/time.h>
  22. #define MPMC_STATIC_CFG(n) (0x200 + 0x20 * (n))
  23. #define MPMC_STATIC_CFG_MW_8BIT 0x0
  24. #define MPMC_STATIC_CFG_MW_16BIT 0x1
  25. #define MPMC_STATIC_CFG_MW_32BIT 0x2
  26. #define MPMC_STATIC_CFG_PM BIT(3)
  27. #define MPMC_STATIC_CFG_PC BIT(6)
  28. #define MPMC_STATIC_CFG_PB BIT(7)
  29. #define MPMC_STATIC_CFG_EW BIT(8)
  30. #define MPMC_STATIC_CFG_B BIT(19)
  31. #define MPMC_STATIC_CFG_P BIT(20)
  32. #define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * (n))
  33. #define MPMC_STATIC_WAIT_WEN_MAX 0x0f
  34. #define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * (n))
  35. #define MPMC_STATIC_WAIT_OEN_MAX 0x0f
  36. #define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * (n))
  37. #define MPMC_STATIC_WAIT_RD_MAX 0x1f
  38. #define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * (n))
  39. #define MPMC_STATIC_WAIT_PAGE_MAX 0x1f
  40. #define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * (n))
  41. #define MPMC_STATIC_WAIT_WR_MAX 0x1f
  42. #define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * (n))
  43. #define MPMC_STATIC_WAIT_TURN_MAX 0x0f
  44. /* Maximum number of static chip selects */
  45. #define PL172_MAX_CS 4
  46. struct pl172_data {
  47. void __iomem *base;
  48. unsigned long rate;
  49. struct clk *clk;
  50. };
  51. static int pl172_timing_prop(struct amba_device *adev,
  52. const struct device_node *np, const char *name,
  53. u32 reg_offset, u32 max, int start)
  54. {
  55. struct pl172_data *pl172 = amba_get_drvdata(adev);
  56. int cycles;
  57. u32 val;
  58. if (!of_property_read_u32(np, name, &val)) {
  59. cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start;
  60. if (cycles < 0) {
  61. cycles = 0;
  62. } else if (cycles > max) {
  63. dev_err(&adev->dev, "%s timing too tight\n", name);
  64. return -EINVAL;
  65. }
  66. writel(cycles, pl172->base + reg_offset);
  67. }
  68. dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start +
  69. readl(pl172->base + reg_offset));
  70. return 0;
  71. }
  72. static int pl172_setup_static(struct amba_device *adev,
  73. struct device_node *np, u32 cs)
  74. {
  75. struct pl172_data *pl172 = amba_get_drvdata(adev);
  76. u32 cfg;
  77. int ret;
  78. /* MPMC static memory configuration */
  79. if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) {
  80. if (cfg == 8) {
  81. cfg = MPMC_STATIC_CFG_MW_8BIT;
  82. } else if (cfg == 16) {
  83. cfg = MPMC_STATIC_CFG_MW_16BIT;
  84. } else if (cfg == 32) {
  85. cfg = MPMC_STATIC_CFG_MW_32BIT;
  86. } else {
  87. dev_err(&adev->dev, "invalid memory width cs%u\n", cs);
  88. return -EINVAL;
  89. }
  90. } else {
  91. dev_err(&adev->dev, "memory-width property required\n");
  92. return -EINVAL;
  93. }
  94. if (of_property_read_bool(np, "mpmc,async-page-mode"))
  95. cfg |= MPMC_STATIC_CFG_PM;
  96. if (of_property_read_bool(np, "mpmc,cs-active-high"))
  97. cfg |= MPMC_STATIC_CFG_PC;
  98. if (of_property_read_bool(np, "mpmc,byte-lane-low"))
  99. cfg |= MPMC_STATIC_CFG_PB;
  100. if (of_property_read_bool(np, "mpmc,extended-wait"))
  101. cfg |= MPMC_STATIC_CFG_EW;
  102. if (amba_part(adev) == 0x172 &&
  103. of_property_read_bool(np, "mpmc,buffer-enable"))
  104. cfg |= MPMC_STATIC_CFG_B;
  105. if (of_property_read_bool(np, "mpmc,write-protect"))
  106. cfg |= MPMC_STATIC_CFG_P;
  107. writel(cfg, pl172->base + MPMC_STATIC_CFG(cs));
  108. dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg);
  109. /* MPMC static memory timing */
  110. ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay",
  111. MPMC_STATIC_WAIT_WEN(cs),
  112. MPMC_STATIC_WAIT_WEN_MAX, 1);
  113. if (ret)
  114. goto fail;
  115. ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay",
  116. MPMC_STATIC_WAIT_OEN(cs),
  117. MPMC_STATIC_WAIT_OEN_MAX, 0);
  118. if (ret)
  119. goto fail;
  120. ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay",
  121. MPMC_STATIC_WAIT_RD(cs),
  122. MPMC_STATIC_WAIT_RD_MAX, 1);
  123. if (ret)
  124. goto fail;
  125. ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay",
  126. MPMC_STATIC_WAIT_PAGE(cs),
  127. MPMC_STATIC_WAIT_PAGE_MAX, 1);
  128. if (ret)
  129. goto fail;
  130. ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay",
  131. MPMC_STATIC_WAIT_WR(cs),
  132. MPMC_STATIC_WAIT_WR_MAX, 2);
  133. if (ret)
  134. goto fail;
  135. ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay",
  136. MPMC_STATIC_WAIT_TURN(cs),
  137. MPMC_STATIC_WAIT_TURN_MAX, 1);
  138. if (ret)
  139. goto fail;
  140. return 0;
  141. fail:
  142. dev_err(&adev->dev, "failed to configure cs%u\n", cs);
  143. return ret;
  144. }
  145. static int pl172_parse_cs_config(struct amba_device *adev,
  146. struct device_node *np)
  147. {
  148. u32 cs;
  149. if (!of_property_read_u32(np, "mpmc,cs", &cs)) {
  150. if (cs >= PL172_MAX_CS) {
  151. dev_err(&adev->dev, "cs%u invalid\n", cs);
  152. return -EINVAL;
  153. }
  154. return pl172_setup_static(adev, np, cs);
  155. }
  156. dev_err(&adev->dev, "cs property required\n");
  157. return -EINVAL;
  158. }
  159. static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"};
  160. static const char * const pl175_revisions[] = {"r1"};
  161. static const char * const pl176_revisions[] = {"r0"};
  162. static int pl172_probe(struct amba_device *adev, const struct amba_id *id)
  163. {
  164. struct device_node *child_np, *np = adev->dev.of_node;
  165. struct device *dev = &adev->dev;
  166. static const char *rev = "?";
  167. struct pl172_data *pl172;
  168. int ret;
  169. if (amba_part(adev) == 0x172) {
  170. if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions))
  171. rev = pl172_revisions[amba_rev(adev)];
  172. } else if (amba_part(adev) == 0x175) {
  173. if (amba_rev(adev) < ARRAY_SIZE(pl175_revisions))
  174. rev = pl175_revisions[amba_rev(adev)];
  175. } else if (amba_part(adev) == 0x176) {
  176. if (amba_rev(adev) < ARRAY_SIZE(pl176_revisions))
  177. rev = pl176_revisions[amba_rev(adev)];
  178. }
  179. dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev);
  180. pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL);
  181. if (!pl172)
  182. return -ENOMEM;
  183. pl172->clk = devm_clk_get(dev, "mpmcclk");
  184. if (IS_ERR(pl172->clk)) {
  185. dev_err(dev, "no mpmcclk provided clock\n");
  186. return PTR_ERR(pl172->clk);
  187. }
  188. ret = clk_prepare_enable(pl172->clk);
  189. if (ret) {
  190. dev_err(dev, "unable to mpmcclk enable clock\n");
  191. return ret;
  192. }
  193. pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC;
  194. if (!pl172->rate) {
  195. dev_err(dev, "unable to get mpmcclk clock rate\n");
  196. ret = -EINVAL;
  197. goto err_clk_enable;
  198. }
  199. ret = amba_request_regions(adev, NULL);
  200. if (ret) {
  201. dev_err(dev, "unable to request AMBA regions\n");
  202. goto err_clk_enable;
  203. }
  204. pl172->base = devm_ioremap(dev, adev->res.start,
  205. resource_size(&adev->res));
  206. if (!pl172->base) {
  207. dev_err(dev, "ioremap failed\n");
  208. ret = -ENOMEM;
  209. goto err_no_ioremap;
  210. }
  211. amba_set_drvdata(adev, pl172);
  212. /*
  213. * Loop through each child node, which represent a chip select, and
  214. * configure parameters and timing. If successful; populate devices
  215. * under that node.
  216. */
  217. for_each_available_child_of_node(np, child_np) {
  218. ret = pl172_parse_cs_config(adev, child_np);
  219. if (ret)
  220. continue;
  221. of_platform_populate(child_np, NULL, NULL, dev);
  222. }
  223. return 0;
  224. err_no_ioremap:
  225. amba_release_regions(adev);
  226. err_clk_enable:
  227. clk_disable_unprepare(pl172->clk);
  228. return ret;
  229. }
  230. static void pl172_remove(struct amba_device *adev)
  231. {
  232. struct pl172_data *pl172 = amba_get_drvdata(adev);
  233. clk_disable_unprepare(pl172->clk);
  234. amba_release_regions(adev);
  235. }
  236. static const struct amba_id pl172_ids[] = {
  237. /* PrimeCell MPMC PL172, EMC found on NXP LPC18xx and LPC43xx */
  238. {
  239. .id = 0x07041172,
  240. .mask = 0x3f0fffff,
  241. },
  242. /* PrimeCell MPMC PL175, EMC found on NXP LPC32xx */
  243. {
  244. .id = 0x07041175,
  245. .mask = 0x3f0fffff,
  246. },
  247. /* PrimeCell MPMC PL176 */
  248. {
  249. .id = 0x89041176,
  250. .mask = 0xff0fffff,
  251. },
  252. { 0, 0 },
  253. };
  254. MODULE_DEVICE_TABLE(amba, pl172_ids);
  255. static struct amba_driver pl172_driver = {
  256. .drv = {
  257. .name = "memory-pl172",
  258. },
  259. .probe = pl172_probe,
  260. .remove = pl172_remove,
  261. .id_table = pl172_ids,
  262. };
  263. module_amba_driver(pl172_driver);
  264. MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
  265. MODULE_DESCRIPTION("PL172 Memory Controller Driver");
  266. MODULE_LICENSE("GPL v2");