omap-gpmc.c 70 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * GPMC support functions
  4. *
  5. * Copyright (C) 2005-2006 Nokia Corporation
  6. *
  7. * Author: Juha Yrjola
  8. *
  9. * Copyright (C) 2009 Texas Instruments
  10. * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11. */
  12. #include <linux/irq.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/err.h>
  16. #include <linux/clk.h>
  17. #include <linux/ioport.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/io.h>
  20. #include <linux/gpio/driver.h>
  21. #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
  22. #include <linux/gpio/machine.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/irqdomain.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/of.h>
  27. #include <linux/of_address.h>
  28. #include <linux/of_device.h>
  29. #include <linux/of_platform.h>
  30. #include <linux/omap-gpmc.h>
  31. #include <linux/pm_runtime.h>
  32. #include <linux/sizes.h>
  33. #include <linux/platform_data/mtd-nand-omap2.h>
  34. #define DEVICE_NAME "omap-gpmc"
  35. /* GPMC register offsets */
  36. #define GPMC_REVISION 0x00
  37. #define GPMC_SYSCONFIG 0x10
  38. #define GPMC_SYSSTATUS 0x14
  39. #define GPMC_IRQSTATUS 0x18
  40. #define GPMC_IRQENABLE 0x1c
  41. #define GPMC_TIMEOUT_CONTROL 0x40
  42. #define GPMC_ERR_ADDRESS 0x44
  43. #define GPMC_ERR_TYPE 0x48
  44. #define GPMC_CONFIG 0x50
  45. #define GPMC_STATUS 0x54
  46. #define GPMC_PREFETCH_CONFIG1 0x1e0
  47. #define GPMC_PREFETCH_CONFIG2 0x1e4
  48. #define GPMC_PREFETCH_CONTROL 0x1ec
  49. #define GPMC_PREFETCH_STATUS 0x1f0
  50. #define GPMC_ECC_CONFIG 0x1f4
  51. #define GPMC_ECC_CONTROL 0x1f8
  52. #define GPMC_ECC_SIZE_CONFIG 0x1fc
  53. #define GPMC_ECC1_RESULT 0x200
  54. #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
  55. #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
  56. #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
  57. #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
  58. #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
  59. #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
  60. #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
  61. /* GPMC ECC control settings */
  62. #define GPMC_ECC_CTRL_ECCCLEAR 0x100
  63. #define GPMC_ECC_CTRL_ECCDISABLE 0x000
  64. #define GPMC_ECC_CTRL_ECCREG1 0x001
  65. #define GPMC_ECC_CTRL_ECCREG2 0x002
  66. #define GPMC_ECC_CTRL_ECCREG3 0x003
  67. #define GPMC_ECC_CTRL_ECCREG4 0x004
  68. #define GPMC_ECC_CTRL_ECCREG5 0x005
  69. #define GPMC_ECC_CTRL_ECCREG6 0x006
  70. #define GPMC_ECC_CTRL_ECCREG7 0x007
  71. #define GPMC_ECC_CTRL_ECCREG8 0x008
  72. #define GPMC_ECC_CTRL_ECCREG9 0x009
  73. #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
  74. #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
  75. #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
  76. #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
  77. #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
  78. #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
  79. #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
  80. #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
  81. #define GPMC_CS0_OFFSET 0x60
  82. #define GPMC_CS_SIZE 0x30
  83. #define GPMC_BCH_SIZE 0x10
  84. /*
  85. * The first 1MB of GPMC address space is typically mapped to
  86. * the internal ROM. Never allocate the first page, to
  87. * facilitate bug detection; even if we didn't boot from ROM.
  88. * As GPMC minimum partition size is 16MB we can only start from
  89. * there.
  90. */
  91. #define GPMC_MEM_START 0x1000000
  92. #define GPMC_MEM_END 0x3FFFFFFF
  93. #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
  94. #define GPMC_SECTION_SHIFT 28 /* 128 MB */
  95. #define CS_NUM_SHIFT 24
  96. #define ENABLE_PREFETCH (0x1 << 7)
  97. #define DMA_MPU_MODE 2
  98. #define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
  99. #define GPMC_REVISION_MINOR(l) ((l) & 0xf)
  100. #define GPMC_HAS_WR_ACCESS 0x1
  101. #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
  102. #define GPMC_HAS_MUX_AAD 0x4
  103. #define GPMC_NR_WAITPINS 4
  104. #define GPMC_CS_CONFIG1 0x00
  105. #define GPMC_CS_CONFIG2 0x04
  106. #define GPMC_CS_CONFIG3 0x08
  107. #define GPMC_CS_CONFIG4 0x0c
  108. #define GPMC_CS_CONFIG5 0x10
  109. #define GPMC_CS_CONFIG6 0x14
  110. #define GPMC_CS_CONFIG7 0x18
  111. #define GPMC_CS_NAND_COMMAND 0x1c
  112. #define GPMC_CS_NAND_ADDRESS 0x20
  113. #define GPMC_CS_NAND_DATA 0x24
  114. /* Control Commands */
  115. #define GPMC_CONFIG_RDY_BSY 0x00000001
  116. #define GPMC_CONFIG_DEV_SIZE 0x00000002
  117. #define GPMC_CONFIG_DEV_TYPE 0x00000003
  118. #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
  119. #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
  120. #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
  121. #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
  122. #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
  123. #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
  124. #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
  125. #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
  126. /** CLKACTIVATIONTIME Max Ticks */
  127. #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
  128. #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
  129. /** ATTACHEDDEVICEPAGELENGTH Max Value */
  130. #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
  131. #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
  132. #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
  133. #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
  134. /** WAITMONITORINGTIME Max Ticks */
  135. #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
  136. #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
  137. #define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12)
  138. #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
  139. /** DEVICESIZE Max Value */
  140. #define GPMC_CONFIG1_DEVICESIZE_MAX 1
  141. #define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10)
  142. #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
  143. #define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8)
  144. #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
  145. #define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3)
  146. #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
  147. #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
  148. #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
  149. #define GPMC_CONFIG7_CSVALID (1 << 6)
  150. #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
  151. #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
  152. #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
  153. #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
  154. /* All CONFIG7 bits except reserved bits */
  155. #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
  156. GPMC_CONFIG7_CSVALID_MASK | \
  157. GPMC_CONFIG7_MASKADDRESS_MASK)
  158. #define GPMC_DEVICETYPE_NOR 0
  159. #define GPMC_DEVICETYPE_NAND 2
  160. #define GPMC_CONFIG_WRITEPROTECT 0x00000010
  161. #define WR_RD_PIN_MONITORING 0x00600000
  162. /* ECC commands */
  163. #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
  164. #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
  165. #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
  166. #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
  167. enum gpmc_clk_domain {
  168. GPMC_CD_FCLK,
  169. GPMC_CD_CLK
  170. };
  171. struct gpmc_cs_data {
  172. const char *name;
  173. #define GPMC_CS_RESERVED (1 << 0)
  174. u32 flags;
  175. struct resource mem;
  176. };
  177. /* Structure to save gpmc cs context */
  178. struct gpmc_cs_config {
  179. u32 config1;
  180. u32 config2;
  181. u32 config3;
  182. u32 config4;
  183. u32 config5;
  184. u32 config6;
  185. u32 config7;
  186. int is_valid;
  187. };
  188. /*
  189. * Structure to save/restore gpmc context
  190. * to support core off on OMAP3
  191. */
  192. struct omap3_gpmc_regs {
  193. u32 sysconfig;
  194. u32 irqenable;
  195. u32 timeout_ctrl;
  196. u32 config;
  197. u32 prefetch_config1;
  198. u32 prefetch_config2;
  199. u32 prefetch_control;
  200. struct gpmc_cs_config cs_context[GPMC_CS_NUM];
  201. };
  202. struct gpmc_device {
  203. struct device *dev;
  204. int irq;
  205. struct irq_chip irq_chip;
  206. struct gpio_chip gpio_chip;
  207. int nirqs;
  208. };
  209. static struct irq_domain *gpmc_irq_domain;
  210. static struct resource gpmc_mem_root;
  211. static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
  212. static DEFINE_SPINLOCK(gpmc_mem_lock);
  213. /* Define chip-selects as reserved by default until probe completes */
  214. static unsigned int gpmc_cs_num = GPMC_CS_NUM;
  215. static unsigned int gpmc_nr_waitpins;
  216. static unsigned int gpmc_capability;
  217. static void __iomem *gpmc_base;
  218. static struct clk *gpmc_l3_clk;
  219. static irqreturn_t gpmc_handle_irq(int irq, void *dev);
  220. static void gpmc_write_reg(int idx, u32 val)
  221. {
  222. writel_relaxed(val, gpmc_base + idx);
  223. }
  224. static u32 gpmc_read_reg(int idx)
  225. {
  226. return readl_relaxed(gpmc_base + idx);
  227. }
  228. void gpmc_cs_write_reg(int cs, int idx, u32 val)
  229. {
  230. void __iomem *reg_addr;
  231. reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  232. writel_relaxed(val, reg_addr);
  233. }
  234. static u32 gpmc_cs_read_reg(int cs, int idx)
  235. {
  236. void __iomem *reg_addr;
  237. reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  238. return readl_relaxed(reg_addr);
  239. }
  240. /* TODO: Add support for gpmc_fck to clock framework and use it */
  241. static unsigned long gpmc_get_fclk_period(void)
  242. {
  243. unsigned long rate = clk_get_rate(gpmc_l3_clk);
  244. rate /= 1000;
  245. rate = 1000000000 / rate; /* In picoseconds */
  246. return rate;
  247. }
  248. /**
  249. * gpmc_get_clk_period - get period of selected clock domain in ps
  250. * @cs: Chip Select Region.
  251. * @cd: Clock Domain.
  252. *
  253. * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
  254. * prior to calling this function with GPMC_CD_CLK.
  255. */
  256. static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
  257. {
  258. unsigned long tick_ps = gpmc_get_fclk_period();
  259. u32 l;
  260. int div;
  261. switch (cd) {
  262. case GPMC_CD_CLK:
  263. /* get current clk divider */
  264. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
  265. div = (l & 0x03) + 1;
  266. /* get GPMC_CLK period */
  267. tick_ps *= div;
  268. break;
  269. case GPMC_CD_FCLK:
  270. default:
  271. break;
  272. }
  273. return tick_ps;
  274. }
  275. static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
  276. enum gpmc_clk_domain cd)
  277. {
  278. unsigned long tick_ps;
  279. /* Calculate in picosecs to yield more exact results */
  280. tick_ps = gpmc_get_clk_period(cs, cd);
  281. return (time_ns * 1000 + tick_ps - 1) / tick_ps;
  282. }
  283. static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
  284. {
  285. return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
  286. }
  287. static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
  288. {
  289. unsigned long tick_ps;
  290. /* Calculate in picosecs to yield more exact results */
  291. tick_ps = gpmc_get_fclk_period();
  292. return (time_ps + tick_ps - 1) / tick_ps;
  293. }
  294. static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
  295. enum gpmc_clk_domain cd)
  296. {
  297. return ticks * gpmc_get_clk_period(cs, cd) / 1000;
  298. }
  299. unsigned int gpmc_ticks_to_ns(unsigned int ticks)
  300. {
  301. return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
  302. }
  303. static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
  304. {
  305. return ticks * gpmc_get_fclk_period();
  306. }
  307. static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
  308. {
  309. unsigned long ticks = gpmc_ps_to_ticks(time_ps);
  310. return ticks * gpmc_get_fclk_period();
  311. }
  312. static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
  313. {
  314. u32 l;
  315. l = gpmc_cs_read_reg(cs, reg);
  316. if (value)
  317. l |= mask;
  318. else
  319. l &= ~mask;
  320. gpmc_cs_write_reg(cs, reg, l);
  321. }
  322. static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
  323. {
  324. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
  325. GPMC_CONFIG1_TIME_PARA_GRAN,
  326. p->time_para_granularity);
  327. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
  328. GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
  329. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
  330. GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
  331. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
  332. GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
  333. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
  334. GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
  335. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
  336. GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
  337. p->cycle2cyclesamecsen);
  338. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
  339. GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
  340. p->cycle2cyclediffcsen);
  341. }
  342. #ifdef CONFIG_OMAP_GPMC_DEBUG
  343. /**
  344. * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
  345. * @cs: Chip Select Region
  346. * @reg: GPMC_CS_CONFIGn register offset.
  347. * @st_bit: Start Bit
  348. * @end_bit: End Bit. Must be >= @st_bit.
  349. * @max: Maximum parameter value (before optional @shift).
  350. * If 0, maximum is as high as @st_bit and @end_bit allow.
  351. * @name: DTS node name, w/o "gpmc,"
  352. * @cd: Clock Domain of timing parameter.
  353. * @shift: Parameter value left shifts @shift, which is then printed instead of value.
  354. * @raw: Raw Format Option.
  355. * raw format: gpmc,name = <value>
  356. * tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
  357. * Where x ns -- y ns result in the same tick value.
  358. * When @max is exceeded, "invalid" is printed inside comment.
  359. * @noval: Parameter values equal to 0 are not printed.
  360. * @return: Specified timing parameter (after optional @shift).
  361. *
  362. */
  363. static int get_gpmc_timing_reg(
  364. /* timing specifiers */
  365. int cs, int reg, int st_bit, int end_bit, int max,
  366. const char *name, const enum gpmc_clk_domain cd,
  367. /* value transform */
  368. int shift,
  369. /* format specifiers */
  370. bool raw, bool noval)
  371. {
  372. u32 l;
  373. int nr_bits;
  374. int mask;
  375. bool invalid;
  376. l = gpmc_cs_read_reg(cs, reg);
  377. nr_bits = end_bit - st_bit + 1;
  378. mask = (1 << nr_bits) - 1;
  379. l = (l >> st_bit) & mask;
  380. if (!max)
  381. max = mask;
  382. invalid = l > max;
  383. if (shift)
  384. l = (shift << l);
  385. if (noval && (l == 0))
  386. return 0;
  387. if (!raw) {
  388. /* DTS tick format for timings in ns */
  389. unsigned int time_ns;
  390. unsigned int time_ns_min = 0;
  391. if (l)
  392. time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
  393. time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
  394. pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
  395. name, time_ns, time_ns_min, time_ns, l,
  396. invalid ? "; invalid " : " ");
  397. } else {
  398. /* raw format */
  399. pr_info("gpmc,%s = <%u>;%s\n", name, l,
  400. invalid ? " /* invalid */" : "");
  401. }
  402. return l;
  403. }
  404. #define GPMC_PRINT_CONFIG(cs, config) \
  405. pr_info("cs%i %s: 0x%08x\n", cs, #config, \
  406. gpmc_cs_read_reg(cs, config))
  407. #define GPMC_GET_RAW(reg, st, end, field) \
  408. get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
  409. #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
  410. get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
  411. #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
  412. get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
  413. #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
  414. get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
  415. #define GPMC_GET_TICKS(reg, st, end, field) \
  416. get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
  417. #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
  418. get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
  419. #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
  420. get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
  421. static void gpmc_show_regs(int cs, const char *desc)
  422. {
  423. pr_info("gpmc cs%i %s:\n", cs, desc);
  424. GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
  425. GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
  426. GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
  427. GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
  428. GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
  429. GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
  430. }
  431. /*
  432. * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
  433. * see commit c9fb809.
  434. */
  435. static void gpmc_cs_show_timings(int cs, const char *desc)
  436. {
  437. gpmc_show_regs(cs, desc);
  438. pr_info("gpmc cs%i access configuration:\n", cs);
  439. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
  440. GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
  441. GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
  442. GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
  443. GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
  444. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
  445. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
  446. GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
  447. GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
  448. "burst-length");
  449. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
  450. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
  451. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
  452. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
  453. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
  454. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
  455. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
  456. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
  457. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
  458. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
  459. GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
  460. pr_info("gpmc cs%i timings configuration:\n", cs);
  461. GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
  462. GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
  463. GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
  464. GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
  465. GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
  466. GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
  467. if (gpmc_capability & GPMC_HAS_MUX_AAD) {
  468. GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
  469. GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
  470. "adv-aad-mux-rd-off-ns");
  471. GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
  472. "adv-aad-mux-wr-off-ns");
  473. }
  474. GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
  475. GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
  476. if (gpmc_capability & GPMC_HAS_MUX_AAD) {
  477. GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
  478. GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
  479. }
  480. GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
  481. GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
  482. GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
  483. GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
  484. GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
  485. GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
  486. GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
  487. GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
  488. GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
  489. GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
  490. "wait-monitoring-ns", GPMC_CD_CLK);
  491. GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
  492. GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
  493. "clk-activation-ns", GPMC_CD_FCLK);
  494. GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
  495. GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
  496. }
  497. #else
  498. static inline void gpmc_cs_show_timings(int cs, const char *desc)
  499. {
  500. }
  501. #endif
  502. /**
  503. * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
  504. * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
  505. * prior to calling this function with @cd equal to GPMC_CD_CLK.
  506. *
  507. * @cs: Chip Select Region.
  508. * @reg: GPMC_CS_CONFIGn register offset.
  509. * @st_bit: Start Bit
  510. * @end_bit: End Bit. Must be >= @st_bit.
  511. * @max: Maximum parameter value.
  512. * If 0, maximum is as high as @st_bit and @end_bit allow.
  513. * @time: Timing parameter in ns.
  514. * @cd: Timing parameter clock domain.
  515. * @name: Timing parameter name.
  516. * @return: 0 on success, -1 on error.
  517. */
  518. static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
  519. int time, enum gpmc_clk_domain cd, const char *name)
  520. {
  521. u32 l;
  522. int ticks, mask, nr_bits;
  523. if (time == 0)
  524. ticks = 0;
  525. else
  526. ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
  527. nr_bits = end_bit - st_bit + 1;
  528. mask = (1 << nr_bits) - 1;
  529. if (!max)
  530. max = mask;
  531. if (ticks > max) {
  532. pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
  533. __func__, cs, name, time, ticks, max);
  534. return -1;
  535. }
  536. l = gpmc_cs_read_reg(cs, reg);
  537. #ifdef CONFIG_OMAP_GPMC_DEBUG
  538. pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
  539. cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
  540. (l >> st_bit) & mask, time);
  541. #endif
  542. l &= ~(mask << st_bit);
  543. l |= ticks << st_bit;
  544. gpmc_cs_write_reg(cs, reg, l);
  545. return 0;
  546. }
  547. /**
  548. * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
  549. * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
  550. * read --> don't sample bus too early
  551. * write --> data is longer on bus
  552. *
  553. * Formula:
  554. * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
  555. * / waitmonitoring_ticks)
  556. * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
  557. * div <= 0 check.
  558. *
  559. * @wait_monitoring: WAITMONITORINGTIME in ns.
  560. * @return: -1 on failure to scale, else proper divider > 0.
  561. */
  562. static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
  563. {
  564. int div = gpmc_ns_to_ticks(wait_monitoring);
  565. div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
  566. div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
  567. if (div > 4)
  568. return -1;
  569. if (div <= 0)
  570. div = 1;
  571. return div;
  572. }
  573. /**
  574. * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
  575. * @sync_clk: GPMC_CLK period in ps.
  576. * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
  577. * Else, returns -1.
  578. */
  579. int gpmc_calc_divider(unsigned int sync_clk)
  580. {
  581. int div = gpmc_ps_to_ticks(sync_clk);
  582. if (div > 4)
  583. return -1;
  584. if (div <= 0)
  585. div = 1;
  586. return div;
  587. }
  588. /**
  589. * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
  590. * @cs: Chip Select Region.
  591. * @t: GPMC timing parameters.
  592. * @s: GPMC timing settings.
  593. * @return: 0 on success, -1 on error.
  594. */
  595. int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
  596. const struct gpmc_settings *s)
  597. {
  598. int div, ret;
  599. u32 l;
  600. div = gpmc_calc_divider(t->sync_clk);
  601. if (div < 0)
  602. return -EINVAL;
  603. /*
  604. * See if we need to change the divider for waitmonitoringtime.
  605. *
  606. * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
  607. * pure asynchronous accesses, i.e. both read and write asynchronous.
  608. * However, only do so if WAITMONITORINGTIME is actually used, i.e.
  609. * either WAITREADMONITORING or WAITWRITEMONITORING is set.
  610. *
  611. * This statement must not change div to scale async WAITMONITORINGTIME
  612. * to protect mixed synchronous and asynchronous accesses.
  613. *
  614. * We raise an error later if WAITMONITORINGTIME does not fit.
  615. */
  616. if (!s->sync_read && !s->sync_write &&
  617. (s->wait_on_read || s->wait_on_write)
  618. ) {
  619. div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
  620. if (div < 0) {
  621. pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
  622. __func__,
  623. t->wait_monitoring
  624. );
  625. return -ENXIO;
  626. }
  627. }
  628. ret = 0;
  629. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
  630. GPMC_CD_FCLK, "cs_on");
  631. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
  632. GPMC_CD_FCLK, "cs_rd_off");
  633. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
  634. GPMC_CD_FCLK, "cs_wr_off");
  635. if (ret)
  636. return -ENXIO;
  637. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
  638. GPMC_CD_FCLK, "adv_on");
  639. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
  640. GPMC_CD_FCLK, "adv_rd_off");
  641. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
  642. GPMC_CD_FCLK, "adv_wr_off");
  643. if (ret)
  644. return -ENXIO;
  645. if (gpmc_capability & GPMC_HAS_MUX_AAD) {
  646. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
  647. t->adv_aad_mux_on, GPMC_CD_FCLK,
  648. "adv_aad_mux_on");
  649. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
  650. t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
  651. "adv_aad_mux_rd_off");
  652. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
  653. t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
  654. "adv_aad_mux_wr_off");
  655. if (ret)
  656. return -ENXIO;
  657. }
  658. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
  659. GPMC_CD_FCLK, "oe_on");
  660. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
  661. GPMC_CD_FCLK, "oe_off");
  662. if (gpmc_capability & GPMC_HAS_MUX_AAD) {
  663. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
  664. t->oe_aad_mux_on, GPMC_CD_FCLK,
  665. "oe_aad_mux_on");
  666. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
  667. t->oe_aad_mux_off, GPMC_CD_FCLK,
  668. "oe_aad_mux_off");
  669. }
  670. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
  671. GPMC_CD_FCLK, "we_on");
  672. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
  673. GPMC_CD_FCLK, "we_off");
  674. if (ret)
  675. return -ENXIO;
  676. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
  677. GPMC_CD_FCLK, "rd_cycle");
  678. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
  679. GPMC_CD_FCLK, "wr_cycle");
  680. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
  681. GPMC_CD_FCLK, "access");
  682. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
  683. t->page_burst_access, GPMC_CD_FCLK,
  684. "page_burst_access");
  685. if (ret)
  686. return -ENXIO;
  687. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
  688. t->bus_turnaround, GPMC_CD_FCLK,
  689. "bus_turnaround");
  690. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
  691. t->cycle2cycle_delay, GPMC_CD_FCLK,
  692. "cycle2cycle_delay");
  693. if (ret)
  694. return -ENXIO;
  695. if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
  696. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
  697. t->wr_data_mux_bus, GPMC_CD_FCLK,
  698. "wr_data_mux_bus");
  699. if (ret)
  700. return -ENXIO;
  701. }
  702. if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
  703. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
  704. t->wr_access, GPMC_CD_FCLK,
  705. "wr_access");
  706. if (ret)
  707. return -ENXIO;
  708. }
  709. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
  710. l &= ~0x03;
  711. l |= (div - 1);
  712. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
  713. ret = 0;
  714. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
  715. GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
  716. t->wait_monitoring, GPMC_CD_CLK,
  717. "wait_monitoring");
  718. ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
  719. GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
  720. t->clk_activation, GPMC_CD_FCLK,
  721. "clk_activation");
  722. if (ret)
  723. return -ENXIO;
  724. #ifdef CONFIG_OMAP_GPMC_DEBUG
  725. pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
  726. cs, (div * gpmc_get_fclk_period()) / 1000, div);
  727. #endif
  728. gpmc_cs_bool_timings(cs, &t->bool_timings);
  729. gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
  730. return 0;
  731. }
  732. static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
  733. {
  734. u32 l;
  735. u32 mask;
  736. /*
  737. * Ensure that base address is aligned on a
  738. * boundary equal to or greater than size.
  739. */
  740. if (base & (size - 1))
  741. return -EINVAL;
  742. base >>= GPMC_CHUNK_SHIFT;
  743. mask = (1 << GPMC_SECTION_SHIFT) - size;
  744. mask >>= GPMC_CHUNK_SHIFT;
  745. mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
  746. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  747. l &= ~GPMC_CONFIG7_MASK;
  748. l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
  749. l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
  750. l |= GPMC_CONFIG7_CSVALID;
  751. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
  752. return 0;
  753. }
  754. static void gpmc_cs_enable_mem(int cs)
  755. {
  756. u32 l;
  757. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  758. l |= GPMC_CONFIG7_CSVALID;
  759. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
  760. }
  761. static void gpmc_cs_disable_mem(int cs)
  762. {
  763. u32 l;
  764. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  765. l &= ~GPMC_CONFIG7_CSVALID;
  766. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
  767. }
  768. static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
  769. {
  770. u32 l;
  771. u32 mask;
  772. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  773. *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
  774. mask = (l >> 8) & 0x0f;
  775. *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
  776. }
  777. static int gpmc_cs_mem_enabled(int cs)
  778. {
  779. u32 l;
  780. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  781. return l & GPMC_CONFIG7_CSVALID;
  782. }
  783. static void gpmc_cs_set_reserved(int cs, int reserved)
  784. {
  785. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  786. gpmc->flags |= GPMC_CS_RESERVED;
  787. }
  788. static bool gpmc_cs_reserved(int cs)
  789. {
  790. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  791. return gpmc->flags & GPMC_CS_RESERVED;
  792. }
  793. static unsigned long gpmc_mem_align(unsigned long size)
  794. {
  795. int order;
  796. size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
  797. order = GPMC_CHUNK_SHIFT - 1;
  798. do {
  799. size >>= 1;
  800. order++;
  801. } while (size);
  802. size = 1 << order;
  803. return size;
  804. }
  805. static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
  806. {
  807. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  808. struct resource *res = &gpmc->mem;
  809. int r;
  810. size = gpmc_mem_align(size);
  811. spin_lock(&gpmc_mem_lock);
  812. res->start = base;
  813. res->end = base + size - 1;
  814. r = request_resource(&gpmc_mem_root, res);
  815. spin_unlock(&gpmc_mem_lock);
  816. return r;
  817. }
  818. static int gpmc_cs_delete_mem(int cs)
  819. {
  820. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  821. struct resource *res = &gpmc->mem;
  822. int r;
  823. spin_lock(&gpmc_mem_lock);
  824. r = release_resource(res);
  825. res->start = 0;
  826. res->end = 0;
  827. spin_unlock(&gpmc_mem_lock);
  828. return r;
  829. }
  830. int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
  831. {
  832. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  833. struct resource *res = &gpmc->mem;
  834. int r = -1;
  835. if (cs >= gpmc_cs_num) {
  836. pr_err("%s: requested chip-select is disabled\n", __func__);
  837. return -ENODEV;
  838. }
  839. size = gpmc_mem_align(size);
  840. if (size > (1 << GPMC_SECTION_SHIFT))
  841. return -ENOMEM;
  842. spin_lock(&gpmc_mem_lock);
  843. if (gpmc_cs_reserved(cs)) {
  844. r = -EBUSY;
  845. goto out;
  846. }
  847. if (gpmc_cs_mem_enabled(cs))
  848. r = adjust_resource(res, res->start & ~(size - 1), size);
  849. if (r < 0)
  850. r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
  851. size, NULL, NULL);
  852. if (r < 0)
  853. goto out;
  854. /* Disable CS while changing base address and size mask */
  855. gpmc_cs_disable_mem(cs);
  856. r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
  857. if (r < 0) {
  858. release_resource(res);
  859. goto out;
  860. }
  861. /* Enable CS */
  862. gpmc_cs_enable_mem(cs);
  863. *base = res->start;
  864. gpmc_cs_set_reserved(cs, 1);
  865. out:
  866. spin_unlock(&gpmc_mem_lock);
  867. return r;
  868. }
  869. EXPORT_SYMBOL(gpmc_cs_request);
  870. void gpmc_cs_free(int cs)
  871. {
  872. struct gpmc_cs_data *gpmc;
  873. struct resource *res;
  874. spin_lock(&gpmc_mem_lock);
  875. if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
  876. WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
  877. spin_unlock(&gpmc_mem_lock);
  878. return;
  879. }
  880. gpmc = &gpmc_cs[cs];
  881. res = &gpmc->mem;
  882. gpmc_cs_disable_mem(cs);
  883. if (res->flags)
  884. release_resource(res);
  885. gpmc_cs_set_reserved(cs, 0);
  886. spin_unlock(&gpmc_mem_lock);
  887. }
  888. EXPORT_SYMBOL(gpmc_cs_free);
  889. /**
  890. * gpmc_configure - write request to configure gpmc
  891. * @cmd: command type
  892. * @wval: value to write
  893. * @return status of the operation
  894. */
  895. int gpmc_configure(int cmd, int wval)
  896. {
  897. u32 regval;
  898. switch (cmd) {
  899. case GPMC_CONFIG_WP:
  900. regval = gpmc_read_reg(GPMC_CONFIG);
  901. if (wval)
  902. regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
  903. else
  904. regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
  905. gpmc_write_reg(GPMC_CONFIG, regval);
  906. break;
  907. default:
  908. pr_err("%s: command not supported\n", __func__);
  909. return -EINVAL;
  910. }
  911. return 0;
  912. }
  913. EXPORT_SYMBOL(gpmc_configure);
  914. static bool gpmc_nand_writebuffer_empty(void)
  915. {
  916. if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
  917. return true;
  918. return false;
  919. }
  920. static struct gpmc_nand_ops nand_ops = {
  921. .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
  922. };
  923. /**
  924. * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
  925. * @reg: the GPMC NAND register map exclusive for NAND use.
  926. * @cs: GPMC chip select number on which the NAND sits. The
  927. * register map returned will be specific to this chip select.
  928. *
  929. * Returns NULL on error e.g. invalid cs.
  930. */
  931. struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
  932. {
  933. int i;
  934. if (cs >= gpmc_cs_num)
  935. return NULL;
  936. reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
  937. GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
  938. reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
  939. GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
  940. reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
  941. GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
  942. reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
  943. reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
  944. reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
  945. reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
  946. reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
  947. reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
  948. reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
  949. reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
  950. for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
  951. reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
  952. GPMC_BCH_SIZE * i;
  953. reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
  954. GPMC_BCH_SIZE * i;
  955. reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
  956. GPMC_BCH_SIZE * i;
  957. reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
  958. GPMC_BCH_SIZE * i;
  959. reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
  960. i * GPMC_BCH_SIZE;
  961. reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
  962. i * GPMC_BCH_SIZE;
  963. reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
  964. i * GPMC_BCH_SIZE;
  965. }
  966. return &nand_ops;
  967. }
  968. EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
  969. static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
  970. struct gpmc_settings *s,
  971. int freq, int latency)
  972. {
  973. struct gpmc_device_timings dev_t;
  974. const int t_cer = 15;
  975. const int t_avdp = 12;
  976. const int t_cez = 20; /* max of t_cez, t_oez */
  977. const int t_wpl = 40;
  978. const int t_wph = 30;
  979. int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
  980. switch (freq) {
  981. case 104:
  982. min_gpmc_clk_period = 9600; /* 104 MHz */
  983. t_ces = 3;
  984. t_avds = 4;
  985. t_avdh = 2;
  986. t_ach = 3;
  987. t_aavdh = 6;
  988. t_rdyo = 6;
  989. break;
  990. case 83:
  991. min_gpmc_clk_period = 12000; /* 83 MHz */
  992. t_ces = 5;
  993. t_avds = 4;
  994. t_avdh = 2;
  995. t_ach = 6;
  996. t_aavdh = 6;
  997. t_rdyo = 9;
  998. break;
  999. case 66:
  1000. min_gpmc_clk_period = 15000; /* 66 MHz */
  1001. t_ces = 6;
  1002. t_avds = 5;
  1003. t_avdh = 2;
  1004. t_ach = 6;
  1005. t_aavdh = 6;
  1006. t_rdyo = 11;
  1007. break;
  1008. default:
  1009. min_gpmc_clk_period = 18500; /* 54 MHz */
  1010. t_ces = 7;
  1011. t_avds = 7;
  1012. t_avdh = 7;
  1013. t_ach = 9;
  1014. t_aavdh = 7;
  1015. t_rdyo = 15;
  1016. break;
  1017. }
  1018. /* Set synchronous read timings */
  1019. memset(&dev_t, 0, sizeof(dev_t));
  1020. if (!s->sync_write) {
  1021. dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
  1022. dev_t.t_wpl = t_wpl * 1000;
  1023. dev_t.t_wph = t_wph * 1000;
  1024. dev_t.t_aavdh = t_aavdh * 1000;
  1025. }
  1026. dev_t.ce_xdelay = true;
  1027. dev_t.avd_xdelay = true;
  1028. dev_t.oe_xdelay = true;
  1029. dev_t.we_xdelay = true;
  1030. dev_t.clk = min_gpmc_clk_period;
  1031. dev_t.t_bacc = dev_t.clk;
  1032. dev_t.t_ces = t_ces * 1000;
  1033. dev_t.t_avds = t_avds * 1000;
  1034. dev_t.t_avdh = t_avdh * 1000;
  1035. dev_t.t_ach = t_ach * 1000;
  1036. dev_t.cyc_iaa = (latency + 1);
  1037. dev_t.t_cez_r = t_cez * 1000;
  1038. dev_t.t_cez_w = dev_t.t_cez_r;
  1039. dev_t.cyc_aavdh_oe = 1;
  1040. dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
  1041. gpmc_calc_timings(t, s, &dev_t);
  1042. }
  1043. int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
  1044. int latency,
  1045. struct gpmc_onenand_info *info)
  1046. {
  1047. int ret;
  1048. struct gpmc_timings gpmc_t;
  1049. struct gpmc_settings gpmc_s;
  1050. gpmc_read_settings_dt(dev->of_node, &gpmc_s);
  1051. info->sync_read = gpmc_s.sync_read;
  1052. info->sync_write = gpmc_s.sync_write;
  1053. info->burst_len = gpmc_s.burst_len;
  1054. if (!gpmc_s.sync_read && !gpmc_s.sync_write)
  1055. return 0;
  1056. gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
  1057. ret = gpmc_cs_program_settings(cs, &gpmc_s);
  1058. if (ret < 0)
  1059. return ret;
  1060. return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
  1061. }
  1062. EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
  1063. int gpmc_get_client_irq(unsigned int irq_config)
  1064. {
  1065. if (!gpmc_irq_domain) {
  1066. pr_warn("%s called before GPMC IRQ domain available\n",
  1067. __func__);
  1068. return 0;
  1069. }
  1070. /* we restrict this to NAND IRQs only */
  1071. if (irq_config >= GPMC_NR_NAND_IRQS)
  1072. return 0;
  1073. return irq_create_mapping(gpmc_irq_domain, irq_config);
  1074. }
  1075. static int gpmc_irq_endis(unsigned long hwirq, bool endis)
  1076. {
  1077. u32 regval;
  1078. /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
  1079. if (hwirq >= GPMC_NR_NAND_IRQS)
  1080. hwirq += 8 - GPMC_NR_NAND_IRQS;
  1081. regval = gpmc_read_reg(GPMC_IRQENABLE);
  1082. if (endis)
  1083. regval |= BIT(hwirq);
  1084. else
  1085. regval &= ~BIT(hwirq);
  1086. gpmc_write_reg(GPMC_IRQENABLE, regval);
  1087. return 0;
  1088. }
  1089. static void gpmc_irq_disable(struct irq_data *p)
  1090. {
  1091. gpmc_irq_endis(p->hwirq, false);
  1092. }
  1093. static void gpmc_irq_enable(struct irq_data *p)
  1094. {
  1095. gpmc_irq_endis(p->hwirq, true);
  1096. }
  1097. static void gpmc_irq_mask(struct irq_data *d)
  1098. {
  1099. gpmc_irq_endis(d->hwirq, false);
  1100. }
  1101. static void gpmc_irq_unmask(struct irq_data *d)
  1102. {
  1103. gpmc_irq_endis(d->hwirq, true);
  1104. }
  1105. static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
  1106. {
  1107. u32 regval;
  1108. /* NAND IRQs polarity is not configurable */
  1109. if (hwirq < GPMC_NR_NAND_IRQS)
  1110. return;
  1111. /* WAITPIN starts at BIT 8 */
  1112. hwirq += 8 - GPMC_NR_NAND_IRQS;
  1113. regval = gpmc_read_reg(GPMC_CONFIG);
  1114. if (rising_edge)
  1115. regval &= ~BIT(hwirq);
  1116. else
  1117. regval |= BIT(hwirq);
  1118. gpmc_write_reg(GPMC_CONFIG, regval);
  1119. }
  1120. static void gpmc_irq_ack(struct irq_data *d)
  1121. {
  1122. unsigned int hwirq = d->hwirq;
  1123. /* skip reserved bits */
  1124. if (hwirq >= GPMC_NR_NAND_IRQS)
  1125. hwirq += 8 - GPMC_NR_NAND_IRQS;
  1126. /* Setting bit to 1 clears (or Acks) the interrupt */
  1127. gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
  1128. }
  1129. static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
  1130. {
  1131. /* can't set type for NAND IRQs */
  1132. if (d->hwirq < GPMC_NR_NAND_IRQS)
  1133. return -EINVAL;
  1134. /* We can support either rising or falling edge at a time */
  1135. if (trigger == IRQ_TYPE_EDGE_FALLING)
  1136. gpmc_irq_edge_config(d->hwirq, false);
  1137. else if (trigger == IRQ_TYPE_EDGE_RISING)
  1138. gpmc_irq_edge_config(d->hwirq, true);
  1139. else
  1140. return -EINVAL;
  1141. return 0;
  1142. }
  1143. static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
  1144. irq_hw_number_t hw)
  1145. {
  1146. struct gpmc_device *gpmc = d->host_data;
  1147. irq_set_chip_data(virq, gpmc);
  1148. if (hw < GPMC_NR_NAND_IRQS) {
  1149. irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
  1150. irq_set_chip_and_handler(virq, &gpmc->irq_chip,
  1151. handle_simple_irq);
  1152. } else {
  1153. irq_set_chip_and_handler(virq, &gpmc->irq_chip,
  1154. handle_edge_irq);
  1155. }
  1156. return 0;
  1157. }
  1158. static const struct irq_domain_ops gpmc_irq_domain_ops = {
  1159. .map = gpmc_irq_map,
  1160. .xlate = irq_domain_xlate_twocell,
  1161. };
  1162. static irqreturn_t gpmc_handle_irq(int irq, void *data)
  1163. {
  1164. int hwirq, virq;
  1165. u32 regval, regvalx;
  1166. struct gpmc_device *gpmc = data;
  1167. regval = gpmc_read_reg(GPMC_IRQSTATUS);
  1168. regvalx = regval;
  1169. if (!regval)
  1170. return IRQ_NONE;
  1171. for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
  1172. /* skip reserved status bits */
  1173. if (hwirq == GPMC_NR_NAND_IRQS)
  1174. regvalx >>= 8 - GPMC_NR_NAND_IRQS;
  1175. if (regvalx & BIT(hwirq)) {
  1176. virq = irq_find_mapping(gpmc_irq_domain, hwirq);
  1177. if (!virq) {
  1178. dev_warn(gpmc->dev,
  1179. "spurious irq detected hwirq %d, virq %d\n",
  1180. hwirq, virq);
  1181. }
  1182. generic_handle_irq(virq);
  1183. }
  1184. }
  1185. gpmc_write_reg(GPMC_IRQSTATUS, regval);
  1186. return IRQ_HANDLED;
  1187. }
  1188. static int gpmc_setup_irq(struct gpmc_device *gpmc)
  1189. {
  1190. u32 regval;
  1191. int rc;
  1192. /* Disable interrupts */
  1193. gpmc_write_reg(GPMC_IRQENABLE, 0);
  1194. /* clear interrupts */
  1195. regval = gpmc_read_reg(GPMC_IRQSTATUS);
  1196. gpmc_write_reg(GPMC_IRQSTATUS, regval);
  1197. gpmc->irq_chip.name = "gpmc";
  1198. gpmc->irq_chip.irq_enable = gpmc_irq_enable;
  1199. gpmc->irq_chip.irq_disable = gpmc_irq_disable;
  1200. gpmc->irq_chip.irq_ack = gpmc_irq_ack;
  1201. gpmc->irq_chip.irq_mask = gpmc_irq_mask;
  1202. gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
  1203. gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
  1204. gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
  1205. gpmc->nirqs,
  1206. &gpmc_irq_domain_ops,
  1207. gpmc);
  1208. if (!gpmc_irq_domain) {
  1209. dev_err(gpmc->dev, "IRQ domain add failed\n");
  1210. return -ENODEV;
  1211. }
  1212. rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
  1213. if (rc) {
  1214. dev_err(gpmc->dev, "failed to request irq %d: %d\n",
  1215. gpmc->irq, rc);
  1216. irq_domain_remove(gpmc_irq_domain);
  1217. gpmc_irq_domain = NULL;
  1218. }
  1219. return rc;
  1220. }
  1221. static int gpmc_free_irq(struct gpmc_device *gpmc)
  1222. {
  1223. int hwirq;
  1224. free_irq(gpmc->irq, gpmc);
  1225. for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
  1226. irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
  1227. irq_domain_remove(gpmc_irq_domain);
  1228. gpmc_irq_domain = NULL;
  1229. return 0;
  1230. }
  1231. static void gpmc_mem_exit(void)
  1232. {
  1233. int cs;
  1234. for (cs = 0; cs < gpmc_cs_num; cs++) {
  1235. if (!gpmc_cs_mem_enabled(cs))
  1236. continue;
  1237. gpmc_cs_delete_mem(cs);
  1238. }
  1239. }
  1240. static void gpmc_mem_init(void)
  1241. {
  1242. int cs;
  1243. gpmc_mem_root.start = GPMC_MEM_START;
  1244. gpmc_mem_root.end = GPMC_MEM_END;
  1245. /* Reserve all regions that has been set up by bootloader */
  1246. for (cs = 0; cs < gpmc_cs_num; cs++) {
  1247. u32 base, size;
  1248. if (!gpmc_cs_mem_enabled(cs))
  1249. continue;
  1250. gpmc_cs_get_memconf(cs, &base, &size);
  1251. if (gpmc_cs_insert_mem(cs, base, size)) {
  1252. pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
  1253. __func__, cs, base, base + size);
  1254. gpmc_cs_disable_mem(cs);
  1255. }
  1256. }
  1257. }
  1258. static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
  1259. {
  1260. u32 temp;
  1261. int div;
  1262. div = gpmc_calc_divider(sync_clk);
  1263. temp = gpmc_ps_to_ticks(time_ps);
  1264. temp = (temp + div - 1) / div;
  1265. return gpmc_ticks_to_ps(temp * div);
  1266. }
  1267. /* XXX: can the cycles be avoided ? */
  1268. static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
  1269. struct gpmc_device_timings *dev_t,
  1270. bool mux)
  1271. {
  1272. u32 temp;
  1273. /* adv_rd_off */
  1274. temp = dev_t->t_avdp_r;
  1275. /* XXX: mux check required ? */
  1276. if (mux) {
  1277. /* XXX: t_avdp not to be required for sync, only added for tusb
  1278. * this indirectly necessitates requirement of t_avdp_r and
  1279. * t_avdp_w instead of having a single t_avdp
  1280. */
  1281. temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
  1282. temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
  1283. }
  1284. gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
  1285. /* oe_on */
  1286. temp = dev_t->t_oeasu; /* XXX: remove this ? */
  1287. if (mux) {
  1288. temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
  1289. temp = max_t(u32, temp, gpmc_t->adv_rd_off +
  1290. gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
  1291. }
  1292. gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
  1293. /* access */
  1294. /* XXX: any scope for improvement ?, by combining oe_on
  1295. * and clk_activation, need to check whether
  1296. * access = clk_activation + round to sync clk ?
  1297. */
  1298. temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
  1299. temp += gpmc_t->clk_activation;
  1300. if (dev_t->cyc_oe)
  1301. temp = max_t(u32, temp, gpmc_t->oe_on +
  1302. gpmc_ticks_to_ps(dev_t->cyc_oe));
  1303. gpmc_t->access = gpmc_round_ps_to_ticks(temp);
  1304. gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
  1305. gpmc_t->cs_rd_off = gpmc_t->oe_off;
  1306. /* rd_cycle */
  1307. temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
  1308. temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
  1309. gpmc_t->access;
  1310. /* XXX: barter t_ce_rdyz with t_cez_r ? */
  1311. if (dev_t->t_ce_rdyz)
  1312. temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
  1313. gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
  1314. return 0;
  1315. }
  1316. static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
  1317. struct gpmc_device_timings *dev_t,
  1318. bool mux)
  1319. {
  1320. u32 temp;
  1321. /* adv_wr_off */
  1322. temp = dev_t->t_avdp_w;
  1323. if (mux) {
  1324. temp = max_t(u32, temp,
  1325. gpmc_t->clk_activation + dev_t->t_avdh);
  1326. temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
  1327. }
  1328. gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
  1329. /* wr_data_mux_bus */
  1330. temp = max_t(u32, dev_t->t_weasu,
  1331. gpmc_t->clk_activation + dev_t->t_rdyo);
  1332. /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
  1333. * and in that case remember to handle we_on properly
  1334. */
  1335. if (mux) {
  1336. temp = max_t(u32, temp,
  1337. gpmc_t->adv_wr_off + dev_t->t_aavdh);
  1338. temp = max_t(u32, temp, gpmc_t->adv_wr_off +
  1339. gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
  1340. }
  1341. gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
  1342. /* we_on */
  1343. if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
  1344. gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
  1345. else
  1346. gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
  1347. /* wr_access */
  1348. /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
  1349. gpmc_t->wr_access = gpmc_t->access;
  1350. /* we_off */
  1351. temp = gpmc_t->we_on + dev_t->t_wpl;
  1352. temp = max_t(u32, temp,
  1353. gpmc_t->wr_access + gpmc_ticks_to_ps(1));
  1354. temp = max_t(u32, temp,
  1355. gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
  1356. gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
  1357. gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
  1358. dev_t->t_wph);
  1359. /* wr_cycle */
  1360. temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
  1361. temp += gpmc_t->wr_access;
  1362. /* XXX: barter t_ce_rdyz with t_cez_w ? */
  1363. if (dev_t->t_ce_rdyz)
  1364. temp = max_t(u32, temp,
  1365. gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
  1366. gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
  1367. return 0;
  1368. }
  1369. static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
  1370. struct gpmc_device_timings *dev_t,
  1371. bool mux)
  1372. {
  1373. u32 temp;
  1374. /* adv_rd_off */
  1375. temp = dev_t->t_avdp_r;
  1376. if (mux)
  1377. temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
  1378. gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
  1379. /* oe_on */
  1380. temp = dev_t->t_oeasu;
  1381. if (mux)
  1382. temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
  1383. gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
  1384. /* access */
  1385. temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
  1386. gpmc_t->oe_on + dev_t->t_oe);
  1387. temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
  1388. temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
  1389. gpmc_t->access = gpmc_round_ps_to_ticks(temp);
  1390. gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
  1391. gpmc_t->cs_rd_off = gpmc_t->oe_off;
  1392. /* rd_cycle */
  1393. temp = max_t(u32, dev_t->t_rd_cycle,
  1394. gpmc_t->cs_rd_off + dev_t->t_cez_r);
  1395. temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
  1396. gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
  1397. return 0;
  1398. }
  1399. static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
  1400. struct gpmc_device_timings *dev_t,
  1401. bool mux)
  1402. {
  1403. u32 temp;
  1404. /* adv_wr_off */
  1405. temp = dev_t->t_avdp_w;
  1406. if (mux)
  1407. temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
  1408. gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
  1409. /* wr_data_mux_bus */
  1410. temp = dev_t->t_weasu;
  1411. if (mux) {
  1412. temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
  1413. temp = max_t(u32, temp, gpmc_t->adv_wr_off +
  1414. gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
  1415. }
  1416. gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
  1417. /* we_on */
  1418. if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
  1419. gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
  1420. else
  1421. gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
  1422. /* we_off */
  1423. temp = gpmc_t->we_on + dev_t->t_wpl;
  1424. gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
  1425. gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
  1426. dev_t->t_wph);
  1427. /* wr_cycle */
  1428. temp = max_t(u32, dev_t->t_wr_cycle,
  1429. gpmc_t->cs_wr_off + dev_t->t_cez_w);
  1430. gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
  1431. return 0;
  1432. }
  1433. static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
  1434. struct gpmc_device_timings *dev_t)
  1435. {
  1436. u32 temp;
  1437. gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
  1438. gpmc_get_fclk_period();
  1439. gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
  1440. dev_t->t_bacc,
  1441. gpmc_t->sync_clk);
  1442. temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
  1443. gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
  1444. if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
  1445. return 0;
  1446. if (dev_t->ce_xdelay)
  1447. gpmc_t->bool_timings.cs_extra_delay = true;
  1448. if (dev_t->avd_xdelay)
  1449. gpmc_t->bool_timings.adv_extra_delay = true;
  1450. if (dev_t->oe_xdelay)
  1451. gpmc_t->bool_timings.oe_extra_delay = true;
  1452. if (dev_t->we_xdelay)
  1453. gpmc_t->bool_timings.we_extra_delay = true;
  1454. return 0;
  1455. }
  1456. static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
  1457. struct gpmc_device_timings *dev_t,
  1458. bool sync)
  1459. {
  1460. u32 temp;
  1461. /* cs_on */
  1462. gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
  1463. /* adv_on */
  1464. temp = dev_t->t_avdasu;
  1465. if (dev_t->t_ce_avd)
  1466. temp = max_t(u32, temp,
  1467. gpmc_t->cs_on + dev_t->t_ce_avd);
  1468. gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
  1469. if (sync)
  1470. gpmc_calc_sync_common_timings(gpmc_t, dev_t);
  1471. return 0;
  1472. }
  1473. /*
  1474. * TODO: remove this function once all peripherals are confirmed to
  1475. * work with generic timing. Simultaneously gpmc_cs_set_timings()
  1476. * has to be modified to handle timings in ps instead of ns
  1477. */
  1478. static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
  1479. {
  1480. t->cs_on /= 1000;
  1481. t->cs_rd_off /= 1000;
  1482. t->cs_wr_off /= 1000;
  1483. t->adv_on /= 1000;
  1484. t->adv_rd_off /= 1000;
  1485. t->adv_wr_off /= 1000;
  1486. t->we_on /= 1000;
  1487. t->we_off /= 1000;
  1488. t->oe_on /= 1000;
  1489. t->oe_off /= 1000;
  1490. t->page_burst_access /= 1000;
  1491. t->access /= 1000;
  1492. t->rd_cycle /= 1000;
  1493. t->wr_cycle /= 1000;
  1494. t->bus_turnaround /= 1000;
  1495. t->cycle2cycle_delay /= 1000;
  1496. t->wait_monitoring /= 1000;
  1497. t->clk_activation /= 1000;
  1498. t->wr_access /= 1000;
  1499. t->wr_data_mux_bus /= 1000;
  1500. }
  1501. int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
  1502. struct gpmc_settings *gpmc_s,
  1503. struct gpmc_device_timings *dev_t)
  1504. {
  1505. bool mux = false, sync = false;
  1506. if (gpmc_s) {
  1507. mux = gpmc_s->mux_add_data ? true : false;
  1508. sync = (gpmc_s->sync_read || gpmc_s->sync_write);
  1509. }
  1510. memset(gpmc_t, 0, sizeof(*gpmc_t));
  1511. gpmc_calc_common_timings(gpmc_t, dev_t, sync);
  1512. if (gpmc_s && gpmc_s->sync_read)
  1513. gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
  1514. else
  1515. gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
  1516. if (gpmc_s && gpmc_s->sync_write)
  1517. gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
  1518. else
  1519. gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
  1520. /* TODO: remove, see function definition */
  1521. gpmc_convert_ps_to_ns(gpmc_t);
  1522. return 0;
  1523. }
  1524. /**
  1525. * gpmc_cs_program_settings - programs non-timing related settings
  1526. * @cs: GPMC chip-select to program
  1527. * @p: pointer to GPMC settings structure
  1528. *
  1529. * Programs non-timing related settings for a GPMC chip-select, such as
  1530. * bus-width, burst configuration, etc. Function should be called once
  1531. * for each chip-select that is being used and must be called before
  1532. * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
  1533. * register will be initialised to zero by this function. Returns 0 on
  1534. * success and appropriate negative error code on failure.
  1535. */
  1536. int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
  1537. {
  1538. u32 config1;
  1539. if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
  1540. pr_err("%s: invalid width %d!", __func__, p->device_width);
  1541. return -EINVAL;
  1542. }
  1543. /* Address-data multiplexing not supported for NAND devices */
  1544. if (p->device_nand && p->mux_add_data) {
  1545. pr_err("%s: invalid configuration!\n", __func__);
  1546. return -EINVAL;
  1547. }
  1548. if ((p->mux_add_data > GPMC_MUX_AD) ||
  1549. ((p->mux_add_data == GPMC_MUX_AAD) &&
  1550. !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
  1551. pr_err("%s: invalid multiplex configuration!\n", __func__);
  1552. return -EINVAL;
  1553. }
  1554. /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
  1555. if (p->burst_read || p->burst_write) {
  1556. switch (p->burst_len) {
  1557. case GPMC_BURST_4:
  1558. case GPMC_BURST_8:
  1559. case GPMC_BURST_16:
  1560. break;
  1561. default:
  1562. pr_err("%s: invalid page/burst-length (%d)\n",
  1563. __func__, p->burst_len);
  1564. return -EINVAL;
  1565. }
  1566. }
  1567. if (p->wait_pin > gpmc_nr_waitpins) {
  1568. pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
  1569. return -EINVAL;
  1570. }
  1571. config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
  1572. if (p->sync_read)
  1573. config1 |= GPMC_CONFIG1_READTYPE_SYNC;
  1574. if (p->sync_write)
  1575. config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
  1576. if (p->wait_on_read)
  1577. config1 |= GPMC_CONFIG1_WAIT_READ_MON;
  1578. if (p->wait_on_write)
  1579. config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
  1580. if (p->wait_on_read || p->wait_on_write)
  1581. config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
  1582. if (p->device_nand)
  1583. config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
  1584. if (p->mux_add_data)
  1585. config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
  1586. if (p->burst_read)
  1587. config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
  1588. if (p->burst_write)
  1589. config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
  1590. if (p->burst_read || p->burst_write) {
  1591. config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
  1592. config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
  1593. }
  1594. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
  1595. return 0;
  1596. }
  1597. #ifdef CONFIG_OF
  1598. static const struct of_device_id gpmc_dt_ids[] = {
  1599. { .compatible = "ti,omap2420-gpmc" },
  1600. { .compatible = "ti,omap2430-gpmc" },
  1601. { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
  1602. { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
  1603. { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
  1604. { }
  1605. };
  1606. static void gpmc_cs_set_name(int cs, const char *name)
  1607. {
  1608. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  1609. gpmc->name = name;
  1610. }
  1611. static const char *gpmc_cs_get_name(int cs)
  1612. {
  1613. struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
  1614. return gpmc->name;
  1615. }
  1616. /**
  1617. * gpmc_cs_remap - remaps a chip-select physical base address
  1618. * @cs: chip-select to remap
  1619. * @base: physical base address to re-map chip-select to
  1620. *
  1621. * Re-maps a chip-select to a new physical base address specified by
  1622. * "base". Returns 0 on success and appropriate negative error code
  1623. * on failure.
  1624. */
  1625. static int gpmc_cs_remap(int cs, u32 base)
  1626. {
  1627. int ret;
  1628. u32 old_base, size;
  1629. if (cs >= gpmc_cs_num) {
  1630. pr_err("%s: requested chip-select is disabled\n", __func__);
  1631. return -ENODEV;
  1632. }
  1633. /*
  1634. * Make sure we ignore any device offsets from the GPMC partition
  1635. * allocated for the chip select and that the new base confirms
  1636. * to the GPMC 16MB minimum granularity.
  1637. */
  1638. base &= ~(SZ_16M - 1);
  1639. gpmc_cs_get_memconf(cs, &old_base, &size);
  1640. if (base == old_base)
  1641. return 0;
  1642. ret = gpmc_cs_delete_mem(cs);
  1643. if (ret < 0)
  1644. return ret;
  1645. ret = gpmc_cs_insert_mem(cs, base, size);
  1646. if (ret < 0)
  1647. return ret;
  1648. ret = gpmc_cs_set_memconf(cs, base, size);
  1649. return ret;
  1650. }
  1651. /**
  1652. * gpmc_read_settings_dt - read gpmc settings from device-tree
  1653. * @np: pointer to device-tree node for a gpmc child device
  1654. * @p: pointer to gpmc settings structure
  1655. *
  1656. * Reads the GPMC settings for a GPMC child device from device-tree and
  1657. * stores them in the GPMC settings structure passed. The GPMC settings
  1658. * structure is initialised to zero by this function and so any
  1659. * previously stored settings will be cleared.
  1660. */
  1661. void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
  1662. {
  1663. memset(p, 0, sizeof(struct gpmc_settings));
  1664. p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
  1665. p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
  1666. of_property_read_u32(np, "gpmc,device-width", &p->device_width);
  1667. of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
  1668. if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
  1669. p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
  1670. p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
  1671. p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
  1672. if (!p->burst_read && !p->burst_write)
  1673. pr_warn("%s: page/burst-length set but not used!\n",
  1674. __func__);
  1675. }
  1676. if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
  1677. p->wait_on_read = of_property_read_bool(np,
  1678. "gpmc,wait-on-read");
  1679. p->wait_on_write = of_property_read_bool(np,
  1680. "gpmc,wait-on-write");
  1681. if (!p->wait_on_read && !p->wait_on_write)
  1682. pr_debug("%s: rd/wr wait monitoring not enabled!\n",
  1683. __func__);
  1684. }
  1685. }
  1686. static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
  1687. struct gpmc_timings *gpmc_t)
  1688. {
  1689. struct gpmc_bool_timings *p;
  1690. if (!np || !gpmc_t)
  1691. return;
  1692. memset(gpmc_t, 0, sizeof(*gpmc_t));
  1693. /* minimum clock period for syncronous mode */
  1694. of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
  1695. /* chip select timtings */
  1696. of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
  1697. of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
  1698. of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
  1699. /* ADV signal timings */
  1700. of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
  1701. of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
  1702. of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
  1703. of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
  1704. &gpmc_t->adv_aad_mux_on);
  1705. of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
  1706. &gpmc_t->adv_aad_mux_rd_off);
  1707. of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
  1708. &gpmc_t->adv_aad_mux_wr_off);
  1709. /* WE signal timings */
  1710. of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
  1711. of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
  1712. /* OE signal timings */
  1713. of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
  1714. of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
  1715. of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
  1716. &gpmc_t->oe_aad_mux_on);
  1717. of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
  1718. &gpmc_t->oe_aad_mux_off);
  1719. /* access and cycle timings */
  1720. of_property_read_u32(np, "gpmc,page-burst-access-ns",
  1721. &gpmc_t->page_burst_access);
  1722. of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
  1723. of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
  1724. of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
  1725. of_property_read_u32(np, "gpmc,bus-turnaround-ns",
  1726. &gpmc_t->bus_turnaround);
  1727. of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
  1728. &gpmc_t->cycle2cycle_delay);
  1729. of_property_read_u32(np, "gpmc,wait-monitoring-ns",
  1730. &gpmc_t->wait_monitoring);
  1731. of_property_read_u32(np, "gpmc,clk-activation-ns",
  1732. &gpmc_t->clk_activation);
  1733. /* only applicable to OMAP3+ */
  1734. of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
  1735. of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
  1736. &gpmc_t->wr_data_mux_bus);
  1737. /* bool timing parameters */
  1738. p = &gpmc_t->bool_timings;
  1739. p->cycle2cyclediffcsen =
  1740. of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
  1741. p->cycle2cyclesamecsen =
  1742. of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
  1743. p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
  1744. p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
  1745. p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
  1746. p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
  1747. p->time_para_granularity =
  1748. of_property_read_bool(np, "gpmc,time-para-granularity");
  1749. }
  1750. /**
  1751. * gpmc_probe_generic_child - configures the gpmc for a child device
  1752. * @pdev: pointer to gpmc platform device
  1753. * @child: pointer to device-tree node for child device
  1754. *
  1755. * Allocates and configures a GPMC chip-select for a child device.
  1756. * Returns 0 on success and appropriate negative error code on failure.
  1757. */
  1758. static int gpmc_probe_generic_child(struct platform_device *pdev,
  1759. struct device_node *child)
  1760. {
  1761. struct gpmc_settings gpmc_s;
  1762. struct gpmc_timings gpmc_t;
  1763. struct resource res;
  1764. unsigned long base;
  1765. const char *name;
  1766. int ret, cs;
  1767. u32 val;
  1768. struct gpio_desc *waitpin_desc = NULL;
  1769. struct gpmc_device *gpmc = platform_get_drvdata(pdev);
  1770. if (of_property_read_u32(child, "reg", &cs) < 0) {
  1771. dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
  1772. child);
  1773. return -ENODEV;
  1774. }
  1775. if (of_address_to_resource(child, 0, &res) < 0) {
  1776. dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
  1777. child);
  1778. return -ENODEV;
  1779. }
  1780. /*
  1781. * Check if we have multiple instances of the same device
  1782. * on a single chip select. If so, use the already initialized
  1783. * timings.
  1784. */
  1785. name = gpmc_cs_get_name(cs);
  1786. if (name && of_node_name_eq(child, name))
  1787. goto no_timings;
  1788. ret = gpmc_cs_request(cs, resource_size(&res), &base);
  1789. if (ret < 0) {
  1790. dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
  1791. return ret;
  1792. }
  1793. gpmc_cs_set_name(cs, child->full_name);
  1794. gpmc_read_settings_dt(child, &gpmc_s);
  1795. gpmc_read_timings_dt(child, &gpmc_t);
  1796. /*
  1797. * For some GPMC devices we still need to rely on the bootloader
  1798. * timings because the devices can be connected via FPGA.
  1799. * REVISIT: Add timing support from slls644g.pdf.
  1800. */
  1801. if (!gpmc_t.cs_rd_off) {
  1802. WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
  1803. cs);
  1804. gpmc_cs_show_timings(cs,
  1805. "please add GPMC bootloader timings to .dts");
  1806. goto no_timings;
  1807. }
  1808. /* CS must be disabled while making changes to gpmc configuration */
  1809. gpmc_cs_disable_mem(cs);
  1810. /*
  1811. * FIXME: gpmc_cs_request() will map the CS to an arbitrary
  1812. * location in the gpmc address space. When booting with
  1813. * device-tree we want the NOR flash to be mapped to the
  1814. * location specified in the device-tree blob. So remap the
  1815. * CS to this location. Once DT migration is complete should
  1816. * just make gpmc_cs_request() map a specific address.
  1817. */
  1818. ret = gpmc_cs_remap(cs, res.start);
  1819. if (ret < 0) {
  1820. dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
  1821. cs, &res.start);
  1822. if (res.start < GPMC_MEM_START) {
  1823. dev_info(&pdev->dev,
  1824. "GPMC CS %d start cannot be lesser than 0x%x\n",
  1825. cs, GPMC_MEM_START);
  1826. } else if (res.end > GPMC_MEM_END) {
  1827. dev_info(&pdev->dev,
  1828. "GPMC CS %d end cannot be greater than 0x%x\n",
  1829. cs, GPMC_MEM_END);
  1830. }
  1831. goto err;
  1832. }
  1833. if (of_node_name_eq(child, "nand")) {
  1834. /* Warn about older DT blobs with no compatible property */
  1835. if (!of_property_read_bool(child, "compatible")) {
  1836. dev_warn(&pdev->dev,
  1837. "Incompatible NAND node: missing compatible");
  1838. ret = -EINVAL;
  1839. goto err;
  1840. }
  1841. }
  1842. if (of_node_name_eq(child, "onenand")) {
  1843. /* Warn about older DT blobs with no compatible property */
  1844. if (!of_property_read_bool(child, "compatible")) {
  1845. dev_warn(&pdev->dev,
  1846. "Incompatible OneNAND node: missing compatible");
  1847. ret = -EINVAL;
  1848. goto err;
  1849. }
  1850. }
  1851. if (of_device_is_compatible(child, "ti,omap2-nand")) {
  1852. /* NAND specific setup */
  1853. val = 8;
  1854. of_property_read_u32(child, "nand-bus-width", &val);
  1855. switch (val) {
  1856. case 8:
  1857. gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
  1858. break;
  1859. case 16:
  1860. gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
  1861. break;
  1862. default:
  1863. dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
  1864. child);
  1865. ret = -EINVAL;
  1866. goto err;
  1867. }
  1868. /* disable write protect */
  1869. gpmc_configure(GPMC_CONFIG_WP, 0);
  1870. gpmc_s.device_nand = true;
  1871. } else {
  1872. ret = of_property_read_u32(child, "bank-width",
  1873. &gpmc_s.device_width);
  1874. if (ret < 0 && !gpmc_s.device_width) {
  1875. dev_err(&pdev->dev,
  1876. "%pOF has no 'gpmc,device-width' property\n",
  1877. child);
  1878. goto err;
  1879. }
  1880. }
  1881. /* Reserve wait pin if it is required and valid */
  1882. if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
  1883. unsigned int wait_pin = gpmc_s.wait_pin;
  1884. waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
  1885. wait_pin, "WAITPIN",
  1886. GPIO_ACTIVE_HIGH,
  1887. GPIOD_IN);
  1888. if (IS_ERR(waitpin_desc)) {
  1889. dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
  1890. ret = PTR_ERR(waitpin_desc);
  1891. goto err;
  1892. }
  1893. }
  1894. gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
  1895. ret = gpmc_cs_program_settings(cs, &gpmc_s);
  1896. if (ret < 0)
  1897. goto err_cs;
  1898. ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
  1899. if (ret) {
  1900. dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
  1901. child);
  1902. goto err_cs;
  1903. }
  1904. /* Clear limited address i.e. enable A26-A11 */
  1905. val = gpmc_read_reg(GPMC_CONFIG);
  1906. val &= ~GPMC_CONFIG_LIMITEDADDRESS;
  1907. gpmc_write_reg(GPMC_CONFIG, val);
  1908. /* Enable CS region */
  1909. gpmc_cs_enable_mem(cs);
  1910. no_timings:
  1911. /* create platform device, NULL on error or when disabled */
  1912. if (!of_platform_device_create(child, NULL, &pdev->dev))
  1913. goto err_child_fail;
  1914. /* is child a common bus? */
  1915. if (of_match_node(of_default_bus_match_table, child))
  1916. /* create children and other common bus children */
  1917. if (of_platform_default_populate(child, NULL, &pdev->dev))
  1918. goto err_child_fail;
  1919. return 0;
  1920. err_child_fail:
  1921. dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
  1922. ret = -ENODEV;
  1923. err_cs:
  1924. gpiochip_free_own_desc(waitpin_desc);
  1925. err:
  1926. gpmc_cs_free(cs);
  1927. return ret;
  1928. }
  1929. static int gpmc_probe_dt(struct platform_device *pdev)
  1930. {
  1931. int ret;
  1932. const struct of_device_id *of_id =
  1933. of_match_device(gpmc_dt_ids, &pdev->dev);
  1934. if (!of_id)
  1935. return 0;
  1936. ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
  1937. &gpmc_cs_num);
  1938. if (ret < 0) {
  1939. pr_err("%s: number of chip-selects not defined\n", __func__);
  1940. return ret;
  1941. } else if (gpmc_cs_num < 1) {
  1942. pr_err("%s: all chip-selects are disabled\n", __func__);
  1943. return -EINVAL;
  1944. } else if (gpmc_cs_num > GPMC_CS_NUM) {
  1945. pr_err("%s: number of supported chip-selects cannot be > %d\n",
  1946. __func__, GPMC_CS_NUM);
  1947. return -EINVAL;
  1948. }
  1949. ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
  1950. &gpmc_nr_waitpins);
  1951. if (ret < 0) {
  1952. pr_err("%s: number of wait pins not found!\n", __func__);
  1953. return ret;
  1954. }
  1955. return 0;
  1956. }
  1957. static void gpmc_probe_dt_children(struct platform_device *pdev)
  1958. {
  1959. int ret;
  1960. struct device_node *child;
  1961. for_each_available_child_of_node(pdev->dev.of_node, child) {
  1962. ret = gpmc_probe_generic_child(pdev, child);
  1963. if (ret) {
  1964. dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
  1965. child, ret);
  1966. }
  1967. }
  1968. }
  1969. #else
  1970. void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
  1971. {
  1972. memset(p, 0, sizeof(*p));
  1973. }
  1974. static int gpmc_probe_dt(struct platform_device *pdev)
  1975. {
  1976. return 0;
  1977. }
  1978. static void gpmc_probe_dt_children(struct platform_device *pdev)
  1979. {
  1980. }
  1981. #endif /* CONFIG_OF */
  1982. static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
  1983. {
  1984. return 1; /* we're input only */
  1985. }
  1986. static int gpmc_gpio_direction_input(struct gpio_chip *chip,
  1987. unsigned int offset)
  1988. {
  1989. return 0; /* we're input only */
  1990. }
  1991. static int gpmc_gpio_direction_output(struct gpio_chip *chip,
  1992. unsigned int offset, int value)
  1993. {
  1994. return -EINVAL; /* we're input only */
  1995. }
  1996. static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
  1997. int value)
  1998. {
  1999. }
  2000. static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
  2001. {
  2002. u32 reg;
  2003. offset += 8;
  2004. reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
  2005. return !!reg;
  2006. }
  2007. static int gpmc_gpio_init(struct gpmc_device *gpmc)
  2008. {
  2009. int ret;
  2010. gpmc->gpio_chip.parent = gpmc->dev;
  2011. gpmc->gpio_chip.owner = THIS_MODULE;
  2012. gpmc->gpio_chip.label = DEVICE_NAME;
  2013. gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
  2014. gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
  2015. gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
  2016. gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
  2017. gpmc->gpio_chip.set = gpmc_gpio_set;
  2018. gpmc->gpio_chip.get = gpmc_gpio_get;
  2019. gpmc->gpio_chip.base = -1;
  2020. ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
  2021. if (ret < 0) {
  2022. dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
  2023. return ret;
  2024. }
  2025. return 0;
  2026. }
  2027. static int gpmc_probe(struct platform_device *pdev)
  2028. {
  2029. int rc;
  2030. u32 l;
  2031. struct resource *res;
  2032. struct gpmc_device *gpmc;
  2033. gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
  2034. if (!gpmc)
  2035. return -ENOMEM;
  2036. gpmc->dev = &pdev->dev;
  2037. platform_set_drvdata(pdev, gpmc);
  2038. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2039. if (!res)
  2040. return -ENOENT;
  2041. gpmc_base = devm_ioremap_resource(&pdev->dev, res);
  2042. if (IS_ERR(gpmc_base))
  2043. return PTR_ERR(gpmc_base);
  2044. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  2045. if (!res) {
  2046. dev_err(&pdev->dev, "Failed to get resource: irq\n");
  2047. return -ENOENT;
  2048. }
  2049. gpmc->irq = res->start;
  2050. gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
  2051. if (IS_ERR(gpmc_l3_clk)) {
  2052. dev_err(&pdev->dev, "Failed to get GPMC fck\n");
  2053. return PTR_ERR(gpmc_l3_clk);
  2054. }
  2055. if (!clk_get_rate(gpmc_l3_clk)) {
  2056. dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
  2057. return -EINVAL;
  2058. }
  2059. if (pdev->dev.of_node) {
  2060. rc = gpmc_probe_dt(pdev);
  2061. if (rc)
  2062. return rc;
  2063. } else {
  2064. gpmc_cs_num = GPMC_CS_NUM;
  2065. gpmc_nr_waitpins = GPMC_NR_WAITPINS;
  2066. }
  2067. pm_runtime_enable(&pdev->dev);
  2068. pm_runtime_get_sync(&pdev->dev);
  2069. l = gpmc_read_reg(GPMC_REVISION);
  2070. /*
  2071. * FIXME: Once device-tree migration is complete the below flags
  2072. * should be populated based upon the device-tree compatible
  2073. * string. For now just use the IP revision. OMAP3+ devices have
  2074. * the wr_access and wr_data_mux_bus register fields. OMAP4+
  2075. * devices support the addr-addr-data multiplex protocol.
  2076. *
  2077. * GPMC IP revisions:
  2078. * - OMAP24xx = 2.0
  2079. * - OMAP3xxx = 5.0
  2080. * - OMAP44xx/54xx/AM335x = 6.0
  2081. */
  2082. if (GPMC_REVISION_MAJOR(l) > 0x4)
  2083. gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
  2084. if (GPMC_REVISION_MAJOR(l) > 0x5)
  2085. gpmc_capability |= GPMC_HAS_MUX_AAD;
  2086. dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
  2087. GPMC_REVISION_MINOR(l));
  2088. gpmc_mem_init();
  2089. rc = gpmc_gpio_init(gpmc);
  2090. if (rc)
  2091. goto gpio_init_failed;
  2092. gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
  2093. rc = gpmc_setup_irq(gpmc);
  2094. if (rc) {
  2095. dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
  2096. goto gpio_init_failed;
  2097. }
  2098. gpmc_probe_dt_children(pdev);
  2099. return 0;
  2100. gpio_init_failed:
  2101. gpmc_mem_exit();
  2102. pm_runtime_put_sync(&pdev->dev);
  2103. pm_runtime_disable(&pdev->dev);
  2104. return rc;
  2105. }
  2106. static int gpmc_remove(struct platform_device *pdev)
  2107. {
  2108. struct gpmc_device *gpmc = platform_get_drvdata(pdev);
  2109. gpmc_free_irq(gpmc);
  2110. gpmc_mem_exit();
  2111. pm_runtime_put_sync(&pdev->dev);
  2112. pm_runtime_disable(&pdev->dev);
  2113. return 0;
  2114. }
  2115. #ifdef CONFIG_PM_SLEEP
  2116. static int gpmc_suspend(struct device *dev)
  2117. {
  2118. omap3_gpmc_save_context();
  2119. pm_runtime_put_sync(dev);
  2120. return 0;
  2121. }
  2122. static int gpmc_resume(struct device *dev)
  2123. {
  2124. pm_runtime_get_sync(dev);
  2125. omap3_gpmc_restore_context();
  2126. return 0;
  2127. }
  2128. #endif
  2129. static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
  2130. static struct platform_driver gpmc_driver = {
  2131. .probe = gpmc_probe,
  2132. .remove = gpmc_remove,
  2133. .driver = {
  2134. .name = DEVICE_NAME,
  2135. .of_match_table = of_match_ptr(gpmc_dt_ids),
  2136. .pm = &gpmc_pm_ops,
  2137. },
  2138. };
  2139. static __init int gpmc_init(void)
  2140. {
  2141. return platform_driver_register(&gpmc_driver);
  2142. }
  2143. postcore_initcall(gpmc_init);
  2144. static struct omap3_gpmc_regs gpmc_context;
  2145. void omap3_gpmc_save_context(void)
  2146. {
  2147. int i;
  2148. if (!gpmc_base)
  2149. return;
  2150. gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
  2151. gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
  2152. gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
  2153. gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
  2154. gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
  2155. gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
  2156. gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
  2157. for (i = 0; i < gpmc_cs_num; i++) {
  2158. gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
  2159. if (gpmc_context.cs_context[i].is_valid) {
  2160. gpmc_context.cs_context[i].config1 =
  2161. gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
  2162. gpmc_context.cs_context[i].config2 =
  2163. gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
  2164. gpmc_context.cs_context[i].config3 =
  2165. gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
  2166. gpmc_context.cs_context[i].config4 =
  2167. gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
  2168. gpmc_context.cs_context[i].config5 =
  2169. gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
  2170. gpmc_context.cs_context[i].config6 =
  2171. gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
  2172. gpmc_context.cs_context[i].config7 =
  2173. gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
  2174. }
  2175. }
  2176. }
  2177. void omap3_gpmc_restore_context(void)
  2178. {
  2179. int i;
  2180. if (!gpmc_base)
  2181. return;
  2182. gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
  2183. gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
  2184. gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
  2185. gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
  2186. gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
  2187. gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
  2188. gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
  2189. for (i = 0; i < gpmc_cs_num; i++) {
  2190. if (gpmc_context.cs_context[i].is_valid) {
  2191. gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
  2192. gpmc_context.cs_context[i].config1);
  2193. gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
  2194. gpmc_context.cs_context[i].config2);
  2195. gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
  2196. gpmc_context.cs_context[i].config3);
  2197. gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
  2198. gpmc_context.cs_context[i].config4);
  2199. gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
  2200. gpmc_context.cs_context[i].config5);
  2201. gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
  2202. gpmc_context.cs_context[i].config6);
  2203. gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
  2204. gpmc_context.cs_context[i].config7);
  2205. }
  2206. }
  2207. }