mvebu-devbus.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Marvell EBU SoC Device Bus Controller
  4. * (memory controller for NOR/NAND/SRAM/FPGA devices)
  5. *
  6. * Copyright (C) 2013-2014 Marvell
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/slab.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/clk.h>
  14. #include <linux/mbus.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/of_address.h>
  17. #include <linux/platform_device.h>
  18. /* Register definitions */
  19. #define ARMADA_DEV_WIDTH_SHIFT 30
  20. #define ARMADA_BADR_SKEW_SHIFT 28
  21. #define ARMADA_RD_HOLD_SHIFT 23
  22. #define ARMADA_ACC_NEXT_SHIFT 17
  23. #define ARMADA_RD_SETUP_SHIFT 12
  24. #define ARMADA_ACC_FIRST_SHIFT 6
  25. #define ARMADA_SYNC_ENABLE_SHIFT 24
  26. #define ARMADA_WR_HIGH_SHIFT 16
  27. #define ARMADA_WR_LOW_SHIFT 8
  28. #define ARMADA_READ_PARAM_OFFSET 0x0
  29. #define ARMADA_WRITE_PARAM_OFFSET 0x4
  30. #define ORION_RESERVED (0x2 << 30)
  31. #define ORION_BADR_SKEW_SHIFT 28
  32. #define ORION_WR_HIGH_EXT_BIT BIT(27)
  33. #define ORION_WR_HIGH_EXT_MASK 0x8
  34. #define ORION_WR_LOW_EXT_BIT BIT(26)
  35. #define ORION_WR_LOW_EXT_MASK 0x8
  36. #define ORION_ALE_WR_EXT_BIT BIT(25)
  37. #define ORION_ALE_WR_EXT_MASK 0x8
  38. #define ORION_ACC_NEXT_EXT_BIT BIT(24)
  39. #define ORION_ACC_NEXT_EXT_MASK 0x10
  40. #define ORION_ACC_FIRST_EXT_BIT BIT(23)
  41. #define ORION_ACC_FIRST_EXT_MASK 0x10
  42. #define ORION_TURN_OFF_EXT_BIT BIT(22)
  43. #define ORION_TURN_OFF_EXT_MASK 0x8
  44. #define ORION_DEV_WIDTH_SHIFT 20
  45. #define ORION_WR_HIGH_SHIFT 17
  46. #define ORION_WR_HIGH_MASK 0x7
  47. #define ORION_WR_LOW_SHIFT 14
  48. #define ORION_WR_LOW_MASK 0x7
  49. #define ORION_ALE_WR_SHIFT 11
  50. #define ORION_ALE_WR_MASK 0x7
  51. #define ORION_ACC_NEXT_SHIFT 7
  52. #define ORION_ACC_NEXT_MASK 0xF
  53. #define ORION_ACC_FIRST_SHIFT 3
  54. #define ORION_ACC_FIRST_MASK 0xF
  55. #define ORION_TURN_OFF_SHIFT 0
  56. #define ORION_TURN_OFF_MASK 0x7
  57. struct devbus_read_params {
  58. u32 bus_width;
  59. u32 badr_skew;
  60. u32 turn_off;
  61. u32 acc_first;
  62. u32 acc_next;
  63. u32 rd_setup;
  64. u32 rd_hold;
  65. };
  66. struct devbus_write_params {
  67. u32 sync_enable;
  68. u32 wr_high;
  69. u32 wr_low;
  70. u32 ale_wr;
  71. };
  72. struct devbus {
  73. struct device *dev;
  74. void __iomem *base;
  75. unsigned long tick_ps;
  76. };
  77. static int get_timing_param_ps(struct devbus *devbus,
  78. struct device_node *node,
  79. const char *name,
  80. u32 *ticks)
  81. {
  82. u32 time_ps;
  83. int err;
  84. err = of_property_read_u32(node, name, &time_ps);
  85. if (err < 0) {
  86. dev_err(devbus->dev, "%pOF has no '%s' property\n",
  87. node, name);
  88. return err;
  89. }
  90. *ticks = (time_ps + devbus->tick_ps - 1) / devbus->tick_ps;
  91. dev_dbg(devbus->dev, "%s: %u ps -> 0x%x\n",
  92. name, time_ps, *ticks);
  93. return 0;
  94. }
  95. static int devbus_get_timing_params(struct devbus *devbus,
  96. struct device_node *node,
  97. struct devbus_read_params *r,
  98. struct devbus_write_params *w)
  99. {
  100. int err;
  101. err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width);
  102. if (err < 0) {
  103. dev_err(devbus->dev,
  104. "%pOF has no 'devbus,bus-width' property\n",
  105. node);
  106. return err;
  107. }
  108. /*
  109. * The bus width is encoded into the register as 0 for 8 bits,
  110. * and 1 for 16 bits, so we do the necessary conversion here.
  111. */
  112. if (r->bus_width == 8) {
  113. r->bus_width = 0;
  114. } else if (r->bus_width == 16) {
  115. r->bus_width = 1;
  116. } else {
  117. dev_err(devbus->dev, "invalid bus width %d\n", r->bus_width);
  118. return -EINVAL;
  119. }
  120. err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
  121. &r->badr_skew);
  122. if (err < 0)
  123. return err;
  124. err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
  125. &r->turn_off);
  126. if (err < 0)
  127. return err;
  128. err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
  129. &r->acc_first);
  130. if (err < 0)
  131. return err;
  132. err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
  133. &r->acc_next);
  134. if (err < 0)
  135. return err;
  136. if (of_device_is_compatible(devbus->dev->of_node, "marvell,mvebu-devbus")) {
  137. err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
  138. &r->rd_setup);
  139. if (err < 0)
  140. return err;
  141. err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
  142. &r->rd_hold);
  143. if (err < 0)
  144. return err;
  145. err = of_property_read_u32(node, "devbus,sync-enable",
  146. &w->sync_enable);
  147. if (err < 0) {
  148. dev_err(devbus->dev,
  149. "%pOF has no 'devbus,sync-enable' property\n",
  150. node);
  151. return err;
  152. }
  153. }
  154. err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
  155. &w->ale_wr);
  156. if (err < 0)
  157. return err;
  158. err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
  159. &w->wr_low);
  160. if (err < 0)
  161. return err;
  162. err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
  163. &w->wr_high);
  164. if (err < 0)
  165. return err;
  166. return 0;
  167. }
  168. static void devbus_orion_set_timing_params(struct devbus *devbus,
  169. struct device_node *node,
  170. struct devbus_read_params *r,
  171. struct devbus_write_params *w)
  172. {
  173. u32 value;
  174. /*
  175. * The hardware designers found it would be a good idea to
  176. * split most of the values in the register into two fields:
  177. * one containing all the low-order bits, and another one
  178. * containing just the high-order bit. For all of those
  179. * fields, we have to split the value into these two parts.
  180. */
  181. value = (r->turn_off & ORION_TURN_OFF_MASK) << ORION_TURN_OFF_SHIFT |
  182. (r->acc_first & ORION_ACC_FIRST_MASK) << ORION_ACC_FIRST_SHIFT |
  183. (r->acc_next & ORION_ACC_NEXT_MASK) << ORION_ACC_NEXT_SHIFT |
  184. (w->ale_wr & ORION_ALE_WR_MASK) << ORION_ALE_WR_SHIFT |
  185. (w->wr_low & ORION_WR_LOW_MASK) << ORION_WR_LOW_SHIFT |
  186. (w->wr_high & ORION_WR_HIGH_MASK) << ORION_WR_HIGH_SHIFT |
  187. r->bus_width << ORION_DEV_WIDTH_SHIFT |
  188. ((r->turn_off & ORION_TURN_OFF_EXT_MASK) ? ORION_TURN_OFF_EXT_BIT : 0) |
  189. ((r->acc_first & ORION_ACC_FIRST_EXT_MASK) ? ORION_ACC_FIRST_EXT_BIT : 0) |
  190. ((r->acc_next & ORION_ACC_NEXT_EXT_MASK) ? ORION_ACC_NEXT_EXT_BIT : 0) |
  191. ((w->ale_wr & ORION_ALE_WR_EXT_MASK) ? ORION_ALE_WR_EXT_BIT : 0) |
  192. ((w->wr_low & ORION_WR_LOW_EXT_MASK) ? ORION_WR_LOW_EXT_BIT : 0) |
  193. ((w->wr_high & ORION_WR_HIGH_EXT_MASK) ? ORION_WR_HIGH_EXT_BIT : 0) |
  194. (r->badr_skew << ORION_BADR_SKEW_SHIFT) |
  195. ORION_RESERVED;
  196. writel(value, devbus->base);
  197. }
  198. static void devbus_armada_set_timing_params(struct devbus *devbus,
  199. struct device_node *node,
  200. struct devbus_read_params *r,
  201. struct devbus_write_params *w)
  202. {
  203. u32 value;
  204. /* Set read timings */
  205. value = r->bus_width << ARMADA_DEV_WIDTH_SHIFT |
  206. r->badr_skew << ARMADA_BADR_SKEW_SHIFT |
  207. r->rd_hold << ARMADA_RD_HOLD_SHIFT |
  208. r->acc_next << ARMADA_ACC_NEXT_SHIFT |
  209. r->rd_setup << ARMADA_RD_SETUP_SHIFT |
  210. r->acc_first << ARMADA_ACC_FIRST_SHIFT |
  211. r->turn_off;
  212. dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
  213. devbus->base + ARMADA_READ_PARAM_OFFSET,
  214. value);
  215. writel(value, devbus->base + ARMADA_READ_PARAM_OFFSET);
  216. /* Set write timings */
  217. value = w->sync_enable << ARMADA_SYNC_ENABLE_SHIFT |
  218. w->wr_low << ARMADA_WR_LOW_SHIFT |
  219. w->wr_high << ARMADA_WR_HIGH_SHIFT |
  220. w->ale_wr;
  221. dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
  222. devbus->base + ARMADA_WRITE_PARAM_OFFSET,
  223. value);
  224. writel(value, devbus->base + ARMADA_WRITE_PARAM_OFFSET);
  225. }
  226. static int mvebu_devbus_probe(struct platform_device *pdev)
  227. {
  228. struct device *dev = &pdev->dev;
  229. struct device_node *node = pdev->dev.of_node;
  230. struct devbus_read_params r;
  231. struct devbus_write_params w;
  232. struct devbus *devbus;
  233. struct clk *clk;
  234. unsigned long rate;
  235. int err;
  236. devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
  237. if (!devbus)
  238. return -ENOMEM;
  239. devbus->dev = dev;
  240. devbus->base = devm_platform_ioremap_resource(pdev, 0);
  241. if (IS_ERR(devbus->base))
  242. return PTR_ERR(devbus->base);
  243. clk = devm_clk_get(&pdev->dev, NULL);
  244. if (IS_ERR(clk))
  245. return PTR_ERR(clk);
  246. clk_prepare_enable(clk);
  247. /*
  248. * Obtain clock period in picoseconds,
  249. * we need this in order to convert timing
  250. * parameters from cycles to picoseconds.
  251. */
  252. rate = clk_get_rate(clk) / 1000;
  253. devbus->tick_ps = 1000000000 / rate;
  254. dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
  255. devbus->tick_ps);
  256. if (!of_property_read_bool(node, "devbus,keep-config")) {
  257. /* Read the Device Tree node */
  258. err = devbus_get_timing_params(devbus, node, &r, &w);
  259. if (err < 0)
  260. return err;
  261. /* Set the new timing parameters */
  262. if (of_device_is_compatible(node, "marvell,orion-devbus"))
  263. devbus_orion_set_timing_params(devbus, node, &r, &w);
  264. else
  265. devbus_armada_set_timing_params(devbus, node, &r, &w);
  266. }
  267. /*
  268. * We need to create a child device explicitly from here to
  269. * guarantee that the child will be probed after the timing
  270. * parameters for the bus are written.
  271. */
  272. err = of_platform_populate(node, NULL, NULL, dev);
  273. if (err < 0)
  274. return err;
  275. return 0;
  276. }
  277. static const struct of_device_id mvebu_devbus_of_match[] = {
  278. { .compatible = "marvell,mvebu-devbus" },
  279. { .compatible = "marvell,orion-devbus" },
  280. {},
  281. };
  282. MODULE_DEVICE_TABLE(of, mvebu_devbus_of_match);
  283. static struct platform_driver mvebu_devbus_driver = {
  284. .probe = mvebu_devbus_probe,
  285. .driver = {
  286. .name = "mvebu-devbus",
  287. .of_match_table = mvebu_devbus_of_match,
  288. },
  289. };
  290. static int __init mvebu_devbus_init(void)
  291. {
  292. return platform_driver_register(&mvebu_devbus_driver);
  293. }
  294. module_init(mvebu_devbus_init);
  295. MODULE_LICENSE("GPL v2");
  296. MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
  297. MODULE_DESCRIPTION("Marvell EBU SoC Device Bus controller");