mtk-smi.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2016 MediaTek Inc.
  4. * Author: Yong Wu <yong.wu@mediatek.com>
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/component.h>
  8. #include <linux/device.h>
  9. #include <linux/err.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <soc/mediatek/smi.h>
  17. #include <dt-bindings/memory/mt2701-larb-port.h>
  18. #include <dt-bindings/memory/mtk-memory-port.h>
  19. /* mt8173 */
  20. #define SMI_LARB_MMU_EN 0xf00
  21. /* mt8167 */
  22. #define MT8167_SMI_LARB_MMU_EN 0xfc0
  23. /* mt2701 */
  24. #define REG_SMI_SECUR_CON_BASE 0x5c0
  25. /* every register control 8 port, register offset 0x4 */
  26. #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
  27. #define REG_SMI_SECUR_CON_ADDR(id) \
  28. (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
  29. /*
  30. * every port have 4 bit to control, bit[port + 3] control virtual or physical,
  31. * bit[port + 2 : port + 1] control the domain, bit[port] control the security
  32. * or non-security.
  33. */
  34. #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
  35. #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
  36. /* mt2701 domain should be set to 3 */
  37. #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
  38. /* mt2712 */
  39. #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
  40. #define F_MMU_EN BIT(0)
  41. #define BANK_SEL(id) ({ \
  42. u32 _id = (id) & 0x3; \
  43. (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
  44. })
  45. /* SMI COMMON */
  46. #define SMI_BUS_SEL 0x220
  47. #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
  48. /* All are MMU0 defaultly. Only specialize mmu1 here. */
  49. #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
  50. enum mtk_smi_gen {
  51. MTK_SMI_GEN1,
  52. MTK_SMI_GEN2
  53. };
  54. struct mtk_smi_common_plat {
  55. enum mtk_smi_gen gen;
  56. bool has_gals;
  57. u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
  58. };
  59. struct mtk_smi_larb_gen {
  60. int port_in_larb[MTK_LARB_NR_MAX + 1];
  61. void (*config_port)(struct device *dev);
  62. unsigned int larb_direct_to_common_mask;
  63. bool has_gals;
  64. };
  65. struct mtk_smi {
  66. struct device *dev;
  67. struct clk *clk_apb, *clk_smi;
  68. struct clk *clk_gals0, *clk_gals1;
  69. struct clk *clk_async; /*only needed by mt2701*/
  70. union {
  71. void __iomem *smi_ao_base; /* only for gen1 */
  72. void __iomem *base; /* only for gen2 */
  73. };
  74. const struct mtk_smi_common_plat *plat;
  75. };
  76. struct mtk_smi_larb { /* larb: local arbiter */
  77. struct mtk_smi smi;
  78. void __iomem *base;
  79. struct device *smi_common_dev;
  80. const struct mtk_smi_larb_gen *larb_gen;
  81. int larbid;
  82. u32 *mmu;
  83. unsigned char *bank;
  84. };
  85. static int mtk_smi_clk_enable(const struct mtk_smi *smi)
  86. {
  87. int ret;
  88. ret = clk_prepare_enable(smi->clk_apb);
  89. if (ret)
  90. return ret;
  91. ret = clk_prepare_enable(smi->clk_smi);
  92. if (ret)
  93. goto err_disable_apb;
  94. ret = clk_prepare_enable(smi->clk_gals0);
  95. if (ret)
  96. goto err_disable_smi;
  97. ret = clk_prepare_enable(smi->clk_gals1);
  98. if (ret)
  99. goto err_disable_gals0;
  100. return 0;
  101. err_disable_gals0:
  102. clk_disable_unprepare(smi->clk_gals0);
  103. err_disable_smi:
  104. clk_disable_unprepare(smi->clk_smi);
  105. err_disable_apb:
  106. clk_disable_unprepare(smi->clk_apb);
  107. return ret;
  108. }
  109. static void mtk_smi_clk_disable(const struct mtk_smi *smi)
  110. {
  111. clk_disable_unprepare(smi->clk_gals1);
  112. clk_disable_unprepare(smi->clk_gals0);
  113. clk_disable_unprepare(smi->clk_smi);
  114. clk_disable_unprepare(smi->clk_apb);
  115. }
  116. int mtk_smi_larb_get(struct device *larbdev)
  117. {
  118. int ret = pm_runtime_resume_and_get(larbdev);
  119. return (ret < 0) ? ret : 0;
  120. }
  121. EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
  122. void mtk_smi_larb_put(struct device *larbdev)
  123. {
  124. pm_runtime_put_sync(larbdev);
  125. }
  126. EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
  127. static int
  128. mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
  129. {
  130. struct mtk_smi_larb *larb = dev_get_drvdata(dev);
  131. struct mtk_smi_larb_iommu *larb_mmu = data;
  132. unsigned int i;
  133. for (i = 0; i < MTK_LARB_NR_MAX; i++) {
  134. if (dev == larb_mmu[i].dev) {
  135. larb->larbid = i;
  136. larb->mmu = &larb_mmu[i].mmu;
  137. larb->bank = larb_mmu[i].bank;
  138. return 0;
  139. }
  140. }
  141. return -ENODEV;
  142. }
  143. static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
  144. {
  145. struct mtk_smi_larb *larb = dev_get_drvdata(dev);
  146. u32 reg;
  147. int i;
  148. if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
  149. return;
  150. for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
  151. reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
  152. reg |= F_MMU_EN;
  153. reg |= BANK_SEL(larb->bank[i]);
  154. writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
  155. }
  156. }
  157. static void mtk_smi_larb_config_port_mt8173(struct device *dev)
  158. {
  159. struct mtk_smi_larb *larb = dev_get_drvdata(dev);
  160. writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
  161. }
  162. static void mtk_smi_larb_config_port_mt8167(struct device *dev)
  163. {
  164. struct mtk_smi_larb *larb = dev_get_drvdata(dev);
  165. writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
  166. }
  167. static void mtk_smi_larb_config_port_gen1(struct device *dev)
  168. {
  169. struct mtk_smi_larb *larb = dev_get_drvdata(dev);
  170. const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
  171. struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
  172. int i, m4u_port_id, larb_port_num;
  173. u32 sec_con_val, reg_val;
  174. m4u_port_id = larb_gen->port_in_larb[larb->larbid];
  175. larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
  176. - larb_gen->port_in_larb[larb->larbid];
  177. for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
  178. if (*larb->mmu & BIT(i)) {
  179. /* bit[port + 3] controls the virtual or physical */
  180. sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
  181. } else {
  182. /* do not need to enable m4u for this port */
  183. continue;
  184. }
  185. reg_val = readl(common->smi_ao_base
  186. + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
  187. reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
  188. reg_val |= sec_con_val;
  189. reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
  190. writel(reg_val,
  191. common->smi_ao_base
  192. + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
  193. }
  194. }
  195. static void
  196. mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
  197. {
  198. /* Do nothing as the iommu is always enabled. */
  199. }
  200. static const struct component_ops mtk_smi_larb_component_ops = {
  201. .bind = mtk_smi_larb_bind,
  202. .unbind = mtk_smi_larb_unbind,
  203. };
  204. static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
  205. /* mt8173 do not need the port in larb */
  206. .config_port = mtk_smi_larb_config_port_mt8173,
  207. };
  208. static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
  209. /* mt8167 do not need the port in larb */
  210. .config_port = mtk_smi_larb_config_port_mt8167,
  211. };
  212. static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
  213. .port_in_larb = {
  214. LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
  215. LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
  216. },
  217. .config_port = mtk_smi_larb_config_port_gen1,
  218. };
  219. static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
  220. .config_port = mtk_smi_larb_config_port_gen2_general,
  221. .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
  222. };
  223. static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
  224. .config_port = mtk_smi_larb_config_port_gen2_general,
  225. .larb_direct_to_common_mask =
  226. BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
  227. /* DUMMY | IPU0 | IPU1 | CCU | MDLA */
  228. };
  229. static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
  230. .has_gals = true,
  231. .config_port = mtk_smi_larb_config_port_gen2_general,
  232. .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
  233. /* IPU0 | IPU1 | CCU */
  234. };
  235. static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
  236. .config_port = mtk_smi_larb_config_port_gen2_general,
  237. };
  238. static const struct of_device_id mtk_smi_larb_of_ids[] = {
  239. {
  240. .compatible = "mediatek,mt8167-smi-larb",
  241. .data = &mtk_smi_larb_mt8167
  242. },
  243. {
  244. .compatible = "mediatek,mt8173-smi-larb",
  245. .data = &mtk_smi_larb_mt8173
  246. },
  247. {
  248. .compatible = "mediatek,mt2701-smi-larb",
  249. .data = &mtk_smi_larb_mt2701
  250. },
  251. {
  252. .compatible = "mediatek,mt2712-smi-larb",
  253. .data = &mtk_smi_larb_mt2712
  254. },
  255. {
  256. .compatible = "mediatek,mt6779-smi-larb",
  257. .data = &mtk_smi_larb_mt6779
  258. },
  259. {
  260. .compatible = "mediatek,mt8183-smi-larb",
  261. .data = &mtk_smi_larb_mt8183
  262. },
  263. {
  264. .compatible = "mediatek,mt8192-smi-larb",
  265. .data = &mtk_smi_larb_mt8192
  266. },
  267. {}
  268. };
  269. static int mtk_smi_larb_probe(struct platform_device *pdev)
  270. {
  271. struct mtk_smi_larb *larb;
  272. struct resource *res;
  273. struct device *dev = &pdev->dev;
  274. struct device_node *smi_node;
  275. struct platform_device *smi_pdev;
  276. larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
  277. if (!larb)
  278. return -ENOMEM;
  279. larb->larb_gen = of_device_get_match_data(dev);
  280. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  281. larb->base = devm_ioremap_resource(dev, res);
  282. if (IS_ERR(larb->base))
  283. return PTR_ERR(larb->base);
  284. larb->smi.clk_apb = devm_clk_get(dev, "apb");
  285. if (IS_ERR(larb->smi.clk_apb))
  286. return PTR_ERR(larb->smi.clk_apb);
  287. larb->smi.clk_smi = devm_clk_get(dev, "smi");
  288. if (IS_ERR(larb->smi.clk_smi))
  289. return PTR_ERR(larb->smi.clk_smi);
  290. if (larb->larb_gen->has_gals) {
  291. /* The larbs may still haven't gals even if the SoC support.*/
  292. larb->smi.clk_gals0 = devm_clk_get(dev, "gals");
  293. if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT)
  294. larb->smi.clk_gals0 = NULL;
  295. else if (IS_ERR(larb->smi.clk_gals0))
  296. return PTR_ERR(larb->smi.clk_gals0);
  297. }
  298. larb->smi.dev = dev;
  299. smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
  300. if (!smi_node)
  301. return -EINVAL;
  302. smi_pdev = of_find_device_by_node(smi_node);
  303. of_node_put(smi_node);
  304. if (smi_pdev) {
  305. if (!platform_get_drvdata(smi_pdev))
  306. return -EPROBE_DEFER;
  307. larb->smi_common_dev = &smi_pdev->dev;
  308. } else {
  309. dev_err(dev, "Failed to get the smi_common device\n");
  310. return -EINVAL;
  311. }
  312. pm_runtime_enable(dev);
  313. platform_set_drvdata(pdev, larb);
  314. return component_add(dev, &mtk_smi_larb_component_ops);
  315. }
  316. static int mtk_smi_larb_remove(struct platform_device *pdev)
  317. {
  318. pm_runtime_disable(&pdev->dev);
  319. component_del(&pdev->dev, &mtk_smi_larb_component_ops);
  320. return 0;
  321. }
  322. static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
  323. {
  324. struct mtk_smi_larb *larb = dev_get_drvdata(dev);
  325. const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
  326. int ret;
  327. /* Power on smi-common. */
  328. ret = pm_runtime_resume_and_get(larb->smi_common_dev);
  329. if (ret < 0) {
  330. dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret);
  331. return ret;
  332. }
  333. ret = mtk_smi_clk_enable(&larb->smi);
  334. if (ret < 0) {
  335. dev_err(dev, "Failed to enable clock(%d).\n", ret);
  336. pm_runtime_put_sync(larb->smi_common_dev);
  337. return ret;
  338. }
  339. /* Configure the basic setting for this larb */
  340. larb_gen->config_port(dev);
  341. return 0;
  342. }
  343. static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
  344. {
  345. struct mtk_smi_larb *larb = dev_get_drvdata(dev);
  346. mtk_smi_clk_disable(&larb->smi);
  347. pm_runtime_put_sync(larb->smi_common_dev);
  348. return 0;
  349. }
  350. static const struct dev_pm_ops smi_larb_pm_ops = {
  351. SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
  352. SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  353. pm_runtime_force_resume)
  354. };
  355. static struct platform_driver mtk_smi_larb_driver = {
  356. .probe = mtk_smi_larb_probe,
  357. .remove = mtk_smi_larb_remove,
  358. .driver = {
  359. .name = "mtk-smi-larb",
  360. .of_match_table = mtk_smi_larb_of_ids,
  361. .pm = &smi_larb_pm_ops,
  362. }
  363. };
  364. static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
  365. .gen = MTK_SMI_GEN1,
  366. };
  367. static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
  368. .gen = MTK_SMI_GEN2,
  369. };
  370. static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
  371. .gen = MTK_SMI_GEN2,
  372. .has_gals = true,
  373. .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
  374. F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
  375. };
  376. static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
  377. .gen = MTK_SMI_GEN2,
  378. .has_gals = true,
  379. .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
  380. F_MMU1_LARB(7),
  381. };
  382. static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
  383. .gen = MTK_SMI_GEN2,
  384. .has_gals = true,
  385. .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
  386. F_MMU1_LARB(6),
  387. };
  388. static const struct of_device_id mtk_smi_common_of_ids[] = {
  389. {
  390. .compatible = "mediatek,mt8173-smi-common",
  391. .data = &mtk_smi_common_gen2,
  392. },
  393. {
  394. .compatible = "mediatek,mt8167-smi-common",
  395. .data = &mtk_smi_common_gen2,
  396. },
  397. {
  398. .compatible = "mediatek,mt2701-smi-common",
  399. .data = &mtk_smi_common_gen1,
  400. },
  401. {
  402. .compatible = "mediatek,mt2712-smi-common",
  403. .data = &mtk_smi_common_gen2,
  404. },
  405. {
  406. .compatible = "mediatek,mt6779-smi-common",
  407. .data = &mtk_smi_common_mt6779,
  408. },
  409. {
  410. .compatible = "mediatek,mt8183-smi-common",
  411. .data = &mtk_smi_common_mt8183,
  412. },
  413. {
  414. .compatible = "mediatek,mt8192-smi-common",
  415. .data = &mtk_smi_common_mt8192,
  416. },
  417. {}
  418. };
  419. static int mtk_smi_common_probe(struct platform_device *pdev)
  420. {
  421. struct device *dev = &pdev->dev;
  422. struct mtk_smi *common;
  423. struct resource *res;
  424. int ret;
  425. common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
  426. if (!common)
  427. return -ENOMEM;
  428. common->dev = dev;
  429. common->plat = of_device_get_match_data(dev);
  430. common->clk_apb = devm_clk_get(dev, "apb");
  431. if (IS_ERR(common->clk_apb))
  432. return PTR_ERR(common->clk_apb);
  433. common->clk_smi = devm_clk_get(dev, "smi");
  434. if (IS_ERR(common->clk_smi))
  435. return PTR_ERR(common->clk_smi);
  436. if (common->plat->has_gals) {
  437. common->clk_gals0 = devm_clk_get(dev, "gals0");
  438. if (IS_ERR(common->clk_gals0))
  439. return PTR_ERR(common->clk_gals0);
  440. common->clk_gals1 = devm_clk_get(dev, "gals1");
  441. if (IS_ERR(common->clk_gals1))
  442. return PTR_ERR(common->clk_gals1);
  443. }
  444. /*
  445. * for mtk smi gen 1, we need to get the ao(always on) base to config
  446. * m4u port, and we need to enable the aync clock for transform the smi
  447. * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
  448. * base.
  449. */
  450. if (common->plat->gen == MTK_SMI_GEN1) {
  451. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  452. common->smi_ao_base = devm_ioremap_resource(dev, res);
  453. if (IS_ERR(common->smi_ao_base))
  454. return PTR_ERR(common->smi_ao_base);
  455. common->clk_async = devm_clk_get(dev, "async");
  456. if (IS_ERR(common->clk_async))
  457. return PTR_ERR(common->clk_async);
  458. ret = clk_prepare_enable(common->clk_async);
  459. if (ret)
  460. return ret;
  461. } else {
  462. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  463. common->base = devm_ioremap_resource(dev, res);
  464. if (IS_ERR(common->base))
  465. return PTR_ERR(common->base);
  466. }
  467. pm_runtime_enable(dev);
  468. platform_set_drvdata(pdev, common);
  469. return 0;
  470. }
  471. static int mtk_smi_common_remove(struct platform_device *pdev)
  472. {
  473. pm_runtime_disable(&pdev->dev);
  474. return 0;
  475. }
  476. static int __maybe_unused mtk_smi_common_resume(struct device *dev)
  477. {
  478. struct mtk_smi *common = dev_get_drvdata(dev);
  479. u32 bus_sel = common->plat->bus_sel;
  480. int ret;
  481. ret = mtk_smi_clk_enable(common);
  482. if (ret) {
  483. dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
  484. return ret;
  485. }
  486. if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
  487. writel(bus_sel, common->base + SMI_BUS_SEL);
  488. return 0;
  489. }
  490. static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
  491. {
  492. struct mtk_smi *common = dev_get_drvdata(dev);
  493. mtk_smi_clk_disable(common);
  494. return 0;
  495. }
  496. static const struct dev_pm_ops smi_common_pm_ops = {
  497. SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
  498. SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  499. pm_runtime_force_resume)
  500. };
  501. static struct platform_driver mtk_smi_common_driver = {
  502. .probe = mtk_smi_common_probe,
  503. .remove = mtk_smi_common_remove,
  504. .driver = {
  505. .name = "mtk-smi-common",
  506. .of_match_table = mtk_smi_common_of_ids,
  507. .pm = &smi_common_pm_ops,
  508. }
  509. };
  510. static struct platform_driver * const smidrivers[] = {
  511. &mtk_smi_common_driver,
  512. &mtk_smi_larb_driver,
  513. };
  514. static int __init mtk_smi_init(void)
  515. {
  516. return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers));
  517. }
  518. module_init(mtk_smi_init);
  519. static void __exit mtk_smi_exit(void)
  520. {
  521. platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers));
  522. }
  523. module_exit(mtk_smi_exit);
  524. MODULE_DESCRIPTION("MediaTek SMI driver");
  525. MODULE_LICENSE("GPL v2");