jedec_ddr_data.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * DDR addressing details and AC timing parameters from JEDEC specs
  4. *
  5. * Copyright (C) 2012 Texas Instruments, Inc.
  6. *
  7. * Aneesh V <aneesh@ti.com>
  8. */
  9. #include <linux/export.h>
  10. #include "jedec_ddr.h"
  11. /* LPDDR2 addressing details from JESD209-2 section 2.4 */
  12. const struct lpddr2_addressing
  13. lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
  14. {B4, T_REFI_15_6, T_RFC_90}, /* 64M */
  15. {B4, T_REFI_15_6, T_RFC_90}, /* 128M */
  16. {B4, T_REFI_7_8, T_RFC_90}, /* 256M */
  17. {B4, T_REFI_7_8, T_RFC_90}, /* 512M */
  18. {B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
  19. {B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
  20. {B8, T_REFI_3_9, T_RFC_130}, /* 4G */
  21. {B8, T_REFI_3_9, T_RFC_210}, /* 8G */
  22. {B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
  23. {B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
  24. };
  25. EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
  26. /* LPDDR2 AC timing parameters from JESD209-2 section 12 */
  27. const struct lpddr2_timings
  28. lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
  29. /* Speed bin 400(200 MHz) */
  30. [0] = {
  31. .max_freq = 200000000,
  32. .min_freq = 10000000,
  33. .tRPab = 21000,
  34. .tRCD = 18000,
  35. .tWR = 15000,
  36. .tRAS_min = 42000,
  37. .tRRD = 10000,
  38. .tWTR = 10000,
  39. .tXP = 7500,
  40. .tRTP = 7500,
  41. .tCKESR = 15000,
  42. .tDQSCK_max = 5500,
  43. .tFAW = 50000,
  44. .tZQCS = 90000,
  45. .tZQCL = 360000,
  46. .tZQinit = 1000000,
  47. .tRAS_max_ns = 70000,
  48. .tDQSCK_max_derated = 6000,
  49. },
  50. /* Speed bin 533(266 MHz) */
  51. [1] = {
  52. .max_freq = 266666666,
  53. .min_freq = 10000000,
  54. .tRPab = 21000,
  55. .tRCD = 18000,
  56. .tWR = 15000,
  57. .tRAS_min = 42000,
  58. .tRRD = 10000,
  59. .tWTR = 7500,
  60. .tXP = 7500,
  61. .tRTP = 7500,
  62. .tCKESR = 15000,
  63. .tDQSCK_max = 5500,
  64. .tFAW = 50000,
  65. .tZQCS = 90000,
  66. .tZQCL = 360000,
  67. .tZQinit = 1000000,
  68. .tRAS_max_ns = 70000,
  69. .tDQSCK_max_derated = 6000,
  70. },
  71. /* Speed bin 800(400 MHz) */
  72. [2] = {
  73. .max_freq = 400000000,
  74. .min_freq = 10000000,
  75. .tRPab = 21000,
  76. .tRCD = 18000,
  77. .tWR = 15000,
  78. .tRAS_min = 42000,
  79. .tRRD = 10000,
  80. .tWTR = 7500,
  81. .tXP = 7500,
  82. .tRTP = 7500,
  83. .tCKESR = 15000,
  84. .tDQSCK_max = 5500,
  85. .tFAW = 50000,
  86. .tZQCS = 90000,
  87. .tZQCL = 360000,
  88. .tZQinit = 1000000,
  89. .tRAS_max_ns = 70000,
  90. .tDQSCK_max_derated = 6000,
  91. },
  92. /* Speed bin 1066(533 MHz) */
  93. [3] = {
  94. .max_freq = 533333333,
  95. .min_freq = 10000000,
  96. .tRPab = 21000,
  97. .tRCD = 18000,
  98. .tWR = 15000,
  99. .tRAS_min = 42000,
  100. .tRRD = 10000,
  101. .tWTR = 7500,
  102. .tXP = 7500,
  103. .tRTP = 7500,
  104. .tCKESR = 15000,
  105. .tDQSCK_max = 5500,
  106. .tFAW = 50000,
  107. .tZQCS = 90000,
  108. .tZQCL = 360000,
  109. .tZQinit = 1000000,
  110. .tRAS_max_ns = 70000,
  111. .tDQSCK_max_derated = 5620,
  112. },
  113. };
  114. EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
  115. const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
  116. .tRPab = 3,
  117. .tRCD = 3,
  118. .tWR = 3,
  119. .tRASmin = 3,
  120. .tRRD = 2,
  121. .tWTR = 2,
  122. .tXP = 2,
  123. .tRTP = 2,
  124. .tCKE = 3,
  125. .tCKESR = 3,
  126. .tFAW = 8
  127. };
  128. EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);