qcom-ipcc.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/bitfield.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/irq.h>
  8. #include <linux/irqdomain.h>
  9. #include <linux/mailbox_controller.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <dt-bindings/mailbox/qcom-ipcc.h>
  13. #define IPCC_MBOX_MAX_CHAN 48
  14. /* IPCC Register offsets */
  15. #define IPCC_REG_SEND_ID 0x0c
  16. #define IPCC_REG_RECV_ID 0x10
  17. #define IPCC_REG_RECV_SIGNAL_ENABLE 0x14
  18. #define IPCC_REG_RECV_SIGNAL_DISABLE 0x18
  19. #define IPCC_REG_RECV_SIGNAL_CLEAR 0x1c
  20. #define IPCC_REG_CLIENT_CLEAR 0x38
  21. #define IPCC_SIGNAL_ID_MASK GENMASK(15, 0)
  22. #define IPCC_CLIENT_ID_MASK GENMASK(31, 16)
  23. #define IPCC_NO_PENDING_IRQ GENMASK(31, 0)
  24. /**
  25. * struct qcom_ipcc_chan_info - Per-mailbox-channel info
  26. * @client_id: The client-id to which the interrupt has to be triggered
  27. * @signal_id: The signal-id to which the interrupt has to be triggered
  28. */
  29. struct qcom_ipcc_chan_info {
  30. u16 client_id;
  31. u16 signal_id;
  32. };
  33. /**
  34. * struct qcom_ipcc - Holder for the mailbox driver
  35. * @dev: Device associated with this instance
  36. * @base: Base address of the IPCC frame associated to APSS
  37. * @irq_domain: The irq_domain associated with this instance
  38. * @chan: The mailbox channels array
  39. * @mchan: The per-mailbox channel info array
  40. * @mbox: The mailbox controller
  41. * @irq: Summary irq
  42. */
  43. struct qcom_ipcc {
  44. struct device *dev;
  45. void __iomem *base;
  46. struct irq_domain *irq_domain;
  47. struct mbox_chan chan[IPCC_MBOX_MAX_CHAN];
  48. struct qcom_ipcc_chan_info mchan[IPCC_MBOX_MAX_CHAN];
  49. struct mbox_controller mbox;
  50. int irq;
  51. };
  52. static inline struct qcom_ipcc *to_qcom_ipcc(struct mbox_controller *mbox)
  53. {
  54. return container_of(mbox, struct qcom_ipcc, mbox);
  55. }
  56. static inline u32 qcom_ipcc_get_hwirq(u16 client_id, u16 signal_id)
  57. {
  58. return FIELD_PREP(IPCC_CLIENT_ID_MASK, client_id) |
  59. FIELD_PREP(IPCC_SIGNAL_ID_MASK, signal_id);
  60. }
  61. static irqreturn_t qcom_ipcc_irq_fn(int irq, void *data)
  62. {
  63. struct qcom_ipcc *ipcc = data;
  64. u32 hwirq;
  65. int virq;
  66. for (;;) {
  67. hwirq = readl(ipcc->base + IPCC_REG_RECV_ID);
  68. if (hwirq == IPCC_NO_PENDING_IRQ)
  69. break;
  70. virq = irq_find_mapping(ipcc->irq_domain, hwirq);
  71. writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR);
  72. generic_handle_irq(virq);
  73. }
  74. return IRQ_HANDLED;
  75. }
  76. static void qcom_ipcc_mask_irq(struct irq_data *irqd)
  77. {
  78. struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);
  79. irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
  80. writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE);
  81. }
  82. static void qcom_ipcc_unmask_irq(struct irq_data *irqd)
  83. {
  84. struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);
  85. irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
  86. writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE);
  87. }
  88. static struct irq_chip qcom_ipcc_irq_chip = {
  89. .name = "ipcc",
  90. .irq_mask = qcom_ipcc_mask_irq,
  91. .irq_unmask = qcom_ipcc_unmask_irq,
  92. .flags = IRQCHIP_SKIP_SET_WAKE,
  93. };
  94. static int qcom_ipcc_domain_map(struct irq_domain *d, unsigned int irq,
  95. irq_hw_number_t hw)
  96. {
  97. struct qcom_ipcc *ipcc = d->host_data;
  98. irq_set_chip_and_handler(irq, &qcom_ipcc_irq_chip, handle_level_irq);
  99. irq_set_chip_data(irq, ipcc);
  100. irq_set_noprobe(irq);
  101. return 0;
  102. }
  103. static int qcom_ipcc_domain_xlate(struct irq_domain *d,
  104. struct device_node *node, const u32 *intspec,
  105. unsigned int intsize,
  106. unsigned long *out_hwirq,
  107. unsigned int *out_type)
  108. {
  109. if (intsize != 3)
  110. return -EINVAL;
  111. *out_hwirq = qcom_ipcc_get_hwirq(intspec[0], intspec[1]);
  112. *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
  113. return 0;
  114. }
  115. static const struct irq_domain_ops qcom_ipcc_irq_ops = {
  116. .map = qcom_ipcc_domain_map,
  117. .xlate = qcom_ipcc_domain_xlate,
  118. };
  119. static int qcom_ipcc_mbox_send_data(struct mbox_chan *chan, void *data)
  120. {
  121. struct qcom_ipcc *ipcc = to_qcom_ipcc(chan->mbox);
  122. struct qcom_ipcc_chan_info *mchan = chan->con_priv;
  123. u32 hwirq;
  124. hwirq = qcom_ipcc_get_hwirq(mchan->client_id, mchan->signal_id);
  125. writel(hwirq, ipcc->base + IPCC_REG_SEND_ID);
  126. return 0;
  127. }
  128. static void qcom_ipcc_mbox_shutdown(struct mbox_chan *chan)
  129. {
  130. chan->con_priv = NULL;
  131. }
  132. static struct mbox_chan *qcom_ipcc_mbox_xlate(struct mbox_controller *mbox,
  133. const struct of_phandle_args *ph)
  134. {
  135. struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox);
  136. struct qcom_ipcc_chan_info *mchan;
  137. struct mbox_chan *chan;
  138. unsigned int i;
  139. if (ph->args_count != 2)
  140. return ERR_PTR(-EINVAL);
  141. for (i = 0; i < IPCC_MBOX_MAX_CHAN; i++) {
  142. chan = &ipcc->chan[i];
  143. if (!chan->con_priv) {
  144. mchan = &ipcc->mchan[i];
  145. mchan->client_id = ph->args[0];
  146. mchan->signal_id = ph->args[1];
  147. chan->con_priv = mchan;
  148. break;
  149. }
  150. chan = NULL;
  151. }
  152. return chan ?: ERR_PTR(-EBUSY);
  153. }
  154. static const struct mbox_chan_ops ipcc_mbox_chan_ops = {
  155. .send_data = qcom_ipcc_mbox_send_data,
  156. .shutdown = qcom_ipcc_mbox_shutdown,
  157. };
  158. static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc)
  159. {
  160. struct mbox_controller *mbox;
  161. struct device *dev = ipcc->dev;
  162. mbox = &ipcc->mbox;
  163. mbox->dev = dev;
  164. mbox->num_chans = IPCC_MBOX_MAX_CHAN;
  165. mbox->chans = ipcc->chan;
  166. mbox->ops = &ipcc_mbox_chan_ops;
  167. mbox->of_xlate = qcom_ipcc_mbox_xlate;
  168. mbox->txdone_irq = false;
  169. mbox->txdone_poll = false;
  170. return devm_mbox_controller_register(dev, mbox);
  171. }
  172. static int qcom_ipcc_probe(struct platform_device *pdev)
  173. {
  174. struct qcom_ipcc *ipcc;
  175. int ret;
  176. ipcc = devm_kzalloc(&pdev->dev, sizeof(*ipcc), GFP_KERNEL);
  177. if (!ipcc)
  178. return -ENOMEM;
  179. ipcc->dev = &pdev->dev;
  180. ipcc->base = devm_platform_ioremap_resource(pdev, 0);
  181. if (IS_ERR(ipcc->base))
  182. return PTR_ERR(ipcc->base);
  183. ipcc->irq = platform_get_irq(pdev, 0);
  184. if (ipcc->irq < 0)
  185. return ipcc->irq;
  186. ipcc->irq_domain = irq_domain_add_tree(pdev->dev.of_node,
  187. &qcom_ipcc_irq_ops, ipcc);
  188. if (!ipcc->irq_domain)
  189. return -ENOMEM;
  190. ret = qcom_ipcc_setup_mbox(ipcc);
  191. if (ret)
  192. goto err_mbox;
  193. ret = devm_request_irq(&pdev->dev, ipcc->irq, qcom_ipcc_irq_fn,
  194. IRQF_TRIGGER_HIGH, "ipcc", ipcc);
  195. if (ret < 0) {
  196. dev_err(&pdev->dev, "Failed to register the irq: %d\n", ret);
  197. goto err_mbox;
  198. }
  199. enable_irq_wake(ipcc->irq);
  200. platform_set_drvdata(pdev, ipcc);
  201. return 0;
  202. err_mbox:
  203. irq_domain_remove(ipcc->irq_domain);
  204. return ret;
  205. }
  206. static int qcom_ipcc_remove(struct platform_device *pdev)
  207. {
  208. struct qcom_ipcc *ipcc = platform_get_drvdata(pdev);
  209. disable_irq_wake(ipcc->irq);
  210. irq_domain_remove(ipcc->irq_domain);
  211. return 0;
  212. }
  213. static const struct of_device_id qcom_ipcc_of_match[] = {
  214. { .compatible = "qcom,ipcc"},
  215. {}
  216. };
  217. MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match);
  218. static struct platform_driver qcom_ipcc_driver = {
  219. .probe = qcom_ipcc_probe,
  220. .remove = qcom_ipcc_remove,
  221. .driver = {
  222. .name = "qcom-ipcc",
  223. .of_match_table = qcom_ipcc_of_match,
  224. },
  225. };
  226. static int __init qcom_ipcc_init(void)
  227. {
  228. return platform_driver_register(&qcom_ipcc_driver);
  229. }
  230. arch_initcall(qcom_ipcc_init);
  231. MODULE_AUTHOR("Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>");
  232. MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
  233. MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPCC driver");
  234. MODULE_LICENSE("GPL v2");