pl320-ipc.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2012 Calxeda, Inc.
  4. */
  5. #include <linux/types.h>
  6. #include <linux/err.h>
  7. #include <linux/delay.h>
  8. #include <linux/export.h>
  9. #include <linux/io.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/completion.h>
  12. #include <linux/mutex.h>
  13. #include <linux/notifier.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/device.h>
  16. #include <linux/amba/bus.h>
  17. #include <linux/pl320-ipc.h>
  18. #define IPCMxSOURCE(m) ((m) * 0x40)
  19. #define IPCMxDSET(m) (((m) * 0x40) + 0x004)
  20. #define IPCMxDCLEAR(m) (((m) * 0x40) + 0x008)
  21. #define IPCMxDSTATUS(m) (((m) * 0x40) + 0x00C)
  22. #define IPCMxMODE(m) (((m) * 0x40) + 0x010)
  23. #define IPCMxMSET(m) (((m) * 0x40) + 0x014)
  24. #define IPCMxMCLEAR(m) (((m) * 0x40) + 0x018)
  25. #define IPCMxMSTATUS(m) (((m) * 0x40) + 0x01C)
  26. #define IPCMxSEND(m) (((m) * 0x40) + 0x020)
  27. #define IPCMxDR(m, dr) (((m) * 0x40) + ((dr) * 4) + 0x024)
  28. #define IPCMMIS(irq) (((irq) * 8) + 0x800)
  29. #define IPCMRIS(irq) (((irq) * 8) + 0x804)
  30. #define MBOX_MASK(n) (1 << (n))
  31. #define IPC_TX_MBOX 1
  32. #define IPC_RX_MBOX 2
  33. #define CHAN_MASK(n) (1 << (n))
  34. #define A9_SOURCE 1
  35. #define M3_SOURCE 0
  36. static void __iomem *ipc_base;
  37. static int ipc_irq;
  38. static DEFINE_MUTEX(ipc_m1_lock);
  39. static DECLARE_COMPLETION(ipc_completion);
  40. static ATOMIC_NOTIFIER_HEAD(ipc_notifier);
  41. static inline void set_destination(int source, int mbox)
  42. {
  43. writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDSET(mbox));
  44. writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMSET(mbox));
  45. }
  46. static inline void clear_destination(int source, int mbox)
  47. {
  48. writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDCLEAR(mbox));
  49. writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMCLEAR(mbox));
  50. }
  51. static void __ipc_send(int mbox, u32 *data)
  52. {
  53. int i;
  54. for (i = 0; i < 7; i++)
  55. writel_relaxed(data[i], ipc_base + IPCMxDR(mbox, i));
  56. writel_relaxed(0x1, ipc_base + IPCMxSEND(mbox));
  57. }
  58. static u32 __ipc_rcv(int mbox, u32 *data)
  59. {
  60. int i;
  61. for (i = 0; i < 7; i++)
  62. data[i] = readl_relaxed(ipc_base + IPCMxDR(mbox, i));
  63. return data[1];
  64. }
  65. /* blocking implmentation from the A9 side, not usuable in interrupts! */
  66. int pl320_ipc_transmit(u32 *data)
  67. {
  68. int ret;
  69. mutex_lock(&ipc_m1_lock);
  70. init_completion(&ipc_completion);
  71. __ipc_send(IPC_TX_MBOX, data);
  72. ret = wait_for_completion_timeout(&ipc_completion,
  73. msecs_to_jiffies(1000));
  74. if (ret == 0) {
  75. ret = -ETIMEDOUT;
  76. goto out;
  77. }
  78. ret = __ipc_rcv(IPC_TX_MBOX, data);
  79. out:
  80. mutex_unlock(&ipc_m1_lock);
  81. return ret;
  82. }
  83. EXPORT_SYMBOL_GPL(pl320_ipc_transmit);
  84. static irqreturn_t ipc_handler(int irq, void *dev)
  85. {
  86. u32 irq_stat;
  87. u32 data[7];
  88. irq_stat = readl_relaxed(ipc_base + IPCMMIS(1));
  89. if (irq_stat & MBOX_MASK(IPC_TX_MBOX)) {
  90. writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
  91. complete(&ipc_completion);
  92. }
  93. if (irq_stat & MBOX_MASK(IPC_RX_MBOX)) {
  94. __ipc_rcv(IPC_RX_MBOX, data);
  95. atomic_notifier_call_chain(&ipc_notifier, data[0], data + 1);
  96. writel_relaxed(2, ipc_base + IPCMxSEND(IPC_RX_MBOX));
  97. }
  98. return IRQ_HANDLED;
  99. }
  100. int pl320_ipc_register_notifier(struct notifier_block *nb)
  101. {
  102. return atomic_notifier_chain_register(&ipc_notifier, nb);
  103. }
  104. EXPORT_SYMBOL_GPL(pl320_ipc_register_notifier);
  105. int pl320_ipc_unregister_notifier(struct notifier_block *nb)
  106. {
  107. return atomic_notifier_chain_unregister(&ipc_notifier, nb);
  108. }
  109. EXPORT_SYMBOL_GPL(pl320_ipc_unregister_notifier);
  110. static int pl320_probe(struct amba_device *adev, const struct amba_id *id)
  111. {
  112. int ret;
  113. ipc_base = ioremap(adev->res.start, resource_size(&adev->res));
  114. if (ipc_base == NULL)
  115. return -ENOMEM;
  116. writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
  117. ipc_irq = adev->irq[0];
  118. ret = request_irq(ipc_irq, ipc_handler, 0, dev_name(&adev->dev), NULL);
  119. if (ret < 0)
  120. goto err;
  121. /* Init slow mailbox */
  122. writel_relaxed(CHAN_MASK(A9_SOURCE),
  123. ipc_base + IPCMxSOURCE(IPC_TX_MBOX));
  124. writel_relaxed(CHAN_MASK(M3_SOURCE),
  125. ipc_base + IPCMxDSET(IPC_TX_MBOX));
  126. writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
  127. ipc_base + IPCMxMSET(IPC_TX_MBOX));
  128. /* Init receive mailbox */
  129. writel_relaxed(CHAN_MASK(M3_SOURCE),
  130. ipc_base + IPCMxSOURCE(IPC_RX_MBOX));
  131. writel_relaxed(CHAN_MASK(A9_SOURCE),
  132. ipc_base + IPCMxDSET(IPC_RX_MBOX));
  133. writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
  134. ipc_base + IPCMxMSET(IPC_RX_MBOX));
  135. return 0;
  136. err:
  137. iounmap(ipc_base);
  138. return ret;
  139. }
  140. static struct amba_id pl320_ids[] = {
  141. {
  142. .id = 0x00041320,
  143. .mask = 0x000fffff,
  144. },
  145. { 0, 0 },
  146. };
  147. static struct amba_driver pl320_driver = {
  148. .drv = {
  149. .name = "pl320",
  150. },
  151. .id_table = pl320_ids,
  152. .probe = pl320_probe,
  153. };
  154. static int __init ipc_init(void)
  155. {
  156. return amba_driver_register(&pl320_driver);
  157. }
  158. subsys_initcall(ipc_init);