mtk-cmdq-mailbox.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2018 MediaTek Inc.
  4. #include <linux/bitops.h>
  5. #include <linux/clk.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/errno.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/io.h>
  11. #include <linux/iopoll.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/mailbox_controller.h>
  16. #include <linux/mailbox/mtk-cmdq-mailbox.h>
  17. #include <linux/of_device.h>
  18. #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
  19. #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
  20. #define CMDQ_CURR_IRQ_STATUS 0x10
  21. #define CMDQ_SYNC_TOKEN_UPDATE 0x68
  22. #define CMDQ_THR_SLOT_CYCLES 0x30
  23. #define CMDQ_THR_BASE 0x100
  24. #define CMDQ_THR_SIZE 0x80
  25. #define CMDQ_THR_WARM_RESET 0x00
  26. #define CMDQ_THR_ENABLE_TASK 0x04
  27. #define CMDQ_THR_SUSPEND_TASK 0x08
  28. #define CMDQ_THR_CURR_STATUS 0x0c
  29. #define CMDQ_THR_IRQ_STATUS 0x10
  30. #define CMDQ_THR_IRQ_ENABLE 0x14
  31. #define CMDQ_THR_CURR_ADDR 0x20
  32. #define CMDQ_THR_END_ADDR 0x24
  33. #define CMDQ_THR_WAIT_TOKEN 0x30
  34. #define CMDQ_THR_PRIORITY 0x40
  35. #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
  36. #define CMDQ_THR_ENABLED 0x1
  37. #define CMDQ_THR_DISABLED 0x0
  38. #define CMDQ_THR_SUSPEND 0x1
  39. #define CMDQ_THR_RESUME 0x0
  40. #define CMDQ_THR_STATUS_SUSPENDED BIT(1)
  41. #define CMDQ_THR_DO_WARM_RESET BIT(0)
  42. #define CMDQ_THR_IRQ_DONE 0x1
  43. #define CMDQ_THR_IRQ_ERROR 0x12
  44. #define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE)
  45. #define CMDQ_THR_IS_WAITING BIT(31)
  46. #define CMDQ_JUMP_BY_OFFSET 0x10000000
  47. #define CMDQ_JUMP_BY_PA 0x10000001
  48. struct cmdq_thread {
  49. struct mbox_chan *chan;
  50. void __iomem *base;
  51. struct list_head task_busy_list;
  52. u32 priority;
  53. };
  54. struct cmdq_task {
  55. struct cmdq *cmdq;
  56. struct list_head list_entry;
  57. dma_addr_t pa_base;
  58. struct cmdq_thread *thread;
  59. struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
  60. };
  61. struct cmdq {
  62. struct mbox_controller mbox;
  63. void __iomem *base;
  64. int irq;
  65. u32 thread_nr;
  66. u32 irq_mask;
  67. struct cmdq_thread *thread;
  68. struct clk *clock;
  69. bool suspended;
  70. u8 shift_pa;
  71. };
  72. struct gce_plat {
  73. u32 thread_nr;
  74. u8 shift;
  75. };
  76. u8 cmdq_get_shift_pa(struct mbox_chan *chan)
  77. {
  78. struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
  79. return cmdq->shift_pa;
  80. }
  81. EXPORT_SYMBOL(cmdq_get_shift_pa);
  82. static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
  83. {
  84. u32 status;
  85. writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
  86. /* If already disabled, treat as suspended successful. */
  87. if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
  88. return 0;
  89. if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
  90. status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
  91. dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
  92. (u32)(thread->base - cmdq->base));
  93. return -EFAULT;
  94. }
  95. return 0;
  96. }
  97. static void cmdq_thread_resume(struct cmdq_thread *thread)
  98. {
  99. writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
  100. }
  101. static void cmdq_init(struct cmdq *cmdq)
  102. {
  103. int i;
  104. WARN_ON(clk_enable(cmdq->clock) < 0);
  105. writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
  106. for (i = 0; i <= CMDQ_MAX_EVENT; i++)
  107. writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
  108. clk_disable(cmdq->clock);
  109. }
  110. static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
  111. {
  112. u32 warm_reset;
  113. writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
  114. if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
  115. warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
  116. 0, 10)) {
  117. dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
  118. (u32)(thread->base - cmdq->base));
  119. return -EFAULT;
  120. }
  121. return 0;
  122. }
  123. static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread)
  124. {
  125. cmdq_thread_reset(cmdq, thread);
  126. writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
  127. }
  128. /* notify GCE to re-fetch commands by setting GCE thread PC */
  129. static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
  130. {
  131. writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
  132. thread->base + CMDQ_THR_CURR_ADDR);
  133. }
  134. static void cmdq_task_insert_into_thread(struct cmdq_task *task)
  135. {
  136. struct device *dev = task->cmdq->mbox.dev;
  137. struct cmdq_thread *thread = task->thread;
  138. struct cmdq_task *prev_task = list_last_entry(
  139. &thread->task_busy_list, typeof(*task), list_entry);
  140. u64 *prev_task_base = prev_task->pkt->va_base;
  141. /* let previous task jump to this task */
  142. dma_sync_single_for_cpu(dev, prev_task->pa_base,
  143. prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
  144. prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
  145. (u64)CMDQ_JUMP_BY_PA << 32 |
  146. (task->pa_base >> task->cmdq->shift_pa);
  147. dma_sync_single_for_device(dev, prev_task->pa_base,
  148. prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
  149. cmdq_thread_invalidate_fetched_data(thread);
  150. }
  151. static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
  152. {
  153. return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
  154. }
  155. static void cmdq_task_exec_done(struct cmdq_task *task, enum cmdq_cb_status sta)
  156. {
  157. struct cmdq_task_cb *cb = &task->pkt->async_cb;
  158. struct cmdq_cb_data data;
  159. WARN_ON(cb->cb == (cmdq_async_flush_cb)NULL);
  160. data.sta = sta;
  161. data.data = cb->data;
  162. cb->cb(data);
  163. list_del(&task->list_entry);
  164. }
  165. static void cmdq_task_handle_error(struct cmdq_task *task)
  166. {
  167. struct cmdq_thread *thread = task->thread;
  168. struct cmdq_task *next_task;
  169. struct cmdq *cmdq = task->cmdq;
  170. dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);
  171. WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
  172. next_task = list_first_entry_or_null(&thread->task_busy_list,
  173. struct cmdq_task, list_entry);
  174. if (next_task)
  175. writel(next_task->pa_base >> cmdq->shift_pa,
  176. thread->base + CMDQ_THR_CURR_ADDR);
  177. cmdq_thread_resume(thread);
  178. }
  179. static void cmdq_thread_irq_handler(struct cmdq *cmdq,
  180. struct cmdq_thread *thread)
  181. {
  182. struct cmdq_task *task, *tmp, *curr_task = NULL;
  183. u32 curr_pa, irq_flag, task_end_pa;
  184. bool err;
  185. irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
  186. writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
  187. /*
  188. * When ISR call this function, another CPU core could run
  189. * "release task" right before we acquire the spin lock, and thus
  190. * reset / disable this GCE thread, so we need to check the enable
  191. * bit of this GCE thread.
  192. */
  193. if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
  194. return;
  195. if (irq_flag & CMDQ_THR_IRQ_ERROR)
  196. err = true;
  197. else if (irq_flag & CMDQ_THR_IRQ_DONE)
  198. err = false;
  199. else
  200. return;
  201. curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;
  202. list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
  203. list_entry) {
  204. task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
  205. if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
  206. curr_task = task;
  207. if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) {
  208. cmdq_task_exec_done(task, CMDQ_CB_NORMAL);
  209. kfree(task);
  210. } else if (err) {
  211. cmdq_task_exec_done(task, CMDQ_CB_ERROR);
  212. cmdq_task_handle_error(curr_task);
  213. kfree(task);
  214. }
  215. if (curr_task)
  216. break;
  217. }
  218. if (list_empty(&thread->task_busy_list)) {
  219. cmdq_thread_disable(cmdq, thread);
  220. clk_disable(cmdq->clock);
  221. }
  222. }
  223. static irqreturn_t cmdq_irq_handler(int irq, void *dev)
  224. {
  225. struct cmdq *cmdq = dev;
  226. unsigned long irq_status, flags = 0L;
  227. int bit;
  228. irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
  229. if (!(irq_status ^ cmdq->irq_mask))
  230. return IRQ_NONE;
  231. for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {
  232. struct cmdq_thread *thread = &cmdq->thread[bit];
  233. spin_lock_irqsave(&thread->chan->lock, flags);
  234. cmdq_thread_irq_handler(cmdq, thread);
  235. spin_unlock_irqrestore(&thread->chan->lock, flags);
  236. }
  237. return IRQ_HANDLED;
  238. }
  239. static int cmdq_suspend(struct device *dev)
  240. {
  241. struct cmdq *cmdq = dev_get_drvdata(dev);
  242. struct cmdq_thread *thread;
  243. int i;
  244. bool task_running = false;
  245. cmdq->suspended = true;
  246. for (i = 0; i < cmdq->thread_nr; i++) {
  247. thread = &cmdq->thread[i];
  248. if (!list_empty(&thread->task_busy_list)) {
  249. task_running = true;
  250. break;
  251. }
  252. }
  253. if (task_running)
  254. dev_warn(dev, "exist running task(s) in suspend\n");
  255. clk_unprepare(cmdq->clock);
  256. return 0;
  257. }
  258. static int cmdq_resume(struct device *dev)
  259. {
  260. struct cmdq *cmdq = dev_get_drvdata(dev);
  261. WARN_ON(clk_prepare(cmdq->clock) < 0);
  262. cmdq->suspended = false;
  263. return 0;
  264. }
  265. static int cmdq_remove(struct platform_device *pdev)
  266. {
  267. struct cmdq *cmdq = platform_get_drvdata(pdev);
  268. clk_unprepare(cmdq->clock);
  269. return 0;
  270. }
  271. static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
  272. {
  273. struct cmdq_pkt *pkt = (struct cmdq_pkt *)data;
  274. struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
  275. struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
  276. struct cmdq_task *task;
  277. unsigned long curr_pa, end_pa;
  278. /* Client should not flush new tasks if suspended. */
  279. WARN_ON(cmdq->suspended);
  280. task = kzalloc(sizeof(*task), GFP_ATOMIC);
  281. if (!task)
  282. return -ENOMEM;
  283. task->cmdq = cmdq;
  284. INIT_LIST_HEAD(&task->list_entry);
  285. task->pa_base = pkt->pa_base;
  286. task->thread = thread;
  287. task->pkt = pkt;
  288. if (list_empty(&thread->task_busy_list)) {
  289. WARN_ON(clk_enable(cmdq->clock) < 0);
  290. /*
  291. * The thread reset will clear thread related register to 0,
  292. * including pc, end, priority, irq, suspend and enable. Thus
  293. * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
  294. * thread and make it running.
  295. */
  296. WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
  297. writel(task->pa_base >> cmdq->shift_pa,
  298. thread->base + CMDQ_THR_CURR_ADDR);
  299. writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
  300. thread->base + CMDQ_THR_END_ADDR);
  301. writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
  302. writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
  303. writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
  304. } else {
  305. WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
  306. curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
  307. cmdq->shift_pa;
  308. end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
  309. cmdq->shift_pa;
  310. /* check boundary */
  311. if (curr_pa == end_pa - CMDQ_INST_SIZE ||
  312. curr_pa == end_pa) {
  313. /* set to this task directly */
  314. writel(task->pa_base >> cmdq->shift_pa,
  315. thread->base + CMDQ_THR_CURR_ADDR);
  316. } else {
  317. cmdq_task_insert_into_thread(task);
  318. smp_mb(); /* modify jump before enable thread */
  319. }
  320. writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
  321. thread->base + CMDQ_THR_END_ADDR);
  322. cmdq_thread_resume(thread);
  323. }
  324. list_move_tail(&task->list_entry, &thread->task_busy_list);
  325. return 0;
  326. }
  327. static int cmdq_mbox_startup(struct mbox_chan *chan)
  328. {
  329. return 0;
  330. }
  331. static void cmdq_mbox_shutdown(struct mbox_chan *chan)
  332. {
  333. struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
  334. struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
  335. struct cmdq_task *task, *tmp;
  336. unsigned long flags;
  337. spin_lock_irqsave(&thread->chan->lock, flags);
  338. if (list_empty(&thread->task_busy_list))
  339. goto done;
  340. WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
  341. /* make sure executed tasks have success callback */
  342. cmdq_thread_irq_handler(cmdq, thread);
  343. if (list_empty(&thread->task_busy_list))
  344. goto done;
  345. list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
  346. list_entry) {
  347. cmdq_task_exec_done(task, CMDQ_CB_ERROR);
  348. kfree(task);
  349. }
  350. cmdq_thread_disable(cmdq, thread);
  351. clk_disable(cmdq->clock);
  352. done:
  353. /*
  354. * The thread->task_busy_list empty means thread already disable. The
  355. * cmdq_mbox_send_data() always reset thread which clear disable and
  356. * suspend statue when first pkt send to channel, so there is no need
  357. * to do any operation here, only unlock and leave.
  358. */
  359. spin_unlock_irqrestore(&thread->chan->lock, flags);
  360. }
  361. static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
  362. {
  363. struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
  364. struct cmdq_task_cb *cb;
  365. struct cmdq_cb_data data;
  366. struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
  367. struct cmdq_task *task, *tmp;
  368. unsigned long flags;
  369. u32 enable;
  370. spin_lock_irqsave(&thread->chan->lock, flags);
  371. if (list_empty(&thread->task_busy_list))
  372. goto out;
  373. WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
  374. if (!cmdq_thread_is_in_wfe(thread))
  375. goto wait;
  376. list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
  377. list_entry) {
  378. cb = &task->pkt->async_cb;
  379. if (cb->cb) {
  380. data.sta = CMDQ_CB_ERROR;
  381. data.data = cb->data;
  382. cb->cb(data);
  383. }
  384. list_del(&task->list_entry);
  385. kfree(task);
  386. }
  387. cmdq_thread_resume(thread);
  388. cmdq_thread_disable(cmdq, thread);
  389. clk_disable(cmdq->clock);
  390. out:
  391. spin_unlock_irqrestore(&thread->chan->lock, flags);
  392. return 0;
  393. wait:
  394. cmdq_thread_resume(thread);
  395. spin_unlock_irqrestore(&thread->chan->lock, flags);
  396. if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK,
  397. enable, enable == 0, 1, timeout)) {
  398. dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n",
  399. (u32)(thread->base - cmdq->base));
  400. return -EFAULT;
  401. }
  402. return 0;
  403. }
  404. static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
  405. .send_data = cmdq_mbox_send_data,
  406. .startup = cmdq_mbox_startup,
  407. .shutdown = cmdq_mbox_shutdown,
  408. .flush = cmdq_mbox_flush,
  409. };
  410. static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox,
  411. const struct of_phandle_args *sp)
  412. {
  413. int ind = sp->args[0];
  414. struct cmdq_thread *thread;
  415. if (ind >= mbox->num_chans)
  416. return ERR_PTR(-EINVAL);
  417. thread = (struct cmdq_thread *)mbox->chans[ind].con_priv;
  418. thread->priority = sp->args[1];
  419. thread->chan = &mbox->chans[ind];
  420. return &mbox->chans[ind];
  421. }
  422. static int cmdq_probe(struct platform_device *pdev)
  423. {
  424. struct device *dev = &pdev->dev;
  425. struct resource *res;
  426. struct cmdq *cmdq;
  427. int err, i;
  428. struct gce_plat *plat_data;
  429. cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
  430. if (!cmdq)
  431. return -ENOMEM;
  432. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  433. cmdq->base = devm_ioremap_resource(dev, res);
  434. if (IS_ERR(cmdq->base)) {
  435. dev_err(dev, "failed to ioremap gce\n");
  436. return PTR_ERR(cmdq->base);
  437. }
  438. cmdq->irq = platform_get_irq(pdev, 0);
  439. if (cmdq->irq < 0)
  440. return cmdq->irq;
  441. plat_data = (struct gce_plat *)of_device_get_match_data(dev);
  442. if (!plat_data) {
  443. dev_err(dev, "failed to get match data\n");
  444. return -EINVAL;
  445. }
  446. cmdq->thread_nr = plat_data->thread_nr;
  447. cmdq->shift_pa = plat_data->shift;
  448. cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
  449. err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
  450. "mtk_cmdq", cmdq);
  451. if (err < 0) {
  452. dev_err(dev, "failed to register ISR (%d)\n", err);
  453. return err;
  454. }
  455. dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
  456. dev, cmdq->base, cmdq->irq);
  457. cmdq->clock = devm_clk_get(dev, "gce");
  458. if (IS_ERR(cmdq->clock)) {
  459. dev_err(dev, "failed to get gce clk\n");
  460. return PTR_ERR(cmdq->clock);
  461. }
  462. cmdq->mbox.dev = dev;
  463. cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
  464. sizeof(*cmdq->mbox.chans), GFP_KERNEL);
  465. if (!cmdq->mbox.chans)
  466. return -ENOMEM;
  467. cmdq->mbox.num_chans = cmdq->thread_nr;
  468. cmdq->mbox.ops = &cmdq_mbox_chan_ops;
  469. cmdq->mbox.of_xlate = cmdq_xlate;
  470. /* make use of TXDONE_BY_ACK */
  471. cmdq->mbox.txdone_irq = false;
  472. cmdq->mbox.txdone_poll = false;
  473. cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr,
  474. sizeof(*cmdq->thread), GFP_KERNEL);
  475. if (!cmdq->thread)
  476. return -ENOMEM;
  477. for (i = 0; i < cmdq->thread_nr; i++) {
  478. cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
  479. CMDQ_THR_SIZE * i;
  480. INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
  481. cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i];
  482. }
  483. err = devm_mbox_controller_register(dev, &cmdq->mbox);
  484. if (err < 0) {
  485. dev_err(dev, "failed to register mailbox: %d\n", err);
  486. return err;
  487. }
  488. platform_set_drvdata(pdev, cmdq);
  489. WARN_ON(clk_prepare(cmdq->clock) < 0);
  490. cmdq_init(cmdq);
  491. return 0;
  492. }
  493. static const struct dev_pm_ops cmdq_pm_ops = {
  494. .suspend = cmdq_suspend,
  495. .resume = cmdq_resume,
  496. };
  497. static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
  498. static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
  499. static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3};
  500. static const struct of_device_id cmdq_of_ids[] = {
  501. {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
  502. {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
  503. {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
  504. {}
  505. };
  506. static struct platform_driver cmdq_drv = {
  507. .probe = cmdq_probe,
  508. .remove = cmdq_remove,
  509. .driver = {
  510. .name = "mtk_cmdq",
  511. .pm = &cmdq_pm_ops,
  512. .of_match_table = cmdq_of_ids,
  513. }
  514. };
  515. static int __init cmdq_drv_init(void)
  516. {
  517. return platform_driver_register(&cmdq_drv);
  518. }
  519. static void __exit cmdq_drv_exit(void)
  520. {
  521. platform_driver_unregister(&cmdq_drv);
  522. }
  523. subsys_initcall(cmdq_drv_init);
  524. module_exit(cmdq_drv_exit);
  525. MODULE_LICENSE("GPL v2");