imx-mailbox.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/firmware/imx/ipc.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/iopoll.h>
  10. #include <linux/kernel.h>
  11. #include <linux/mailbox_controller.h>
  12. #include <linux/module.h>
  13. #include <linux/of_device.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/suspend.h>
  16. #include <linux/slab.h>
  17. #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
  18. #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
  19. #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
  20. #define IMX_MU_xSR_BRDIP BIT(9)
  21. /* General Purpose Interrupt Enable */
  22. #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
  23. /* Receive Interrupt Enable */
  24. #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
  25. /* Transmit Interrupt Enable */
  26. #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
  27. /* General Purpose Interrupt Request */
  28. #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
  29. #define IMX_MU_CHANS 16
  30. /* TX0/RX0/RXDB[0-3] */
  31. #define IMX_MU_SCU_CHANS 6
  32. #define IMX_MU_CHAN_NAME_SIZE 20
  33. enum imx_mu_chan_type {
  34. IMX_MU_TYPE_TX, /* Tx */
  35. IMX_MU_TYPE_RX, /* Rx */
  36. IMX_MU_TYPE_TXDB, /* Tx doorbell */
  37. IMX_MU_TYPE_RXDB, /* Rx doorbell */
  38. };
  39. struct imx_sc_rpc_msg_max {
  40. struct imx_sc_rpc_msg hdr;
  41. u32 data[7];
  42. };
  43. struct imx_mu_con_priv {
  44. unsigned int idx;
  45. char irq_desc[IMX_MU_CHAN_NAME_SIZE];
  46. enum imx_mu_chan_type type;
  47. struct mbox_chan *chan;
  48. struct tasklet_struct txdb_tasklet;
  49. };
  50. struct imx_mu_priv {
  51. struct device *dev;
  52. void __iomem *base;
  53. spinlock_t xcr_lock; /* control register lock */
  54. struct mbox_controller mbox;
  55. struct mbox_chan mbox_chans[IMX_MU_CHANS];
  56. struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
  57. const struct imx_mu_dcfg *dcfg;
  58. struct clk *clk;
  59. int irq;
  60. bool suspend;
  61. u32 xcr;
  62. bool side_b;
  63. };
  64. struct imx_mu_dcfg {
  65. int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
  66. int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
  67. void (*init)(struct imx_mu_priv *priv);
  68. u32 xTR[4]; /* Transmit Registers */
  69. u32 xRR[4]; /* Receive Registers */
  70. u32 xSR; /* Status Register */
  71. u32 xCR; /* Control Register */
  72. };
  73. static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
  74. {
  75. return container_of(mbox, struct imx_mu_priv, mbox);
  76. }
  77. static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
  78. {
  79. iowrite32(val, priv->base + offs);
  80. }
  81. static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
  82. {
  83. return ioread32(priv->base + offs);
  84. }
  85. static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
  86. {
  87. unsigned long flags;
  88. u32 val;
  89. spin_lock_irqsave(&priv->xcr_lock, flags);
  90. val = imx_mu_read(priv, priv->dcfg->xCR);
  91. val &= ~clr;
  92. val |= set;
  93. imx_mu_write(priv, val, priv->dcfg->xCR);
  94. spin_unlock_irqrestore(&priv->xcr_lock, flags);
  95. return val;
  96. }
  97. static int imx_mu_generic_tx(struct imx_mu_priv *priv,
  98. struct imx_mu_con_priv *cp,
  99. void *data)
  100. {
  101. u32 *arg = data;
  102. switch (cp->type) {
  103. case IMX_MU_TYPE_TX:
  104. imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
  105. imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
  106. break;
  107. case IMX_MU_TYPE_TXDB:
  108. imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
  109. tasklet_schedule(&cp->txdb_tasklet);
  110. break;
  111. default:
  112. dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
  113. return -EINVAL;
  114. }
  115. return 0;
  116. }
  117. static int imx_mu_generic_rx(struct imx_mu_priv *priv,
  118. struct imx_mu_con_priv *cp)
  119. {
  120. u32 dat;
  121. dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
  122. mbox_chan_received_data(cp->chan, (void *)&dat);
  123. return 0;
  124. }
  125. static int imx_mu_scu_tx(struct imx_mu_priv *priv,
  126. struct imx_mu_con_priv *cp,
  127. void *data)
  128. {
  129. struct imx_sc_rpc_msg_max *msg = data;
  130. u32 *arg = data;
  131. int i, ret;
  132. u32 xsr;
  133. switch (cp->type) {
  134. case IMX_MU_TYPE_TX:
  135. /*
  136. * msg->hdr.size specifies the number of u32 words while
  137. * sizeof yields bytes.
  138. */
  139. if (msg->hdr.size > sizeof(*msg) / 4) {
  140. /*
  141. * The real message size can be different to
  142. * struct imx_sc_rpc_msg_max size
  143. */
  144. dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2);
  145. return -EINVAL;
  146. }
  147. for (i = 0; i < 4 && i < msg->hdr.size; i++)
  148. imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
  149. for (; i < msg->hdr.size; i++) {
  150. ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
  151. xsr,
  152. xsr & IMX_MU_xSR_TEn(i % 4),
  153. 0, 100);
  154. if (ret) {
  155. dev_err(priv->dev, "Send data index: %d timeout\n", i);
  156. return ret;
  157. }
  158. imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
  159. }
  160. imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
  161. break;
  162. default:
  163. dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
  164. return -EINVAL;
  165. }
  166. return 0;
  167. }
  168. static int imx_mu_scu_rx(struct imx_mu_priv *priv,
  169. struct imx_mu_con_priv *cp)
  170. {
  171. struct imx_sc_rpc_msg_max msg;
  172. u32 *data = (u32 *)&msg;
  173. int i, ret;
  174. u32 xsr;
  175. imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
  176. *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
  177. if (msg.hdr.size > sizeof(msg) / 4) {
  178. dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
  179. return -EINVAL;
  180. }
  181. for (i = 1; i < msg.hdr.size; i++) {
  182. ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr,
  183. xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
  184. if (ret) {
  185. dev_err(priv->dev, "timeout read idx %d\n", i);
  186. return ret;
  187. }
  188. *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
  189. }
  190. imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
  191. mbox_chan_received_data(cp->chan, (void *)&msg);
  192. return 0;
  193. }
  194. static void imx_mu_txdb_tasklet(unsigned long data)
  195. {
  196. struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
  197. mbox_chan_txdone(cp->chan, 0);
  198. }
  199. static irqreturn_t imx_mu_isr(int irq, void *p)
  200. {
  201. struct mbox_chan *chan = p;
  202. struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
  203. struct imx_mu_con_priv *cp = chan->con_priv;
  204. u32 val, ctrl;
  205. ctrl = imx_mu_read(priv, priv->dcfg->xCR);
  206. val = imx_mu_read(priv, priv->dcfg->xSR);
  207. switch (cp->type) {
  208. case IMX_MU_TYPE_TX:
  209. val &= IMX_MU_xSR_TEn(cp->idx) &
  210. (ctrl & IMX_MU_xCR_TIEn(cp->idx));
  211. break;
  212. case IMX_MU_TYPE_RX:
  213. val &= IMX_MU_xSR_RFn(cp->idx) &
  214. (ctrl & IMX_MU_xCR_RIEn(cp->idx));
  215. break;
  216. case IMX_MU_TYPE_RXDB:
  217. val &= IMX_MU_xSR_GIPn(cp->idx) &
  218. (ctrl & IMX_MU_xCR_GIEn(cp->idx));
  219. break;
  220. default:
  221. break;
  222. }
  223. if (!val)
  224. return IRQ_NONE;
  225. if (val == IMX_MU_xSR_TEn(cp->idx)) {
  226. imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
  227. mbox_chan_txdone(chan, 0);
  228. } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
  229. priv->dcfg->rx(priv, cp);
  230. } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
  231. imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
  232. mbox_chan_received_data(chan, NULL);
  233. } else {
  234. dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
  235. return IRQ_NONE;
  236. }
  237. if (priv->suspend)
  238. pm_system_wakeup();
  239. return IRQ_HANDLED;
  240. }
  241. static int imx_mu_send_data(struct mbox_chan *chan, void *data)
  242. {
  243. struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
  244. struct imx_mu_con_priv *cp = chan->con_priv;
  245. return priv->dcfg->tx(priv, cp, data);
  246. }
  247. static int imx_mu_startup(struct mbox_chan *chan)
  248. {
  249. struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
  250. struct imx_mu_con_priv *cp = chan->con_priv;
  251. unsigned long irq_flag = IRQF_SHARED;
  252. int ret;
  253. pm_runtime_get_sync(priv->dev);
  254. if (cp->type == IMX_MU_TYPE_TXDB) {
  255. /* Tx doorbell don't have ACK support */
  256. tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
  257. (unsigned long)cp);
  258. return 0;
  259. }
  260. /* IPC MU should be with IRQF_NO_SUSPEND set */
  261. if (!priv->dev->pm_domain)
  262. irq_flag |= IRQF_NO_SUSPEND;
  263. ret = request_irq(priv->irq, imx_mu_isr, irq_flag,
  264. cp->irq_desc, chan);
  265. if (ret) {
  266. dev_err(priv->dev,
  267. "Unable to acquire IRQ %d\n", priv->irq);
  268. return ret;
  269. }
  270. switch (cp->type) {
  271. case IMX_MU_TYPE_RX:
  272. imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
  273. break;
  274. case IMX_MU_TYPE_RXDB:
  275. imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
  276. break;
  277. default:
  278. break;
  279. }
  280. priv->suspend = true;
  281. return 0;
  282. }
  283. static void imx_mu_shutdown(struct mbox_chan *chan)
  284. {
  285. struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
  286. struct imx_mu_con_priv *cp = chan->con_priv;
  287. if (cp->type == IMX_MU_TYPE_TXDB) {
  288. tasklet_kill(&cp->txdb_tasklet);
  289. pm_runtime_put_sync(priv->dev);
  290. return;
  291. }
  292. switch (cp->type) {
  293. case IMX_MU_TYPE_TX:
  294. imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
  295. break;
  296. case IMX_MU_TYPE_RX:
  297. imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
  298. break;
  299. case IMX_MU_TYPE_RXDB:
  300. imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
  301. break;
  302. default:
  303. break;
  304. }
  305. free_irq(priv->irq, chan);
  306. pm_runtime_put_sync(priv->dev);
  307. }
  308. static const struct mbox_chan_ops imx_mu_ops = {
  309. .send_data = imx_mu_send_data,
  310. .startup = imx_mu_startup,
  311. .shutdown = imx_mu_shutdown,
  312. };
  313. static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox,
  314. const struct of_phandle_args *sp)
  315. {
  316. u32 type, idx, chan;
  317. if (sp->args_count != 2) {
  318. dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
  319. return ERR_PTR(-EINVAL);
  320. }
  321. type = sp->args[0]; /* channel type */
  322. idx = sp->args[1]; /* index */
  323. switch (type) {
  324. case IMX_MU_TYPE_TX:
  325. case IMX_MU_TYPE_RX:
  326. if (idx != 0)
  327. dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
  328. chan = type;
  329. break;
  330. case IMX_MU_TYPE_RXDB:
  331. chan = 2 + idx;
  332. break;
  333. default:
  334. dev_err(mbox->dev, "Invalid chan type: %d\n", type);
  335. return ERR_PTR(-EINVAL);
  336. }
  337. if (chan >= mbox->num_chans) {
  338. dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
  339. return ERR_PTR(-EINVAL);
  340. }
  341. return &mbox->chans[chan];
  342. }
  343. static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
  344. const struct of_phandle_args *sp)
  345. {
  346. u32 type, idx, chan;
  347. if (sp->args_count != 2) {
  348. dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
  349. return ERR_PTR(-EINVAL);
  350. }
  351. type = sp->args[0]; /* channel type */
  352. idx = sp->args[1]; /* index */
  353. chan = type * 4 + idx;
  354. if (chan >= mbox->num_chans) {
  355. dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
  356. return ERR_PTR(-EINVAL);
  357. }
  358. return &mbox->chans[chan];
  359. }
  360. static void imx_mu_init_generic(struct imx_mu_priv *priv)
  361. {
  362. unsigned int i;
  363. for (i = 0; i < IMX_MU_CHANS; i++) {
  364. struct imx_mu_con_priv *cp = &priv->con_priv[i];
  365. cp->idx = i % 4;
  366. cp->type = i >> 2;
  367. cp->chan = &priv->mbox_chans[i];
  368. priv->mbox_chans[i].con_priv = cp;
  369. snprintf(cp->irq_desc, sizeof(cp->irq_desc),
  370. "imx_mu_chan[%i-%i]", cp->type, cp->idx);
  371. }
  372. priv->mbox.num_chans = IMX_MU_CHANS;
  373. priv->mbox.of_xlate = imx_mu_xlate;
  374. if (priv->side_b)
  375. return;
  376. /* Set default MU configuration */
  377. imx_mu_write(priv, 0, priv->dcfg->xCR);
  378. }
  379. static void imx_mu_init_scu(struct imx_mu_priv *priv)
  380. {
  381. unsigned int i;
  382. for (i = 0; i < IMX_MU_SCU_CHANS; i++) {
  383. struct imx_mu_con_priv *cp = &priv->con_priv[i];
  384. cp->idx = i < 2 ? 0 : i - 2;
  385. cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
  386. cp->chan = &priv->mbox_chans[i];
  387. priv->mbox_chans[i].con_priv = cp;
  388. snprintf(cp->irq_desc, sizeof(cp->irq_desc),
  389. "imx_mu_chan[%i-%i]", cp->type, cp->idx);
  390. }
  391. priv->mbox.num_chans = IMX_MU_SCU_CHANS;
  392. priv->mbox.of_xlate = imx_mu_scu_xlate;
  393. /* Set default MU configuration */
  394. imx_mu_write(priv, 0, priv->dcfg->xCR);
  395. }
  396. static int imx_mu_probe(struct platform_device *pdev)
  397. {
  398. struct device *dev = &pdev->dev;
  399. struct device_node *np = dev->of_node;
  400. struct imx_mu_priv *priv;
  401. const struct imx_mu_dcfg *dcfg;
  402. int ret;
  403. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  404. if (!priv)
  405. return -ENOMEM;
  406. priv->dev = dev;
  407. priv->base = devm_platform_ioremap_resource(pdev, 0);
  408. if (IS_ERR(priv->base))
  409. return PTR_ERR(priv->base);
  410. priv->irq = platform_get_irq(pdev, 0);
  411. if (priv->irq < 0)
  412. return priv->irq;
  413. dcfg = of_device_get_match_data(dev);
  414. if (!dcfg)
  415. return -EINVAL;
  416. priv->dcfg = dcfg;
  417. priv->clk = devm_clk_get(dev, NULL);
  418. if (IS_ERR(priv->clk)) {
  419. if (PTR_ERR(priv->clk) != -ENOENT)
  420. return PTR_ERR(priv->clk);
  421. priv->clk = NULL;
  422. }
  423. ret = clk_prepare_enable(priv->clk);
  424. if (ret) {
  425. dev_err(dev, "Failed to enable clock\n");
  426. return ret;
  427. }
  428. priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
  429. priv->dcfg->init(priv);
  430. spin_lock_init(&priv->xcr_lock);
  431. priv->mbox.dev = dev;
  432. priv->mbox.ops = &imx_mu_ops;
  433. priv->mbox.chans = priv->mbox_chans;
  434. priv->mbox.txdone_irq = true;
  435. platform_set_drvdata(pdev, priv);
  436. ret = devm_mbox_controller_register(dev, &priv->mbox);
  437. if (ret) {
  438. clk_disable_unprepare(priv->clk);
  439. return ret;
  440. }
  441. pm_runtime_enable(dev);
  442. ret = pm_runtime_get_sync(dev);
  443. if (ret < 0) {
  444. pm_runtime_put_noidle(dev);
  445. goto disable_runtime_pm;
  446. }
  447. ret = pm_runtime_put_sync(dev);
  448. if (ret < 0)
  449. goto disable_runtime_pm;
  450. clk_disable_unprepare(priv->clk);
  451. priv->suspend = false;
  452. return 0;
  453. disable_runtime_pm:
  454. pm_runtime_disable(dev);
  455. clk_disable_unprepare(priv->clk);
  456. return ret;
  457. }
  458. static int imx_mu_remove(struct platform_device *pdev)
  459. {
  460. struct imx_mu_priv *priv = platform_get_drvdata(pdev);
  461. pm_runtime_disable(priv->dev);
  462. return 0;
  463. }
  464. static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
  465. .tx = imx_mu_generic_tx,
  466. .rx = imx_mu_generic_rx,
  467. .init = imx_mu_init_generic,
  468. .xTR = {0x0, 0x4, 0x8, 0xc},
  469. .xRR = {0x10, 0x14, 0x18, 0x1c},
  470. .xSR = 0x20,
  471. .xCR = 0x24,
  472. };
  473. static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
  474. .tx = imx_mu_generic_tx,
  475. .rx = imx_mu_generic_rx,
  476. .init = imx_mu_init_generic,
  477. .xTR = {0x20, 0x24, 0x28, 0x2c},
  478. .xRR = {0x40, 0x44, 0x48, 0x4c},
  479. .xSR = 0x60,
  480. .xCR = 0x64,
  481. };
  482. static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
  483. .tx = imx_mu_scu_tx,
  484. .rx = imx_mu_scu_rx,
  485. .init = imx_mu_init_scu,
  486. .xTR = {0x0, 0x4, 0x8, 0xc},
  487. .xRR = {0x10, 0x14, 0x18, 0x1c},
  488. .xSR = 0x20,
  489. .xCR = 0x24,
  490. };
  491. static const struct of_device_id imx_mu_dt_ids[] = {
  492. { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
  493. { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
  494. { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
  495. { },
  496. };
  497. MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
  498. static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
  499. {
  500. struct imx_mu_priv *priv = dev_get_drvdata(dev);
  501. if (!priv->clk)
  502. priv->xcr = imx_mu_read(priv, priv->dcfg->xCR);
  503. return 0;
  504. }
  505. static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
  506. {
  507. struct imx_mu_priv *priv = dev_get_drvdata(dev);
  508. /*
  509. * ONLY restore MU when context lost, the TIE could
  510. * be set during noirq resume as there is MU data
  511. * communication going on, and restore the saved
  512. * value will overwrite the TIE and cause MU data
  513. * send failed, may lead to system freeze. This issue
  514. * is observed by testing freeze mode suspend.
  515. */
  516. if (!imx_mu_read(priv, priv->dcfg->xCR) && !priv->clk)
  517. imx_mu_write(priv, priv->xcr, priv->dcfg->xCR);
  518. return 0;
  519. }
  520. static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
  521. {
  522. struct imx_mu_priv *priv = dev_get_drvdata(dev);
  523. clk_disable_unprepare(priv->clk);
  524. return 0;
  525. }
  526. static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
  527. {
  528. struct imx_mu_priv *priv = dev_get_drvdata(dev);
  529. int ret;
  530. ret = clk_prepare_enable(priv->clk);
  531. if (ret)
  532. dev_err(dev, "failed to enable clock\n");
  533. return ret;
  534. }
  535. static const struct dev_pm_ops imx_mu_pm_ops = {
  536. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
  537. imx_mu_resume_noirq)
  538. SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
  539. imx_mu_runtime_resume, NULL)
  540. };
  541. static struct platform_driver imx_mu_driver = {
  542. .probe = imx_mu_probe,
  543. .remove = imx_mu_remove,
  544. .driver = {
  545. .name = "imx_mu",
  546. .of_match_table = imx_mu_dt_ids,
  547. .pm = &imx_mu_pm_ops,
  548. },
  549. };
  550. module_platform_driver(imx_mu_driver);
  551. MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
  552. MODULE_DESCRIPTION("Message Unit driver for i.MX");
  553. MODULE_LICENSE("GPL v2");