qcom-irq-combiner.c 7.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  3. */
  4. /*
  5. * Driver for interrupt combiners in the Top-level Control and Status
  6. * Registers (TCSR) hardware block in Qualcomm Technologies chips.
  7. * An interrupt combiner in this block combines a set of interrupts by
  8. * OR'ing the individual interrupt signals into a summary interrupt
  9. * signal routed to a parent interrupt controller, and provides read-
  10. * only, 32-bit registers to query the status of individual interrupts.
  11. * The status bit for IRQ n is bit (n % 32) within register (n / 32)
  12. * of the given combiner. Thus, each combiner can be described as a set
  13. * of register offsets and the number of IRQs managed.
  14. */
  15. #define pr_fmt(fmt) "QCOM80B1:" fmt
  16. #include <linux/acpi.h>
  17. #include <linux/irqchip/chained_irq.h>
  18. #include <linux/irqdomain.h>
  19. #include <linux/platform_device.h>
  20. #define REG_SIZE 32
  21. struct combiner_reg {
  22. void __iomem *addr;
  23. unsigned long enabled;
  24. };
  25. struct combiner {
  26. struct irq_domain *domain;
  27. int parent_irq;
  28. u32 nirqs;
  29. u32 nregs;
  30. struct combiner_reg regs[];
  31. };
  32. static inline int irq_nr(u32 reg, u32 bit)
  33. {
  34. return reg * REG_SIZE + bit;
  35. }
  36. /*
  37. * Handler for the cascaded IRQ.
  38. */
  39. static void combiner_handle_irq(struct irq_desc *desc)
  40. {
  41. struct combiner *combiner = irq_desc_get_handler_data(desc);
  42. struct irq_chip *chip = irq_desc_get_chip(desc);
  43. u32 reg;
  44. chained_irq_enter(chip, desc);
  45. for (reg = 0; reg < combiner->nregs; reg++) {
  46. int virq;
  47. int hwirq;
  48. u32 bit;
  49. u32 status;
  50. bit = readl_relaxed(combiner->regs[reg].addr);
  51. status = bit & combiner->regs[reg].enabled;
  52. if (bit && !status)
  53. pr_warn_ratelimited("Unexpected IRQ on CPU%d: (%08x %08lx %p)\n",
  54. smp_processor_id(), bit,
  55. combiner->regs[reg].enabled,
  56. combiner->regs[reg].addr);
  57. while (status) {
  58. bit = __ffs(status);
  59. status &= ~(1 << bit);
  60. hwirq = irq_nr(reg, bit);
  61. virq = irq_find_mapping(combiner->domain, hwirq);
  62. if (virq > 0)
  63. generic_handle_irq(virq);
  64. }
  65. }
  66. chained_irq_exit(chip, desc);
  67. }
  68. static void combiner_irq_chip_mask_irq(struct irq_data *data)
  69. {
  70. struct combiner *combiner = irq_data_get_irq_chip_data(data);
  71. struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
  72. clear_bit(data->hwirq % REG_SIZE, &reg->enabled);
  73. }
  74. static void combiner_irq_chip_unmask_irq(struct irq_data *data)
  75. {
  76. struct combiner *combiner = irq_data_get_irq_chip_data(data);
  77. struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
  78. set_bit(data->hwirq % REG_SIZE, &reg->enabled);
  79. }
  80. static struct irq_chip irq_chip = {
  81. .irq_mask = combiner_irq_chip_mask_irq,
  82. .irq_unmask = combiner_irq_chip_unmask_irq,
  83. .name = "qcom-irq-combiner"
  84. };
  85. static int combiner_irq_map(struct irq_domain *domain, unsigned int irq,
  86. irq_hw_number_t hwirq)
  87. {
  88. irq_set_chip_and_handler(irq, &irq_chip, handle_level_irq);
  89. irq_set_chip_data(irq, domain->host_data);
  90. irq_set_noprobe(irq);
  91. return 0;
  92. }
  93. static void combiner_irq_unmap(struct irq_domain *domain, unsigned int irq)
  94. {
  95. irq_domain_reset_irq_data(irq_get_irq_data(irq));
  96. }
  97. static int combiner_irq_translate(struct irq_domain *d, struct irq_fwspec *fws,
  98. unsigned long *hwirq, unsigned int *type)
  99. {
  100. struct combiner *combiner = d->host_data;
  101. if (is_acpi_node(fws->fwnode)) {
  102. if (WARN_ON((fws->param_count != 2) ||
  103. (fws->param[0] >= combiner->nirqs) ||
  104. (fws->param[1] & IORESOURCE_IRQ_LOWEDGE) ||
  105. (fws->param[1] & IORESOURCE_IRQ_HIGHEDGE)))
  106. return -EINVAL;
  107. *hwirq = fws->param[0];
  108. *type = fws->param[1];
  109. return 0;
  110. }
  111. return -EINVAL;
  112. }
  113. static const struct irq_domain_ops domain_ops = {
  114. .map = combiner_irq_map,
  115. .unmap = combiner_irq_unmap,
  116. .translate = combiner_irq_translate
  117. };
  118. static acpi_status count_registers_cb(struct acpi_resource *ares, void *context)
  119. {
  120. int *count = context;
  121. if (ares->type == ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
  122. ++(*count);
  123. return AE_OK;
  124. }
  125. static int count_registers(struct platform_device *pdev)
  126. {
  127. acpi_handle ahandle = ACPI_HANDLE(&pdev->dev);
  128. acpi_status status;
  129. int count = 0;
  130. if (!acpi_has_method(ahandle, METHOD_NAME__CRS))
  131. return -EINVAL;
  132. status = acpi_walk_resources(ahandle, METHOD_NAME__CRS,
  133. count_registers_cb, &count);
  134. if (ACPI_FAILURE(status))
  135. return -EINVAL;
  136. return count;
  137. }
  138. struct get_registers_context {
  139. struct device *dev;
  140. struct combiner *combiner;
  141. int err;
  142. };
  143. static acpi_status get_registers_cb(struct acpi_resource *ares, void *context)
  144. {
  145. struct get_registers_context *ctx = context;
  146. struct acpi_resource_generic_register *reg;
  147. phys_addr_t paddr;
  148. void __iomem *vaddr;
  149. if (ares->type != ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
  150. return AE_OK;
  151. reg = &ares->data.generic_reg;
  152. paddr = reg->address;
  153. if ((reg->space_id != ACPI_SPACE_MEM) ||
  154. (reg->bit_offset != 0) ||
  155. (reg->bit_width > REG_SIZE)) {
  156. dev_err(ctx->dev, "Bad register resource @%pa\n", &paddr);
  157. ctx->err = -EINVAL;
  158. return AE_ERROR;
  159. }
  160. vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE);
  161. if (!vaddr) {
  162. dev_err(ctx->dev, "Can't map register @%pa\n", &paddr);
  163. ctx->err = -ENOMEM;
  164. return AE_ERROR;
  165. }
  166. ctx->combiner->regs[ctx->combiner->nregs].addr = vaddr;
  167. ctx->combiner->nirqs += reg->bit_width;
  168. ctx->combiner->nregs++;
  169. return AE_OK;
  170. }
  171. static int get_registers(struct platform_device *pdev, struct combiner *comb)
  172. {
  173. acpi_handle ahandle = ACPI_HANDLE(&pdev->dev);
  174. acpi_status status;
  175. struct get_registers_context ctx;
  176. if (!acpi_has_method(ahandle, METHOD_NAME__CRS))
  177. return -EINVAL;
  178. ctx.dev = &pdev->dev;
  179. ctx.combiner = comb;
  180. ctx.err = 0;
  181. status = acpi_walk_resources(ahandle, METHOD_NAME__CRS,
  182. get_registers_cb, &ctx);
  183. if (ACPI_FAILURE(status))
  184. return ctx.err;
  185. return 0;
  186. }
  187. static int __init combiner_probe(struct platform_device *pdev)
  188. {
  189. struct combiner *combiner;
  190. int nregs;
  191. int err;
  192. nregs = count_registers(pdev);
  193. if (nregs <= 0) {
  194. dev_err(&pdev->dev, "Error reading register resources\n");
  195. return -EINVAL;
  196. }
  197. combiner = devm_kzalloc(&pdev->dev, struct_size(combiner, regs, nregs),
  198. GFP_KERNEL);
  199. if (!combiner)
  200. return -ENOMEM;
  201. err = get_registers(pdev, combiner);
  202. if (err < 0)
  203. return err;
  204. combiner->parent_irq = platform_get_irq(pdev, 0);
  205. if (combiner->parent_irq <= 0)
  206. return -EPROBE_DEFER;
  207. combiner->domain = irq_domain_create_linear(pdev->dev.fwnode, combiner->nirqs,
  208. &domain_ops, combiner);
  209. if (!combiner->domain)
  210. /* Errors printed by irq_domain_create_linear */
  211. return -ENODEV;
  212. irq_set_chained_handler_and_data(combiner->parent_irq,
  213. combiner_handle_irq, combiner);
  214. dev_info(&pdev->dev, "Initialized with [p=%d,n=%d,r=%p]\n",
  215. combiner->parent_irq, combiner->nirqs, combiner->regs[0].addr);
  216. return 0;
  217. }
  218. static const struct acpi_device_id qcom_irq_combiner_ids[] = {
  219. { "QCOM80B1", },
  220. { }
  221. };
  222. static struct platform_driver qcom_irq_combiner_probe = {
  223. .driver = {
  224. .name = "qcom-irq-combiner",
  225. .acpi_match_table = ACPI_PTR(qcom_irq_combiner_ids),
  226. },
  227. .probe = combiner_probe,
  228. };
  229. builtin_platform_driver(qcom_irq_combiner_probe);