irq-zevio.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/drivers/irqchip/irq-zevio.c
  4. *
  5. * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
  6. */
  7. #include <linux/io.h>
  8. #include <linux/irq.h>
  9. #include <linux/irqchip.h>
  10. #include <linux/of.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_irq.h>
  13. #include <asm/mach/irq.h>
  14. #include <asm/exception.h>
  15. #define IO_STATUS 0x000
  16. #define IO_RAW_STATUS 0x004
  17. #define IO_ENABLE 0x008
  18. #define IO_DISABLE 0x00C
  19. #define IO_CURRENT 0x020
  20. #define IO_RESET 0x028
  21. #define IO_MAX_PRIOTY 0x02C
  22. #define IO_IRQ_BASE 0x000
  23. #define IO_FIQ_BASE 0x100
  24. #define IO_INVERT_SEL 0x200
  25. #define IO_STICKY_SEL 0x204
  26. #define IO_PRIORITY_SEL 0x300
  27. #define MAX_INTRS 32
  28. #define FIQ_START MAX_INTRS
  29. static struct irq_domain *zevio_irq_domain;
  30. static void __iomem *zevio_irq_io;
  31. static void zevio_irq_ack(struct irq_data *irqd)
  32. {
  33. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(irqd);
  34. struct irq_chip_regs *regs = &irq_data_get_chip_type(irqd)->regs;
  35. readl(gc->reg_base + regs->ack);
  36. }
  37. static void __exception_irq_entry zevio_handle_irq(struct pt_regs *regs)
  38. {
  39. int irqnr;
  40. while (readl(zevio_irq_io + IO_STATUS)) {
  41. irqnr = readl(zevio_irq_io + IO_CURRENT);
  42. handle_domain_irq(zevio_irq_domain, irqnr, regs);
  43. }
  44. }
  45. static void __init zevio_init_irq_base(void __iomem *base)
  46. {
  47. /* Disable all interrupts */
  48. writel(~0, base + IO_DISABLE);
  49. /* Accept interrupts of all priorities */
  50. writel(0xF, base + IO_MAX_PRIOTY);
  51. /* Reset existing interrupts */
  52. readl(base + IO_RESET);
  53. }
  54. static int __init zevio_of_init(struct device_node *node,
  55. struct device_node *parent)
  56. {
  57. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  58. struct irq_chip_generic *gc;
  59. int ret;
  60. if (WARN_ON(zevio_irq_io || zevio_irq_domain))
  61. return -EBUSY;
  62. zevio_irq_io = of_iomap(node, 0);
  63. BUG_ON(!zevio_irq_io);
  64. /* Do not invert interrupt status bits */
  65. writel(~0, zevio_irq_io + IO_INVERT_SEL);
  66. /* Disable sticky interrupts */
  67. writel(0, zevio_irq_io + IO_STICKY_SEL);
  68. /* We don't use IRQ priorities. Set each IRQ to highest priority. */
  69. memset_io(zevio_irq_io + IO_PRIORITY_SEL, 0, MAX_INTRS * sizeof(u32));
  70. /* Init IRQ and FIQ */
  71. zevio_init_irq_base(zevio_irq_io + IO_IRQ_BASE);
  72. zevio_init_irq_base(zevio_irq_io + IO_FIQ_BASE);
  73. zevio_irq_domain = irq_domain_add_linear(node, MAX_INTRS,
  74. &irq_generic_chip_ops, NULL);
  75. BUG_ON(!zevio_irq_domain);
  76. ret = irq_alloc_domain_generic_chips(zevio_irq_domain, MAX_INTRS, 1,
  77. "zevio_intc", handle_level_irq,
  78. clr, 0, IRQ_GC_INIT_MASK_CACHE);
  79. BUG_ON(ret);
  80. gc = irq_get_domain_generic_chip(zevio_irq_domain, 0);
  81. gc->reg_base = zevio_irq_io;
  82. gc->chip_types[0].chip.irq_ack = zevio_irq_ack;
  83. gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
  84. gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
  85. gc->chip_types[0].regs.mask = IO_IRQ_BASE + IO_ENABLE;
  86. gc->chip_types[0].regs.enable = IO_IRQ_BASE + IO_ENABLE;
  87. gc->chip_types[0].regs.disable = IO_IRQ_BASE + IO_DISABLE;
  88. gc->chip_types[0].regs.ack = IO_IRQ_BASE + IO_RESET;
  89. set_handle_irq(zevio_handle_irq);
  90. pr_info("TI-NSPIRE classic IRQ controller\n");
  91. return 0;
  92. }
  93. IRQCHIP_DECLARE(zevio_irq, "lsi,zevio-intc", zevio_of_init);