irq-xtensa-pic.c 2.7 KB

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  1. /*
  2. * Xtensa built-in interrupt controller
  3. *
  4. * Copyright (C) 2002 - 2013 Tensilica, Inc.
  5. * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. *
  11. * Chris Zankel <chris@zankel.net>
  12. * Kevin Chea
  13. */
  14. #include <linux/interrupt.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/irq.h>
  17. #include <linux/irqchip.h>
  18. #include <linux/of.h>
  19. unsigned int cached_irq_mask;
  20. /*
  21. * Device Tree IRQ specifier translation function which works with one or
  22. * two cell bindings. First cell value maps directly to the hwirq number.
  23. * Second cell if present specifies whether hwirq number is external (1) or
  24. * internal (0).
  25. */
  26. static int xtensa_pic_irq_domain_xlate(struct irq_domain *d,
  27. struct device_node *ctrlr,
  28. const u32 *intspec, unsigned int intsize,
  29. unsigned long *out_hwirq, unsigned int *out_type)
  30. {
  31. return xtensa_irq_domain_xlate(intspec, intsize,
  32. intspec[0], intspec[0],
  33. out_hwirq, out_type);
  34. }
  35. static const struct irq_domain_ops xtensa_irq_domain_ops = {
  36. .xlate = xtensa_pic_irq_domain_xlate,
  37. .map = xtensa_irq_map,
  38. };
  39. static void xtensa_irq_mask(struct irq_data *d)
  40. {
  41. cached_irq_mask &= ~(1 << d->hwirq);
  42. xtensa_set_sr(cached_irq_mask, intenable);
  43. }
  44. static void xtensa_irq_unmask(struct irq_data *d)
  45. {
  46. cached_irq_mask |= 1 << d->hwirq;
  47. xtensa_set_sr(cached_irq_mask, intenable);
  48. }
  49. static void xtensa_irq_enable(struct irq_data *d)
  50. {
  51. xtensa_irq_unmask(d);
  52. }
  53. static void xtensa_irq_disable(struct irq_data *d)
  54. {
  55. xtensa_irq_mask(d);
  56. }
  57. static void xtensa_irq_ack(struct irq_data *d)
  58. {
  59. xtensa_set_sr(1 << d->hwirq, intclear);
  60. }
  61. static int xtensa_irq_retrigger(struct irq_data *d)
  62. {
  63. unsigned int mask = 1u << d->hwirq;
  64. if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
  65. return 0;
  66. xtensa_set_sr(mask, intset);
  67. return 1;
  68. }
  69. static struct irq_chip xtensa_irq_chip = {
  70. .name = "xtensa",
  71. .irq_enable = xtensa_irq_enable,
  72. .irq_disable = xtensa_irq_disable,
  73. .irq_mask = xtensa_irq_mask,
  74. .irq_unmask = xtensa_irq_unmask,
  75. .irq_ack = xtensa_irq_ack,
  76. .irq_retrigger = xtensa_irq_retrigger,
  77. };
  78. int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
  79. {
  80. struct irq_domain *root_domain =
  81. irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
  82. &xtensa_irq_domain_ops, &xtensa_irq_chip);
  83. irq_set_default_host(root_domain);
  84. return 0;
  85. }
  86. static int __init xtensa_pic_init(struct device_node *np,
  87. struct device_node *interrupt_parent)
  88. {
  89. struct irq_domain *root_domain =
  90. irq_domain_add_linear(np, NR_IRQS, &xtensa_irq_domain_ops,
  91. &xtensa_irq_chip);
  92. irq_set_default_host(root_domain);
  93. return 0;
  94. }
  95. IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init);