irq-xtensa-mx.c 4.5 KB

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  1. /*
  2. * Xtensa MX interrupt distributor
  3. *
  4. * Copyright (C) 2002 - 2013 Tensilica, Inc.
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/interrupt.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/irq.h>
  13. #include <linux/irqchip.h>
  14. #include <linux/of.h>
  15. #include <asm/mxregs.h>
  16. #define HW_IRQ_IPI_COUNT 2
  17. #define HW_IRQ_MX_BASE 2
  18. #define HW_IRQ_EXTERN_BASE 3
  19. static DEFINE_PER_CPU(unsigned int, cached_irq_mask);
  20. static int xtensa_mx_irq_map(struct irq_domain *d, unsigned int irq,
  21. irq_hw_number_t hw)
  22. {
  23. if (hw < HW_IRQ_IPI_COUNT) {
  24. struct irq_chip *irq_chip = d->host_data;
  25. irq_set_chip_and_handler_name(irq, irq_chip,
  26. handle_percpu_irq, "ipi");
  27. irq_set_status_flags(irq, IRQ_LEVEL);
  28. return 0;
  29. }
  30. irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
  31. return xtensa_irq_map(d, irq, hw);
  32. }
  33. /*
  34. * Device Tree IRQ specifier translation function which works with one or
  35. * two cell bindings. First cell value maps directly to the hwirq number.
  36. * Second cell if present specifies whether hwirq number is external (1) or
  37. * internal (0).
  38. */
  39. static int xtensa_mx_irq_domain_xlate(struct irq_domain *d,
  40. struct device_node *ctrlr,
  41. const u32 *intspec, unsigned int intsize,
  42. unsigned long *out_hwirq, unsigned int *out_type)
  43. {
  44. return xtensa_irq_domain_xlate(intspec, intsize,
  45. intspec[0], intspec[0] + HW_IRQ_EXTERN_BASE,
  46. out_hwirq, out_type);
  47. }
  48. static const struct irq_domain_ops xtensa_mx_irq_domain_ops = {
  49. .xlate = xtensa_mx_irq_domain_xlate,
  50. .map = xtensa_mx_irq_map,
  51. };
  52. void secondary_init_irq(void)
  53. {
  54. __this_cpu_write(cached_irq_mask,
  55. XCHAL_INTTYPE_MASK_EXTERN_EDGE |
  56. XCHAL_INTTYPE_MASK_EXTERN_LEVEL);
  57. xtensa_set_sr(XCHAL_INTTYPE_MASK_EXTERN_EDGE |
  58. XCHAL_INTTYPE_MASK_EXTERN_LEVEL, intenable);
  59. }
  60. static void xtensa_mx_irq_mask(struct irq_data *d)
  61. {
  62. unsigned int mask = 1u << d->hwirq;
  63. if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
  64. XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
  65. unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
  66. if (ext_irq >= HW_IRQ_MX_BASE) {
  67. set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENG);
  68. return;
  69. }
  70. }
  71. mask = __this_cpu_read(cached_irq_mask) & ~mask;
  72. __this_cpu_write(cached_irq_mask, mask);
  73. xtensa_set_sr(mask, intenable);
  74. }
  75. static void xtensa_mx_irq_unmask(struct irq_data *d)
  76. {
  77. unsigned int mask = 1u << d->hwirq;
  78. if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
  79. XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
  80. unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
  81. if (ext_irq >= HW_IRQ_MX_BASE) {
  82. set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENGSET);
  83. return;
  84. }
  85. }
  86. mask |= __this_cpu_read(cached_irq_mask);
  87. __this_cpu_write(cached_irq_mask, mask);
  88. xtensa_set_sr(mask, intenable);
  89. }
  90. static void xtensa_mx_irq_enable(struct irq_data *d)
  91. {
  92. xtensa_mx_irq_unmask(d);
  93. }
  94. static void xtensa_mx_irq_disable(struct irq_data *d)
  95. {
  96. xtensa_mx_irq_mask(d);
  97. }
  98. static void xtensa_mx_irq_ack(struct irq_data *d)
  99. {
  100. xtensa_set_sr(1 << d->hwirq, intclear);
  101. }
  102. static int xtensa_mx_irq_retrigger(struct irq_data *d)
  103. {
  104. unsigned int mask = 1u << d->hwirq;
  105. if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
  106. return 0;
  107. xtensa_set_sr(mask, intset);
  108. return 1;
  109. }
  110. static int xtensa_mx_irq_set_affinity(struct irq_data *d,
  111. const struct cpumask *dest, bool force)
  112. {
  113. int cpu = cpumask_any_and(dest, cpu_online_mask);
  114. unsigned mask = 1u << cpu;
  115. set_er(mask, MIROUT(d->hwirq - HW_IRQ_MX_BASE));
  116. irq_data_update_effective_affinity(d, cpumask_of(cpu));
  117. return 0;
  118. }
  119. static struct irq_chip xtensa_mx_irq_chip = {
  120. .name = "xtensa-mx",
  121. .irq_enable = xtensa_mx_irq_enable,
  122. .irq_disable = xtensa_mx_irq_disable,
  123. .irq_mask = xtensa_mx_irq_mask,
  124. .irq_unmask = xtensa_mx_irq_unmask,
  125. .irq_ack = xtensa_mx_irq_ack,
  126. .irq_retrigger = xtensa_mx_irq_retrigger,
  127. .irq_set_affinity = xtensa_mx_irq_set_affinity,
  128. };
  129. int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent)
  130. {
  131. struct irq_domain *root_domain =
  132. irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
  133. &xtensa_mx_irq_domain_ops,
  134. &xtensa_mx_irq_chip);
  135. irq_set_default_host(root_domain);
  136. secondary_init_irq();
  137. return 0;
  138. }
  139. static int __init xtensa_mx_init(struct device_node *np,
  140. struct device_node *interrupt_parent)
  141. {
  142. struct irq_domain *root_domain =
  143. irq_domain_add_linear(np, NR_IRQS, &xtensa_mx_irq_domain_ops,
  144. &xtensa_mx_irq_chip);
  145. irq_set_default_host(root_domain);
  146. secondary_init_irq();
  147. return 0;
  148. }
  149. IRQCHIP_DECLARE(xtensa_mx_irq_chip, "cdns,xtensa-mx", xtensa_mx_init);