irq-vf610-mscm-ir.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2014-2015 Toradex AG
  4. * Author: Stefan Agner <stefan@agner.ch>
  5. *
  6. * IRQ chip driver for MSCM interrupt router available on Vybrid SoC's.
  7. * The interrupt router is between the CPU's interrupt controller and the
  8. * peripheral. The router allows to route the peripheral interrupts to
  9. * one of the two available CPU's on Vybrid VF6xx SoC's (Cortex-A5 or
  10. * Cortex-M4). The router will be configured transparently on a IRQ
  11. * request.
  12. *
  13. * o All peripheral interrupts of the Vybrid SoC can be routed to
  14. * CPU 0, CPU 1 or both. The routing is useful for dual-core
  15. * variants of Vybrid SoC such as VF6xx. This driver routes the
  16. * requested interrupt to the CPU currently running on.
  17. *
  18. * o It is required to setup the interrupt router even on single-core
  19. * variants of Vybrid.
  20. */
  21. #include <linux/cpu_pm.h>
  22. #include <linux/io.h>
  23. #include <linux/irq.h>
  24. #include <linux/irqchip.h>
  25. #include <linux/irqdomain.h>
  26. #include <linux/mfd/syscon.h>
  27. #include <dt-bindings/interrupt-controller/arm-gic.h>
  28. #include <linux/of.h>
  29. #include <linux/of_address.h>
  30. #include <linux/slab.h>
  31. #include <linux/regmap.h>
  32. #define MSCM_CPxNUM 0x4
  33. #define MSCM_IRSPRC(n) (0x80 + 2 * (n))
  34. #define MSCM_IRSPRC_CPEN_MASK 0x3
  35. #define MSCM_IRSPRC_NUM 112
  36. struct vf610_mscm_ir_chip_data {
  37. void __iomem *mscm_ir_base;
  38. u16 cpu_mask;
  39. u16 saved_irsprc[MSCM_IRSPRC_NUM];
  40. bool is_nvic;
  41. };
  42. static struct vf610_mscm_ir_chip_data *mscm_ir_data;
  43. static inline void vf610_mscm_ir_save(struct vf610_mscm_ir_chip_data *data)
  44. {
  45. int i;
  46. for (i = 0; i < MSCM_IRSPRC_NUM; i++)
  47. data->saved_irsprc[i] = readw_relaxed(data->mscm_ir_base + MSCM_IRSPRC(i));
  48. }
  49. static inline void vf610_mscm_ir_restore(struct vf610_mscm_ir_chip_data *data)
  50. {
  51. int i;
  52. for (i = 0; i < MSCM_IRSPRC_NUM; i++)
  53. writew_relaxed(data->saved_irsprc[i], data->mscm_ir_base + MSCM_IRSPRC(i));
  54. }
  55. static int vf610_mscm_ir_notifier(struct notifier_block *self,
  56. unsigned long cmd, void *v)
  57. {
  58. switch (cmd) {
  59. case CPU_CLUSTER_PM_ENTER:
  60. vf610_mscm_ir_save(mscm_ir_data);
  61. break;
  62. case CPU_CLUSTER_PM_ENTER_FAILED:
  63. case CPU_CLUSTER_PM_EXIT:
  64. vf610_mscm_ir_restore(mscm_ir_data);
  65. break;
  66. }
  67. return NOTIFY_OK;
  68. }
  69. static struct notifier_block mscm_ir_notifier_block = {
  70. .notifier_call = vf610_mscm_ir_notifier,
  71. };
  72. static void vf610_mscm_ir_enable(struct irq_data *data)
  73. {
  74. irq_hw_number_t hwirq = data->hwirq;
  75. struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
  76. u16 irsprc;
  77. irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
  78. irsprc &= MSCM_IRSPRC_CPEN_MASK;
  79. WARN_ON(irsprc & ~chip_data->cpu_mask);
  80. writew_relaxed(chip_data->cpu_mask,
  81. chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
  82. irq_chip_enable_parent(data);
  83. }
  84. static void vf610_mscm_ir_disable(struct irq_data *data)
  85. {
  86. irq_hw_number_t hwirq = data->hwirq;
  87. struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
  88. writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
  89. irq_chip_disable_parent(data);
  90. }
  91. static struct irq_chip vf610_mscm_ir_irq_chip = {
  92. .name = "mscm-ir",
  93. .irq_mask = irq_chip_mask_parent,
  94. .irq_unmask = irq_chip_unmask_parent,
  95. .irq_eoi = irq_chip_eoi_parent,
  96. .irq_enable = vf610_mscm_ir_enable,
  97. .irq_disable = vf610_mscm_ir_disable,
  98. .irq_retrigger = irq_chip_retrigger_hierarchy,
  99. .irq_set_affinity = irq_chip_set_affinity_parent,
  100. };
  101. static int vf610_mscm_ir_domain_alloc(struct irq_domain *domain, unsigned int virq,
  102. unsigned int nr_irqs, void *arg)
  103. {
  104. int i;
  105. irq_hw_number_t hwirq;
  106. struct irq_fwspec *fwspec = arg;
  107. struct irq_fwspec parent_fwspec;
  108. if (!irq_domain_get_of_node(domain->parent))
  109. return -EINVAL;
  110. if (fwspec->param_count != 2)
  111. return -EINVAL;
  112. hwirq = fwspec->param[0];
  113. for (i = 0; i < nr_irqs; i++)
  114. irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
  115. &vf610_mscm_ir_irq_chip,
  116. domain->host_data);
  117. parent_fwspec.fwnode = domain->parent->fwnode;
  118. if (mscm_ir_data->is_nvic) {
  119. parent_fwspec.param_count = 1;
  120. parent_fwspec.param[0] = fwspec->param[0];
  121. } else {
  122. parent_fwspec.param_count = 3;
  123. parent_fwspec.param[0] = GIC_SPI;
  124. parent_fwspec.param[1] = fwspec->param[0];
  125. parent_fwspec.param[2] = fwspec->param[1];
  126. }
  127. return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
  128. &parent_fwspec);
  129. }
  130. static int vf610_mscm_ir_domain_translate(struct irq_domain *d,
  131. struct irq_fwspec *fwspec,
  132. unsigned long *hwirq,
  133. unsigned int *type)
  134. {
  135. if (WARN_ON(fwspec->param_count < 2))
  136. return -EINVAL;
  137. *hwirq = fwspec->param[0];
  138. *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
  139. return 0;
  140. }
  141. static const struct irq_domain_ops mscm_irq_domain_ops = {
  142. .translate = vf610_mscm_ir_domain_translate,
  143. .alloc = vf610_mscm_ir_domain_alloc,
  144. .free = irq_domain_free_irqs_common,
  145. };
  146. static int __init vf610_mscm_ir_of_init(struct device_node *node,
  147. struct device_node *parent)
  148. {
  149. struct irq_domain *domain, *domain_parent;
  150. struct regmap *mscm_cp_regmap;
  151. int ret, cpuid;
  152. domain_parent = irq_find_host(parent);
  153. if (!domain_parent) {
  154. pr_err("vf610_mscm_ir: interrupt-parent not found\n");
  155. return -EINVAL;
  156. }
  157. mscm_ir_data = kzalloc(sizeof(*mscm_ir_data), GFP_KERNEL);
  158. if (!mscm_ir_data)
  159. return -ENOMEM;
  160. mscm_ir_data->mscm_ir_base = of_io_request_and_map(node, 0, "mscm-ir");
  161. if (IS_ERR(mscm_ir_data->mscm_ir_base)) {
  162. pr_err("vf610_mscm_ir: unable to map mscm register\n");
  163. ret = PTR_ERR(mscm_ir_data->mscm_ir_base);
  164. goto out_free;
  165. }
  166. mscm_cp_regmap = syscon_regmap_lookup_by_phandle(node, "fsl,cpucfg");
  167. if (IS_ERR(mscm_cp_regmap)) {
  168. ret = PTR_ERR(mscm_cp_regmap);
  169. pr_err("vf610_mscm_ir: regmap lookup for cpucfg failed\n");
  170. goto out_unmap;
  171. }
  172. regmap_read(mscm_cp_regmap, MSCM_CPxNUM, &cpuid);
  173. mscm_ir_data->cpu_mask = 0x1 << cpuid;
  174. domain = irq_domain_add_hierarchy(domain_parent, 0,
  175. MSCM_IRSPRC_NUM, node,
  176. &mscm_irq_domain_ops, mscm_ir_data);
  177. if (!domain) {
  178. ret = -ENOMEM;
  179. goto out_unmap;
  180. }
  181. if (of_device_is_compatible(irq_domain_get_of_node(domain->parent),
  182. "arm,armv7m-nvic"))
  183. mscm_ir_data->is_nvic = true;
  184. cpu_pm_register_notifier(&mscm_ir_notifier_block);
  185. return 0;
  186. out_unmap:
  187. iounmap(mscm_ir_data->mscm_ir_base);
  188. out_free:
  189. kfree(mscm_ir_data);
  190. return ret;
  191. }
  192. IRQCHIP_DECLARE(vf610_mscm_ir, "fsl,vf610-mscm-ir", vf610_mscm_ir_of_init);