irq-tegra.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver code for Tegra's Legacy Interrupt Controller
  4. *
  5. * Author: Marc Zyngier <marc.zyngier@arm.com>
  6. *
  7. * Heavily based on the original arch/arm/mach-tegra/irq.c code:
  8. * Copyright (C) 2011 Google, Inc.
  9. *
  10. * Author:
  11. * Colin Cross <ccross@android.com>
  12. *
  13. * Copyright (C) 2010,2013, NVIDIA Corporation
  14. */
  15. #include <linux/io.h>
  16. #include <linux/irq.h>
  17. #include <linux/irqchip.h>
  18. #include <linux/irqdomain.h>
  19. #include <linux/of_address.h>
  20. #include <linux/slab.h>
  21. #include <linux/syscore_ops.h>
  22. #include <dt-bindings/interrupt-controller/arm-gic.h>
  23. #define ICTLR_CPU_IEP_VFIQ 0x08
  24. #define ICTLR_CPU_IEP_FIR 0x14
  25. #define ICTLR_CPU_IEP_FIR_SET 0x18
  26. #define ICTLR_CPU_IEP_FIR_CLR 0x1c
  27. #define ICTLR_CPU_IER 0x20
  28. #define ICTLR_CPU_IER_SET 0x24
  29. #define ICTLR_CPU_IER_CLR 0x28
  30. #define ICTLR_CPU_IEP_CLASS 0x2C
  31. #define ICTLR_COP_IER 0x30
  32. #define ICTLR_COP_IER_SET 0x34
  33. #define ICTLR_COP_IER_CLR 0x38
  34. #define ICTLR_COP_IEP_CLASS 0x3c
  35. #define TEGRA_MAX_NUM_ICTLRS 6
  36. static unsigned int num_ictlrs;
  37. struct tegra_ictlr_soc {
  38. unsigned int num_ictlrs;
  39. };
  40. static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
  41. .num_ictlrs = 4,
  42. };
  43. static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
  44. .num_ictlrs = 5,
  45. };
  46. static const struct tegra_ictlr_soc tegra210_ictlr_soc = {
  47. .num_ictlrs = 6,
  48. };
  49. static const struct of_device_id ictlr_matches[] = {
  50. { .compatible = "nvidia,tegra210-ictlr", .data = &tegra210_ictlr_soc },
  51. { .compatible = "nvidia,tegra30-ictlr", .data = &tegra30_ictlr_soc },
  52. { .compatible = "nvidia,tegra20-ictlr", .data = &tegra20_ictlr_soc },
  53. { }
  54. };
  55. struct tegra_ictlr_info {
  56. void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
  57. #ifdef CONFIG_PM_SLEEP
  58. u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
  59. u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
  60. u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
  61. u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
  62. u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
  63. #endif
  64. };
  65. static struct tegra_ictlr_info *lic;
  66. static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg)
  67. {
  68. void __iomem *base = (void __iomem __force *)d->chip_data;
  69. u32 mask;
  70. mask = BIT(d->hwirq % 32);
  71. writel_relaxed(mask, base + reg);
  72. }
  73. static void tegra_mask(struct irq_data *d)
  74. {
  75. tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
  76. irq_chip_mask_parent(d);
  77. }
  78. static void tegra_unmask(struct irq_data *d)
  79. {
  80. tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
  81. irq_chip_unmask_parent(d);
  82. }
  83. static void tegra_eoi(struct irq_data *d)
  84. {
  85. tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
  86. irq_chip_eoi_parent(d);
  87. }
  88. static int tegra_retrigger(struct irq_data *d)
  89. {
  90. tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
  91. return irq_chip_retrigger_hierarchy(d);
  92. }
  93. #ifdef CONFIG_PM_SLEEP
  94. static int tegra_set_wake(struct irq_data *d, unsigned int enable)
  95. {
  96. u32 irq = d->hwirq;
  97. u32 index, mask;
  98. index = (irq / 32);
  99. mask = BIT(irq % 32);
  100. if (enable)
  101. lic->ictlr_wake_mask[index] |= mask;
  102. else
  103. lic->ictlr_wake_mask[index] &= ~mask;
  104. /*
  105. * Do *not* call into the parent, as the GIC doesn't have any
  106. * wake-up facility...
  107. */
  108. return 0;
  109. }
  110. static int tegra_ictlr_suspend(void)
  111. {
  112. unsigned long flags;
  113. unsigned int i;
  114. local_irq_save(flags);
  115. for (i = 0; i < num_ictlrs; i++) {
  116. void __iomem *ictlr = lic->base[i];
  117. /* Save interrupt state */
  118. lic->cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
  119. lic->cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
  120. lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
  121. lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
  122. /* Disable COP interrupts */
  123. writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
  124. /* Disable CPU interrupts */
  125. writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
  126. /* Enable the wakeup sources of ictlr */
  127. writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
  128. }
  129. local_irq_restore(flags);
  130. return 0;
  131. }
  132. static void tegra_ictlr_resume(void)
  133. {
  134. unsigned long flags;
  135. unsigned int i;
  136. local_irq_save(flags);
  137. for (i = 0; i < num_ictlrs; i++) {
  138. void __iomem *ictlr = lic->base[i];
  139. writel_relaxed(lic->cpu_iep[i],
  140. ictlr + ICTLR_CPU_IEP_CLASS);
  141. writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
  142. writel_relaxed(lic->cpu_ier[i],
  143. ictlr + ICTLR_CPU_IER_SET);
  144. writel_relaxed(lic->cop_iep[i],
  145. ictlr + ICTLR_COP_IEP_CLASS);
  146. writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
  147. writel_relaxed(lic->cop_ier[i],
  148. ictlr + ICTLR_COP_IER_SET);
  149. }
  150. local_irq_restore(flags);
  151. }
  152. static struct syscore_ops tegra_ictlr_syscore_ops = {
  153. .suspend = tegra_ictlr_suspend,
  154. .resume = tegra_ictlr_resume,
  155. };
  156. static void tegra_ictlr_syscore_init(void)
  157. {
  158. register_syscore_ops(&tegra_ictlr_syscore_ops);
  159. }
  160. #else
  161. #define tegra_set_wake NULL
  162. static inline void tegra_ictlr_syscore_init(void) {}
  163. #endif
  164. static struct irq_chip tegra_ictlr_chip = {
  165. .name = "LIC",
  166. .irq_eoi = tegra_eoi,
  167. .irq_mask = tegra_mask,
  168. .irq_unmask = tegra_unmask,
  169. .irq_retrigger = tegra_retrigger,
  170. .irq_set_wake = tegra_set_wake,
  171. .irq_set_type = irq_chip_set_type_parent,
  172. .flags = IRQCHIP_MASK_ON_SUSPEND,
  173. #ifdef CONFIG_SMP
  174. .irq_set_affinity = irq_chip_set_affinity_parent,
  175. #endif
  176. };
  177. static int tegra_ictlr_domain_translate(struct irq_domain *d,
  178. struct irq_fwspec *fwspec,
  179. unsigned long *hwirq,
  180. unsigned int *type)
  181. {
  182. if (is_of_node(fwspec->fwnode)) {
  183. if (fwspec->param_count != 3)
  184. return -EINVAL;
  185. /* No PPI should point to this domain */
  186. if (fwspec->param[0] != 0)
  187. return -EINVAL;
  188. *hwirq = fwspec->param[1];
  189. *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
  190. return 0;
  191. }
  192. return -EINVAL;
  193. }
  194. static int tegra_ictlr_domain_alloc(struct irq_domain *domain,
  195. unsigned int virq,
  196. unsigned int nr_irqs, void *data)
  197. {
  198. struct irq_fwspec *fwspec = data;
  199. struct irq_fwspec parent_fwspec;
  200. struct tegra_ictlr_info *info = domain->host_data;
  201. irq_hw_number_t hwirq;
  202. unsigned int i;
  203. if (fwspec->param_count != 3)
  204. return -EINVAL; /* Not GIC compliant */
  205. if (fwspec->param[0] != GIC_SPI)
  206. return -EINVAL; /* No PPI should point to this domain */
  207. hwirq = fwspec->param[1];
  208. if (hwirq >= (num_ictlrs * 32))
  209. return -EINVAL;
  210. for (i = 0; i < nr_irqs; i++) {
  211. int ictlr = (hwirq + i) / 32;
  212. irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
  213. &tegra_ictlr_chip,
  214. (void __force *)info->base[ictlr]);
  215. }
  216. parent_fwspec = *fwspec;
  217. parent_fwspec.fwnode = domain->parent->fwnode;
  218. return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
  219. &parent_fwspec);
  220. }
  221. static const struct irq_domain_ops tegra_ictlr_domain_ops = {
  222. .translate = tegra_ictlr_domain_translate,
  223. .alloc = tegra_ictlr_domain_alloc,
  224. .free = irq_domain_free_irqs_common,
  225. };
  226. static int __init tegra_ictlr_init(struct device_node *node,
  227. struct device_node *parent)
  228. {
  229. struct irq_domain *parent_domain, *domain;
  230. const struct of_device_id *match;
  231. const struct tegra_ictlr_soc *soc;
  232. unsigned int i;
  233. int err;
  234. if (!parent) {
  235. pr_err("%pOF: no parent, giving up\n", node);
  236. return -ENODEV;
  237. }
  238. parent_domain = irq_find_host(parent);
  239. if (!parent_domain) {
  240. pr_err("%pOF: unable to obtain parent domain\n", node);
  241. return -ENXIO;
  242. }
  243. match = of_match_node(ictlr_matches, node);
  244. if (!match) /* Should never happen... */
  245. return -ENODEV;
  246. soc = match->data;
  247. lic = kzalloc(sizeof(*lic), GFP_KERNEL);
  248. if (!lic)
  249. return -ENOMEM;
  250. for (i = 0; i < TEGRA_MAX_NUM_ICTLRS; i++) {
  251. void __iomem *base;
  252. base = of_iomap(node, i);
  253. if (!base)
  254. break;
  255. lic->base[i] = base;
  256. /* Disable all interrupts */
  257. writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR);
  258. /* All interrupts target IRQ */
  259. writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);
  260. num_ictlrs++;
  261. }
  262. if (!num_ictlrs) {
  263. pr_err("%pOF: no valid regions, giving up\n", node);
  264. err = -ENOMEM;
  265. goto out_free;
  266. }
  267. WARN(num_ictlrs != soc->num_ictlrs,
  268. "%pOF: Found %u interrupt controllers in DT; expected %u.\n",
  269. node, num_ictlrs, soc->num_ictlrs);
  270. domain = irq_domain_add_hierarchy(parent_domain, 0, num_ictlrs * 32,
  271. node, &tegra_ictlr_domain_ops,
  272. lic);
  273. if (!domain) {
  274. pr_err("%pOF: failed to allocated domain\n", node);
  275. err = -ENOMEM;
  276. goto out_unmap;
  277. }
  278. tegra_ictlr_syscore_init();
  279. pr_info("%pOF: %d interrupts forwarded to %pOF\n",
  280. node, num_ictlrs * 32, parent);
  281. return 0;
  282. out_unmap:
  283. for (i = 0; i < num_ictlrs; i++)
  284. iounmap(lic->base[i]);
  285. out_free:
  286. kfree(lic);
  287. return err;
  288. }
  289. IRQCHIP_DECLARE(tegra20_ictlr, "nvidia,tegra20-ictlr", tegra_ictlr_init);
  290. IRQCHIP_DECLARE(tegra30_ictlr, "nvidia,tegra30-ictlr", tegra_ictlr_init);
  291. IRQCHIP_DECLARE(tegra210_ictlr, "nvidia,tegra210-ictlr", tegra_ictlr_init);