irq-tango.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2014 Mans Rullgard <mans@mansr.com>
  4. */
  5. #include <linux/init.h>
  6. #include <linux/irq.h>
  7. #include <linux/irqchip.h>
  8. #include <linux/irqchip/chained_irq.h>
  9. #include <linux/ioport.h>
  10. #include <linux/io.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/slab.h>
  14. #define IRQ0_CTL_BASE 0x0000
  15. #define IRQ1_CTL_BASE 0x0100
  16. #define EDGE_CTL_BASE 0x0200
  17. #define IRQ2_CTL_BASE 0x0300
  18. #define IRQ_CTL_HI 0x18
  19. #define EDGE_CTL_HI 0x20
  20. #define IRQ_STATUS 0x00
  21. #define IRQ_RAWSTAT 0x04
  22. #define IRQ_EN_SET 0x08
  23. #define IRQ_EN_CLR 0x0c
  24. #define IRQ_SOFT_SET 0x10
  25. #define IRQ_SOFT_CLR 0x14
  26. #define EDGE_STATUS 0x00
  27. #define EDGE_RAWSTAT 0x04
  28. #define EDGE_CFG_RISE 0x08
  29. #define EDGE_CFG_FALL 0x0c
  30. #define EDGE_CFG_RISE_SET 0x10
  31. #define EDGE_CFG_RISE_CLR 0x14
  32. #define EDGE_CFG_FALL_SET 0x18
  33. #define EDGE_CFG_FALL_CLR 0x1c
  34. struct tangox_irq_chip {
  35. void __iomem *base;
  36. unsigned long ctl;
  37. };
  38. static inline u32 intc_readl(struct tangox_irq_chip *chip, int reg)
  39. {
  40. return readl_relaxed(chip->base + reg);
  41. }
  42. static inline void intc_writel(struct tangox_irq_chip *chip, int reg, u32 val)
  43. {
  44. writel_relaxed(val, chip->base + reg);
  45. }
  46. static void tangox_dispatch_irqs(struct irq_domain *dom, unsigned int status,
  47. int base)
  48. {
  49. unsigned int hwirq;
  50. unsigned int virq;
  51. while (status) {
  52. hwirq = __ffs(status);
  53. virq = irq_find_mapping(dom, base + hwirq);
  54. if (virq)
  55. generic_handle_irq(virq);
  56. status &= ~BIT(hwirq);
  57. }
  58. }
  59. static void tangox_irq_handler(struct irq_desc *desc)
  60. {
  61. struct irq_domain *dom = irq_desc_get_handler_data(desc);
  62. struct irq_chip *host_chip = irq_desc_get_chip(desc);
  63. struct tangox_irq_chip *chip = dom->host_data;
  64. unsigned int status_lo, status_hi;
  65. chained_irq_enter(host_chip, desc);
  66. status_lo = intc_readl(chip, chip->ctl + IRQ_STATUS);
  67. status_hi = intc_readl(chip, chip->ctl + IRQ_CTL_HI + IRQ_STATUS);
  68. tangox_dispatch_irqs(dom, status_lo, 0);
  69. tangox_dispatch_irqs(dom, status_hi, 32);
  70. chained_irq_exit(host_chip, desc);
  71. }
  72. static int tangox_irq_set_type(struct irq_data *d, unsigned int flow_type)
  73. {
  74. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  75. struct tangox_irq_chip *chip = gc->domain->host_data;
  76. struct irq_chip_regs *regs = &gc->chip_types[0].regs;
  77. switch (flow_type & IRQ_TYPE_SENSE_MASK) {
  78. case IRQ_TYPE_EDGE_RISING:
  79. intc_writel(chip, regs->type + EDGE_CFG_RISE_SET, d->mask);
  80. intc_writel(chip, regs->type + EDGE_CFG_FALL_CLR, d->mask);
  81. break;
  82. case IRQ_TYPE_EDGE_FALLING:
  83. intc_writel(chip, regs->type + EDGE_CFG_RISE_CLR, d->mask);
  84. intc_writel(chip, regs->type + EDGE_CFG_FALL_SET, d->mask);
  85. break;
  86. case IRQ_TYPE_LEVEL_HIGH:
  87. intc_writel(chip, regs->type + EDGE_CFG_RISE_CLR, d->mask);
  88. intc_writel(chip, regs->type + EDGE_CFG_FALL_CLR, d->mask);
  89. break;
  90. case IRQ_TYPE_LEVEL_LOW:
  91. intc_writel(chip, regs->type + EDGE_CFG_RISE_SET, d->mask);
  92. intc_writel(chip, regs->type + EDGE_CFG_FALL_SET, d->mask);
  93. break;
  94. default:
  95. pr_err("Invalid trigger mode %x for IRQ %d\n",
  96. flow_type, d->irq);
  97. return -EINVAL;
  98. }
  99. return irq_setup_alt_chip(d, flow_type);
  100. }
  101. static void __init tangox_irq_init_chip(struct irq_chip_generic *gc,
  102. unsigned long ctl_offs,
  103. unsigned long edge_offs)
  104. {
  105. struct tangox_irq_chip *chip = gc->domain->host_data;
  106. struct irq_chip_type *ct = gc->chip_types;
  107. unsigned long ctl_base = chip->ctl + ctl_offs;
  108. unsigned long edge_base = EDGE_CTL_BASE + edge_offs;
  109. int i;
  110. gc->reg_base = chip->base;
  111. gc->unused = 0;
  112. for (i = 0; i < 2; i++) {
  113. ct[i].chip.irq_ack = irq_gc_ack_set_bit;
  114. ct[i].chip.irq_mask = irq_gc_mask_disable_reg;
  115. ct[i].chip.irq_mask_ack = irq_gc_mask_disable_and_ack_set;
  116. ct[i].chip.irq_unmask = irq_gc_unmask_enable_reg;
  117. ct[i].chip.irq_set_type = tangox_irq_set_type;
  118. ct[i].chip.name = gc->domain->name;
  119. ct[i].regs.enable = ctl_base + IRQ_EN_SET;
  120. ct[i].regs.disable = ctl_base + IRQ_EN_CLR;
  121. ct[i].regs.ack = edge_base + EDGE_RAWSTAT;
  122. ct[i].regs.type = edge_base;
  123. }
  124. ct[0].type = IRQ_TYPE_LEVEL_MASK;
  125. ct[0].handler = handle_level_irq;
  126. ct[1].type = IRQ_TYPE_EDGE_BOTH;
  127. ct[1].handler = handle_edge_irq;
  128. intc_writel(chip, ct->regs.disable, 0xffffffff);
  129. intc_writel(chip, ct->regs.ack, 0xffffffff);
  130. }
  131. static void __init tangox_irq_domain_init(struct irq_domain *dom)
  132. {
  133. struct irq_chip_generic *gc;
  134. int i;
  135. for (i = 0; i < 2; i++) {
  136. gc = irq_get_domain_generic_chip(dom, i * 32);
  137. tangox_irq_init_chip(gc, i * IRQ_CTL_HI, i * EDGE_CTL_HI);
  138. }
  139. }
  140. static int __init tangox_irq_init(void __iomem *base, struct resource *baseres,
  141. struct device_node *node)
  142. {
  143. struct tangox_irq_chip *chip;
  144. struct irq_domain *dom;
  145. struct resource res;
  146. int irq;
  147. int err;
  148. irq = irq_of_parse_and_map(node, 0);
  149. if (!irq)
  150. panic("%pOFn: failed to get IRQ", node);
  151. err = of_address_to_resource(node, 0, &res);
  152. if (err)
  153. panic("%pOFn: failed to get address", node);
  154. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  155. chip->ctl = res.start - baseres->start;
  156. chip->base = base;
  157. dom = irq_domain_add_linear(node, 64, &irq_generic_chip_ops, chip);
  158. if (!dom)
  159. panic("%pOFn: failed to create irqdomain", node);
  160. err = irq_alloc_domain_generic_chips(dom, 32, 2, node->name,
  161. handle_level_irq, 0, 0, 0);
  162. if (err)
  163. panic("%pOFn: failed to allocate irqchip", node);
  164. tangox_irq_domain_init(dom);
  165. irq_set_chained_handler_and_data(irq, tangox_irq_handler, dom);
  166. return 0;
  167. }
  168. static int __init tangox_of_irq_init(struct device_node *node,
  169. struct device_node *parent)
  170. {
  171. struct device_node *c;
  172. struct resource res;
  173. void __iomem *base;
  174. base = of_iomap(node, 0);
  175. if (!base)
  176. panic("%pOFn: of_iomap failed", node);
  177. of_address_to_resource(node, 0, &res);
  178. for_each_child_of_node(node, c)
  179. tangox_irq_init(base, &res, c);
  180. return 0;
  181. }
  182. IRQCHIP_DECLARE(tangox_intc, "sigma,smp8642-intc", tangox_of_irq_init);