irq-sun4i.c 6.0 KB

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  1. /*
  2. * Allwinner A1X SoCs IRQ chip driver.
  3. *
  4. * Copyright (C) 2012 Maxime Ripard
  5. *
  6. * Maxime Ripard <maxime.ripard@free-electrons.com>
  7. *
  8. * Based on code from
  9. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10. * Benn Huang <benn@allwinnertech.com>
  11. *
  12. * This file is licensed under the terms of the GNU General Public
  13. * License version 2. This program is licensed "as is" without any
  14. * warranty of any kind, whether express or implied.
  15. */
  16. #include <linux/io.h>
  17. #include <linux/irq.h>
  18. #include <linux/irqchip.h>
  19. #include <linux/of.h>
  20. #include <linux/of_address.h>
  21. #include <linux/of_irq.h>
  22. #include <asm/exception.h>
  23. #define SUN4I_IRQ_VECTOR_REG 0x00
  24. #define SUN4I_IRQ_PROTECTION_REG 0x08
  25. #define SUN4I_IRQ_NMI_CTRL_REG 0x0c
  26. #define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
  27. #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
  28. #define SUN4I_IRQ_ENABLE_REG(data, x) ((data)->enable_reg_offset + 0x4 * x)
  29. #define SUN4I_IRQ_MASK_REG(data, x) ((data)->mask_reg_offset + 0x4 * x)
  30. #define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40
  31. #define SUN4I_IRQ_MASK_REG_OFFSET 0x50
  32. #define SUNIV_IRQ_ENABLE_REG_OFFSET 0x20
  33. #define SUNIV_IRQ_MASK_REG_OFFSET 0x30
  34. struct sun4i_irq_chip_data {
  35. void __iomem *irq_base;
  36. struct irq_domain *irq_domain;
  37. u32 enable_reg_offset;
  38. u32 mask_reg_offset;
  39. };
  40. static struct sun4i_irq_chip_data *irq_ic_data;
  41. static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
  42. static void sun4i_irq_ack(struct irq_data *irqd)
  43. {
  44. unsigned int irq = irqd_to_hwirq(irqd);
  45. if (irq != 0)
  46. return; /* Only IRQ 0 / the ENMI needs to be acked */
  47. writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
  48. }
  49. static void sun4i_irq_mask(struct irq_data *irqd)
  50. {
  51. unsigned int irq = irqd_to_hwirq(irqd);
  52. unsigned int irq_off = irq % 32;
  53. int reg = irq / 32;
  54. u32 val;
  55. val = readl(irq_ic_data->irq_base +
  56. SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
  57. writel(val & ~(1 << irq_off),
  58. irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
  59. }
  60. static void sun4i_irq_unmask(struct irq_data *irqd)
  61. {
  62. unsigned int irq = irqd_to_hwirq(irqd);
  63. unsigned int irq_off = irq % 32;
  64. int reg = irq / 32;
  65. u32 val;
  66. val = readl(irq_ic_data->irq_base +
  67. SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
  68. writel(val | (1 << irq_off),
  69. irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));
  70. }
  71. static struct irq_chip sun4i_irq_chip = {
  72. .name = "sun4i_irq",
  73. .irq_eoi = sun4i_irq_ack,
  74. .irq_mask = sun4i_irq_mask,
  75. .irq_unmask = sun4i_irq_unmask,
  76. .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
  77. };
  78. static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
  79. irq_hw_number_t hw)
  80. {
  81. irq_set_chip_and_handler(virq, &sun4i_irq_chip, handle_fasteoi_irq);
  82. irq_set_probe(virq);
  83. return 0;
  84. }
  85. static const struct irq_domain_ops sun4i_irq_ops = {
  86. .map = sun4i_irq_map,
  87. .xlate = irq_domain_xlate_onecell,
  88. };
  89. static int __init sun4i_of_init(struct device_node *node,
  90. struct device_node *parent)
  91. {
  92. irq_ic_data->irq_base = of_iomap(node, 0);
  93. if (!irq_ic_data->irq_base)
  94. panic("%pOF: unable to map IC registers\n",
  95. node);
  96. /* Disable all interrupts */
  97. writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 0));
  98. writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 1));
  99. writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 2));
  100. /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
  101. writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 0));
  102. writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 1));
  103. writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 2));
  104. /* Clear all the pending interrupts */
  105. writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
  106. writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(1));
  107. writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(2));
  108. /* Enable protection mode */
  109. writel(0x01, irq_ic_data->irq_base + SUN4I_IRQ_PROTECTION_REG);
  110. /* Configure the external interrupt source type */
  111. writel(0x00, irq_ic_data->irq_base + SUN4I_IRQ_NMI_CTRL_REG);
  112. irq_ic_data->irq_domain = irq_domain_add_linear(node, 3 * 32,
  113. &sun4i_irq_ops, NULL);
  114. if (!irq_ic_data->irq_domain)
  115. panic("%pOF: unable to create IRQ domain\n", node);
  116. set_handle_irq(sun4i_handle_irq);
  117. return 0;
  118. }
  119. static int __init sun4i_ic_of_init(struct device_node *node,
  120. struct device_node *parent)
  121. {
  122. irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL);
  123. if (!irq_ic_data) {
  124. pr_err("kzalloc failed!\n");
  125. return -ENOMEM;
  126. }
  127. irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET;
  128. irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET;
  129. return sun4i_of_init(node, parent);
  130. }
  131. IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init);
  132. static int __init suniv_ic_of_init(struct device_node *node,
  133. struct device_node *parent)
  134. {
  135. irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL);
  136. if (!irq_ic_data) {
  137. pr_err("kzalloc failed!\n");
  138. return -ENOMEM;
  139. }
  140. irq_ic_data->enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET;
  141. irq_ic_data->mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET;
  142. return sun4i_of_init(node, parent);
  143. }
  144. IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic",
  145. suniv_ic_of_init);
  146. static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
  147. {
  148. u32 hwirq;
  149. /*
  150. * hwirq == 0 can mean one of 3 things:
  151. * 1) no more irqs pending
  152. * 2) irq 0 pending
  153. * 3) spurious irq
  154. * So if we immediately get a reading of 0, check the irq-pending reg
  155. * to differentiate between 2 and 3. We only do this once to avoid
  156. * the extra check in the common case of 1 hapening after having
  157. * read the vector-reg once.
  158. */
  159. hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
  160. if (hwirq == 0 &&
  161. !(readl(irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)) &
  162. BIT(0)))
  163. return;
  164. do {
  165. handle_domain_irq(irq_ic_data->irq_domain, hwirq, regs);
  166. hwirq = readl(irq_ic_data->irq_base +
  167. SUN4I_IRQ_VECTOR_REG) >> 2;
  168. } while (hwirq != 0);
  169. }