irq-stm32-exti.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) Maxime Coquelin 2015
  4. * Copyright (C) STMicroelectronics 2017
  5. * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/delay.h>
  9. #include <linux/hwspinlock.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/irq.h>
  13. #include <linux/irqchip.h>
  14. #include <linux/irqchip/chained_irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/module.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/syscore_ops.h>
  21. #include <dt-bindings/interrupt-controller/arm-gic.h>
  22. #define IRQS_PER_BANK 32
  23. #define HWSPNLCK_TIMEOUT 1000 /* usec */
  24. struct stm32_exti_bank {
  25. u32 imr_ofst;
  26. u32 emr_ofst;
  27. u32 rtsr_ofst;
  28. u32 ftsr_ofst;
  29. u32 swier_ofst;
  30. u32 rpr_ofst;
  31. u32 fpr_ofst;
  32. };
  33. #define UNDEF_REG ~0
  34. struct stm32_desc_irq {
  35. u32 exti;
  36. u32 irq_parent;
  37. struct irq_chip *chip;
  38. };
  39. struct stm32_exti_drv_data {
  40. const struct stm32_exti_bank **exti_banks;
  41. const struct stm32_desc_irq *desc_irqs;
  42. u32 bank_nr;
  43. u32 irq_nr;
  44. };
  45. struct stm32_exti_chip_data {
  46. struct stm32_exti_host_data *host_data;
  47. const struct stm32_exti_bank *reg_bank;
  48. struct raw_spinlock rlock;
  49. u32 wake_active;
  50. u32 mask_cache;
  51. u32 rtsr_cache;
  52. u32 ftsr_cache;
  53. };
  54. struct stm32_exti_host_data {
  55. void __iomem *base;
  56. struct stm32_exti_chip_data *chips_data;
  57. const struct stm32_exti_drv_data *drv_data;
  58. struct hwspinlock *hwlock;
  59. };
  60. static struct stm32_exti_host_data *stm32_host_data;
  61. static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
  62. .imr_ofst = 0x00,
  63. .emr_ofst = 0x04,
  64. .rtsr_ofst = 0x08,
  65. .ftsr_ofst = 0x0C,
  66. .swier_ofst = 0x10,
  67. .rpr_ofst = 0x14,
  68. .fpr_ofst = UNDEF_REG,
  69. };
  70. static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
  71. &stm32f4xx_exti_b1,
  72. };
  73. static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
  74. .exti_banks = stm32f4xx_exti_banks,
  75. .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
  76. };
  77. static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
  78. .imr_ofst = 0x80,
  79. .emr_ofst = 0x84,
  80. .rtsr_ofst = 0x00,
  81. .ftsr_ofst = 0x04,
  82. .swier_ofst = 0x08,
  83. .rpr_ofst = 0x88,
  84. .fpr_ofst = UNDEF_REG,
  85. };
  86. static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
  87. .imr_ofst = 0x90,
  88. .emr_ofst = 0x94,
  89. .rtsr_ofst = 0x20,
  90. .ftsr_ofst = 0x24,
  91. .swier_ofst = 0x28,
  92. .rpr_ofst = 0x98,
  93. .fpr_ofst = UNDEF_REG,
  94. };
  95. static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
  96. .imr_ofst = 0xA0,
  97. .emr_ofst = 0xA4,
  98. .rtsr_ofst = 0x40,
  99. .ftsr_ofst = 0x44,
  100. .swier_ofst = 0x48,
  101. .rpr_ofst = 0xA8,
  102. .fpr_ofst = UNDEF_REG,
  103. };
  104. static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
  105. &stm32h7xx_exti_b1,
  106. &stm32h7xx_exti_b2,
  107. &stm32h7xx_exti_b3,
  108. };
  109. static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
  110. .exti_banks = stm32h7xx_exti_banks,
  111. .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
  112. };
  113. static const struct stm32_exti_bank stm32mp1_exti_b1 = {
  114. .imr_ofst = 0x80,
  115. .emr_ofst = 0x84,
  116. .rtsr_ofst = 0x00,
  117. .ftsr_ofst = 0x04,
  118. .swier_ofst = 0x08,
  119. .rpr_ofst = 0x0C,
  120. .fpr_ofst = 0x10,
  121. };
  122. static const struct stm32_exti_bank stm32mp1_exti_b2 = {
  123. .imr_ofst = 0x90,
  124. .emr_ofst = 0x94,
  125. .rtsr_ofst = 0x20,
  126. .ftsr_ofst = 0x24,
  127. .swier_ofst = 0x28,
  128. .rpr_ofst = 0x2C,
  129. .fpr_ofst = 0x30,
  130. };
  131. static const struct stm32_exti_bank stm32mp1_exti_b3 = {
  132. .imr_ofst = 0xA0,
  133. .emr_ofst = 0xA4,
  134. .rtsr_ofst = 0x40,
  135. .ftsr_ofst = 0x44,
  136. .swier_ofst = 0x48,
  137. .rpr_ofst = 0x4C,
  138. .fpr_ofst = 0x50,
  139. };
  140. static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
  141. &stm32mp1_exti_b1,
  142. &stm32mp1_exti_b2,
  143. &stm32mp1_exti_b3,
  144. };
  145. static struct irq_chip stm32_exti_h_chip;
  146. static struct irq_chip stm32_exti_h_chip_direct;
  147. static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
  148. { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
  149. { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
  150. { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
  151. { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
  152. { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
  153. { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip },
  154. { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip },
  155. { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip },
  156. { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip },
  157. { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip },
  158. { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip },
  159. { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip },
  160. { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip },
  161. { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip },
  162. { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip },
  163. { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip },
  164. { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
  165. { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
  166. { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct },
  167. { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct },
  168. { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
  169. { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct },
  170. { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
  171. { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
  172. { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
  173. { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct },
  174. { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct },
  175. { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct },
  176. { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct },
  177. { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
  178. { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
  179. { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
  180. { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip },
  181. { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct },
  182. { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip },
  183. };
  184. static const struct stm32_exti_drv_data stm32mp1_drv_data = {
  185. .exti_banks = stm32mp1_exti_banks,
  186. .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
  187. .desc_irqs = stm32mp1_desc_irq,
  188. .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
  189. };
  190. static const struct
  191. stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
  192. irq_hw_number_t hwirq)
  193. {
  194. const struct stm32_desc_irq *desc = NULL;
  195. int i;
  196. if (!drv_data->desc_irqs)
  197. return NULL;
  198. for (i = 0; i < drv_data->irq_nr; i++) {
  199. desc = &drv_data->desc_irqs[i];
  200. if (desc->exti == hwirq)
  201. break;
  202. }
  203. return desc;
  204. }
  205. static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
  206. {
  207. struct stm32_exti_chip_data *chip_data = gc->private;
  208. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  209. unsigned long pending;
  210. pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
  211. if (stm32_bank->fpr_ofst != UNDEF_REG)
  212. pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
  213. return pending;
  214. }
  215. static void stm32_irq_handler(struct irq_desc *desc)
  216. {
  217. struct irq_domain *domain = irq_desc_get_handler_data(desc);
  218. struct irq_chip *chip = irq_desc_get_chip(desc);
  219. unsigned int virq, nbanks = domain->gc->num_chips;
  220. struct irq_chip_generic *gc;
  221. unsigned long pending;
  222. int n, i, irq_base = 0;
  223. chained_irq_enter(chip, desc);
  224. for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
  225. gc = irq_get_domain_generic_chip(domain, irq_base);
  226. while ((pending = stm32_exti_pending(gc))) {
  227. for_each_set_bit(n, &pending, IRQS_PER_BANK) {
  228. virq = irq_find_mapping(domain, irq_base + n);
  229. generic_handle_irq(virq);
  230. }
  231. }
  232. }
  233. chained_irq_exit(chip, desc);
  234. }
  235. static int stm32_exti_set_type(struct irq_data *d,
  236. unsigned int type, u32 *rtsr, u32 *ftsr)
  237. {
  238. u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
  239. switch (type) {
  240. case IRQ_TYPE_EDGE_RISING:
  241. *rtsr |= mask;
  242. *ftsr &= ~mask;
  243. break;
  244. case IRQ_TYPE_EDGE_FALLING:
  245. *rtsr &= ~mask;
  246. *ftsr |= mask;
  247. break;
  248. case IRQ_TYPE_EDGE_BOTH:
  249. *rtsr |= mask;
  250. *ftsr |= mask;
  251. break;
  252. default:
  253. return -EINVAL;
  254. }
  255. return 0;
  256. }
  257. static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
  258. {
  259. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  260. struct stm32_exti_chip_data *chip_data = gc->private;
  261. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  262. struct hwspinlock *hwlock = chip_data->host_data->hwlock;
  263. u32 rtsr, ftsr;
  264. int err;
  265. irq_gc_lock(gc);
  266. if (hwlock) {
  267. err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
  268. if (err) {
  269. pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
  270. goto unlock;
  271. }
  272. }
  273. rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
  274. ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
  275. err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
  276. if (err)
  277. goto unspinlock;
  278. irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
  279. irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
  280. unspinlock:
  281. if (hwlock)
  282. hwspin_unlock_in_atomic(hwlock);
  283. unlock:
  284. irq_gc_unlock(gc);
  285. return err;
  286. }
  287. static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
  288. u32 wake_active)
  289. {
  290. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  291. void __iomem *base = chip_data->host_data->base;
  292. /* save rtsr, ftsr registers */
  293. chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
  294. chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
  295. writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
  296. }
  297. static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
  298. u32 mask_cache)
  299. {
  300. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  301. void __iomem *base = chip_data->host_data->base;
  302. /* restore rtsr, ftsr, registers */
  303. writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
  304. writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
  305. writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
  306. }
  307. static void stm32_irq_suspend(struct irq_chip_generic *gc)
  308. {
  309. struct stm32_exti_chip_data *chip_data = gc->private;
  310. irq_gc_lock(gc);
  311. stm32_chip_suspend(chip_data, gc->wake_active);
  312. irq_gc_unlock(gc);
  313. }
  314. static void stm32_irq_resume(struct irq_chip_generic *gc)
  315. {
  316. struct stm32_exti_chip_data *chip_data = gc->private;
  317. irq_gc_lock(gc);
  318. stm32_chip_resume(chip_data, gc->mask_cache);
  319. irq_gc_unlock(gc);
  320. }
  321. static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
  322. unsigned int nr_irqs, void *data)
  323. {
  324. struct irq_fwspec *fwspec = data;
  325. irq_hw_number_t hwirq;
  326. hwirq = fwspec->param[0];
  327. irq_map_generic_chip(d, virq, hwirq);
  328. return 0;
  329. }
  330. static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
  331. unsigned int nr_irqs)
  332. {
  333. struct irq_data *data = irq_domain_get_irq_data(d, virq);
  334. irq_domain_reset_irq_data(data);
  335. }
  336. static const struct irq_domain_ops irq_exti_domain_ops = {
  337. .map = irq_map_generic_chip,
  338. .alloc = stm32_exti_alloc,
  339. .free = stm32_exti_free,
  340. };
  341. static void stm32_irq_ack(struct irq_data *d)
  342. {
  343. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  344. struct stm32_exti_chip_data *chip_data = gc->private;
  345. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  346. irq_gc_lock(gc);
  347. irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
  348. if (stm32_bank->fpr_ofst != UNDEF_REG)
  349. irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
  350. irq_gc_unlock(gc);
  351. }
  352. /* directly set the target bit without reading first. */
  353. static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
  354. {
  355. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  356. void __iomem *base = chip_data->host_data->base;
  357. u32 val = BIT(d->hwirq % IRQS_PER_BANK);
  358. writel_relaxed(val, base + reg);
  359. }
  360. static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
  361. {
  362. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  363. void __iomem *base = chip_data->host_data->base;
  364. u32 val;
  365. val = readl_relaxed(base + reg);
  366. val |= BIT(d->hwirq % IRQS_PER_BANK);
  367. writel_relaxed(val, base + reg);
  368. return val;
  369. }
  370. static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
  371. {
  372. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  373. void __iomem *base = chip_data->host_data->base;
  374. u32 val;
  375. val = readl_relaxed(base + reg);
  376. val &= ~BIT(d->hwirq % IRQS_PER_BANK);
  377. writel_relaxed(val, base + reg);
  378. return val;
  379. }
  380. static void stm32_exti_h_eoi(struct irq_data *d)
  381. {
  382. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  383. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  384. raw_spin_lock(&chip_data->rlock);
  385. stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
  386. if (stm32_bank->fpr_ofst != UNDEF_REG)
  387. stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
  388. raw_spin_unlock(&chip_data->rlock);
  389. if (d->parent_data->chip)
  390. irq_chip_eoi_parent(d);
  391. }
  392. static void stm32_exti_h_mask(struct irq_data *d)
  393. {
  394. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  395. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  396. raw_spin_lock(&chip_data->rlock);
  397. chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
  398. raw_spin_unlock(&chip_data->rlock);
  399. if (d->parent_data->chip)
  400. irq_chip_mask_parent(d);
  401. }
  402. static void stm32_exti_h_unmask(struct irq_data *d)
  403. {
  404. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  405. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  406. raw_spin_lock(&chip_data->rlock);
  407. chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
  408. raw_spin_unlock(&chip_data->rlock);
  409. if (d->parent_data->chip)
  410. irq_chip_unmask_parent(d);
  411. }
  412. static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
  413. {
  414. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  415. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  416. struct hwspinlock *hwlock = chip_data->host_data->hwlock;
  417. void __iomem *base = chip_data->host_data->base;
  418. u32 rtsr, ftsr;
  419. int err;
  420. raw_spin_lock(&chip_data->rlock);
  421. if (hwlock) {
  422. err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
  423. if (err) {
  424. pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
  425. goto unlock;
  426. }
  427. }
  428. rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
  429. ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
  430. err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
  431. if (err)
  432. goto unspinlock;
  433. writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
  434. writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
  435. unspinlock:
  436. if (hwlock)
  437. hwspin_unlock_in_atomic(hwlock);
  438. unlock:
  439. raw_spin_unlock(&chip_data->rlock);
  440. return err;
  441. }
  442. static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
  443. {
  444. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  445. u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
  446. raw_spin_lock(&chip_data->rlock);
  447. if (on)
  448. chip_data->wake_active |= mask;
  449. else
  450. chip_data->wake_active &= ~mask;
  451. raw_spin_unlock(&chip_data->rlock);
  452. return 0;
  453. }
  454. static int stm32_exti_h_set_affinity(struct irq_data *d,
  455. const struct cpumask *dest, bool force)
  456. {
  457. if (d->parent_data->chip)
  458. return irq_chip_set_affinity_parent(d, dest, force);
  459. return -EINVAL;
  460. }
  461. static int __maybe_unused stm32_exti_h_suspend(void)
  462. {
  463. struct stm32_exti_chip_data *chip_data;
  464. int i;
  465. for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
  466. chip_data = &stm32_host_data->chips_data[i];
  467. raw_spin_lock(&chip_data->rlock);
  468. stm32_chip_suspend(chip_data, chip_data->wake_active);
  469. raw_spin_unlock(&chip_data->rlock);
  470. }
  471. return 0;
  472. }
  473. static void __maybe_unused stm32_exti_h_resume(void)
  474. {
  475. struct stm32_exti_chip_data *chip_data;
  476. int i;
  477. for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
  478. chip_data = &stm32_host_data->chips_data[i];
  479. raw_spin_lock(&chip_data->rlock);
  480. stm32_chip_resume(chip_data, chip_data->mask_cache);
  481. raw_spin_unlock(&chip_data->rlock);
  482. }
  483. }
  484. static struct syscore_ops stm32_exti_h_syscore_ops = {
  485. #ifdef CONFIG_PM_SLEEP
  486. .suspend = stm32_exti_h_suspend,
  487. .resume = stm32_exti_h_resume,
  488. #endif
  489. };
  490. static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data)
  491. {
  492. stm32_host_data = host_data;
  493. register_syscore_ops(&stm32_exti_h_syscore_ops);
  494. }
  495. static void stm32_exti_h_syscore_deinit(void)
  496. {
  497. unregister_syscore_ops(&stm32_exti_h_syscore_ops);
  498. }
  499. static int stm32_exti_h_retrigger(struct irq_data *d)
  500. {
  501. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  502. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  503. void __iomem *base = chip_data->host_data->base;
  504. u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
  505. writel_relaxed(mask, base + stm32_bank->swier_ofst);
  506. return 0;
  507. }
  508. static struct irq_chip stm32_exti_h_chip = {
  509. .name = "stm32-exti-h",
  510. .irq_eoi = stm32_exti_h_eoi,
  511. .irq_mask = stm32_exti_h_mask,
  512. .irq_unmask = stm32_exti_h_unmask,
  513. .irq_retrigger = stm32_exti_h_retrigger,
  514. .irq_set_type = stm32_exti_h_set_type,
  515. .irq_set_wake = stm32_exti_h_set_wake,
  516. .flags = IRQCHIP_MASK_ON_SUSPEND,
  517. .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
  518. };
  519. static struct irq_chip stm32_exti_h_chip_direct = {
  520. .name = "stm32-exti-h-direct",
  521. .irq_eoi = irq_chip_eoi_parent,
  522. .irq_ack = irq_chip_ack_parent,
  523. .irq_mask = irq_chip_mask_parent,
  524. .irq_unmask = irq_chip_unmask_parent,
  525. .irq_retrigger = irq_chip_retrigger_hierarchy,
  526. .irq_set_type = irq_chip_set_type_parent,
  527. .irq_set_wake = stm32_exti_h_set_wake,
  528. .flags = IRQCHIP_MASK_ON_SUSPEND,
  529. .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
  530. };
  531. static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
  532. unsigned int virq,
  533. unsigned int nr_irqs, void *data)
  534. {
  535. struct stm32_exti_host_data *host_data = dm->host_data;
  536. struct stm32_exti_chip_data *chip_data;
  537. const struct stm32_desc_irq *desc;
  538. struct irq_fwspec *fwspec = data;
  539. struct irq_fwspec p_fwspec;
  540. irq_hw_number_t hwirq;
  541. int bank;
  542. hwirq = fwspec->param[0];
  543. bank = hwirq / IRQS_PER_BANK;
  544. chip_data = &host_data->chips_data[bank];
  545. desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
  546. if (!desc)
  547. return -EINVAL;
  548. irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip,
  549. chip_data);
  550. if (desc->irq_parent) {
  551. p_fwspec.fwnode = dm->parent->fwnode;
  552. p_fwspec.param_count = 3;
  553. p_fwspec.param[0] = GIC_SPI;
  554. p_fwspec.param[1] = desc->irq_parent;
  555. p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
  556. return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
  557. }
  558. return 0;
  559. }
  560. static struct
  561. stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
  562. struct device_node *node)
  563. {
  564. struct stm32_exti_host_data *host_data;
  565. host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
  566. if (!host_data)
  567. return NULL;
  568. host_data->drv_data = dd;
  569. host_data->chips_data = kcalloc(dd->bank_nr,
  570. sizeof(struct stm32_exti_chip_data),
  571. GFP_KERNEL);
  572. if (!host_data->chips_data)
  573. goto free_host_data;
  574. host_data->base = of_iomap(node, 0);
  575. if (!host_data->base) {
  576. pr_err("%pOF: Unable to map registers\n", node);
  577. goto free_chips_data;
  578. }
  579. stm32_host_data = host_data;
  580. return host_data;
  581. free_chips_data:
  582. kfree(host_data->chips_data);
  583. free_host_data:
  584. kfree(host_data);
  585. return NULL;
  586. }
  587. static struct
  588. stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
  589. u32 bank_idx,
  590. struct device_node *node)
  591. {
  592. const struct stm32_exti_bank *stm32_bank;
  593. struct stm32_exti_chip_data *chip_data;
  594. void __iomem *base = h_data->base;
  595. stm32_bank = h_data->drv_data->exti_banks[bank_idx];
  596. chip_data = &h_data->chips_data[bank_idx];
  597. chip_data->host_data = h_data;
  598. chip_data->reg_bank = stm32_bank;
  599. raw_spin_lock_init(&chip_data->rlock);
  600. /*
  601. * This IP has no reset, so after hot reboot we should
  602. * clear registers to avoid residue
  603. */
  604. writel_relaxed(0, base + stm32_bank->imr_ofst);
  605. writel_relaxed(0, base + stm32_bank->emr_ofst);
  606. pr_info("%pOF: bank%d\n", node, bank_idx);
  607. return chip_data;
  608. }
  609. static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
  610. struct device_node *node)
  611. {
  612. struct stm32_exti_host_data *host_data;
  613. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  614. int nr_irqs, ret, i;
  615. struct irq_chip_generic *gc;
  616. struct irq_domain *domain;
  617. host_data = stm32_exti_host_init(drv_data, node);
  618. if (!host_data)
  619. return -ENOMEM;
  620. domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
  621. &irq_exti_domain_ops, NULL);
  622. if (!domain) {
  623. pr_err("%pOFn: Could not register interrupt domain.\n",
  624. node);
  625. ret = -ENOMEM;
  626. goto out_unmap;
  627. }
  628. ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
  629. handle_edge_irq, clr, 0, 0);
  630. if (ret) {
  631. pr_err("%pOF: Could not allocate generic interrupt chip.\n",
  632. node);
  633. goto out_free_domain;
  634. }
  635. for (i = 0; i < drv_data->bank_nr; i++) {
  636. const struct stm32_exti_bank *stm32_bank;
  637. struct stm32_exti_chip_data *chip_data;
  638. stm32_bank = drv_data->exti_banks[i];
  639. chip_data = stm32_exti_chip_init(host_data, i, node);
  640. gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
  641. gc->reg_base = host_data->base;
  642. gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
  643. gc->chip_types->chip.irq_ack = stm32_irq_ack;
  644. gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
  645. gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
  646. gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
  647. gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
  648. gc->suspend = stm32_irq_suspend;
  649. gc->resume = stm32_irq_resume;
  650. gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
  651. gc->chip_types->regs.mask = stm32_bank->imr_ofst;
  652. gc->private = (void *)chip_data;
  653. }
  654. nr_irqs = of_irq_count(node);
  655. for (i = 0; i < nr_irqs; i++) {
  656. unsigned int irq = irq_of_parse_and_map(node, i);
  657. irq_set_handler_data(irq, domain);
  658. irq_set_chained_handler(irq, stm32_irq_handler);
  659. }
  660. return 0;
  661. out_free_domain:
  662. irq_domain_remove(domain);
  663. out_unmap:
  664. iounmap(host_data->base);
  665. kfree(host_data->chips_data);
  666. kfree(host_data);
  667. return ret;
  668. }
  669. static const struct irq_domain_ops stm32_exti_h_domain_ops = {
  670. .alloc = stm32_exti_h_domain_alloc,
  671. .free = irq_domain_free_irqs_common,
  672. .xlate = irq_domain_xlate_twocell,
  673. };
  674. static void stm32_exti_remove_irq(void *data)
  675. {
  676. struct irq_domain *domain = data;
  677. irq_domain_remove(domain);
  678. }
  679. static int stm32_exti_remove(struct platform_device *pdev)
  680. {
  681. stm32_exti_h_syscore_deinit();
  682. return 0;
  683. }
  684. static int stm32_exti_probe(struct platform_device *pdev)
  685. {
  686. int ret, i;
  687. struct device *dev = &pdev->dev;
  688. struct device_node *np = dev->of_node;
  689. struct irq_domain *parent_domain, *domain;
  690. struct stm32_exti_host_data *host_data;
  691. const struct stm32_exti_drv_data *drv_data;
  692. struct resource *res;
  693. host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
  694. if (!host_data)
  695. return -ENOMEM;
  696. /* check for optional hwspinlock which may be not available yet */
  697. ret = of_hwspin_lock_get_id(np, 0);
  698. if (ret == -EPROBE_DEFER)
  699. /* hwspinlock framework not yet ready */
  700. return ret;
  701. if (ret >= 0) {
  702. host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
  703. if (!host_data->hwlock) {
  704. dev_err(dev, "Failed to request hwspinlock\n");
  705. return -EINVAL;
  706. }
  707. } else if (ret != -ENOENT) {
  708. /* note: ENOENT is a valid case (means 'no hwspinlock') */
  709. dev_err(dev, "Failed to get hwspinlock\n");
  710. return ret;
  711. }
  712. /* initialize host_data */
  713. drv_data = of_device_get_match_data(dev);
  714. if (!drv_data) {
  715. dev_err(dev, "no of match data\n");
  716. return -ENODEV;
  717. }
  718. host_data->drv_data = drv_data;
  719. host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
  720. sizeof(*host_data->chips_data),
  721. GFP_KERNEL);
  722. if (!host_data->chips_data)
  723. return -ENOMEM;
  724. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  725. host_data->base = devm_ioremap_resource(dev, res);
  726. if (IS_ERR(host_data->base)) {
  727. dev_err(dev, "Unable to map registers\n");
  728. return PTR_ERR(host_data->base);
  729. }
  730. for (i = 0; i < drv_data->bank_nr; i++)
  731. stm32_exti_chip_init(host_data, i, np);
  732. parent_domain = irq_find_host(of_irq_find_parent(np));
  733. if (!parent_domain) {
  734. dev_err(dev, "GIC interrupt-parent not found\n");
  735. return -EINVAL;
  736. }
  737. domain = irq_domain_add_hierarchy(parent_domain, 0,
  738. drv_data->bank_nr * IRQS_PER_BANK,
  739. np, &stm32_exti_h_domain_ops,
  740. host_data);
  741. if (!domain) {
  742. dev_err(dev, "Could not register exti domain\n");
  743. return -ENOMEM;
  744. }
  745. ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
  746. if (ret)
  747. return ret;
  748. stm32_exti_h_syscore_init(host_data);
  749. return 0;
  750. }
  751. /* platform driver only for MP1 */
  752. static const struct of_device_id stm32_exti_ids[] = {
  753. { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
  754. {},
  755. };
  756. MODULE_DEVICE_TABLE(of, stm32_exti_ids);
  757. static struct platform_driver stm32_exti_driver = {
  758. .probe = stm32_exti_probe,
  759. .remove = stm32_exti_remove,
  760. .driver = {
  761. .name = "stm32_exti",
  762. .of_match_table = stm32_exti_ids,
  763. },
  764. };
  765. static int __init stm32_exti_arch_init(void)
  766. {
  767. return platform_driver_register(&stm32_exti_driver);
  768. }
  769. static void __exit stm32_exti_arch_exit(void)
  770. {
  771. return platform_driver_unregister(&stm32_exti_driver);
  772. }
  773. arch_initcall(stm32_exti_arch_init);
  774. module_exit(stm32_exti_arch_exit);
  775. /* no platform driver for F4 and H7 */
  776. static int __init stm32f4_exti_of_init(struct device_node *np,
  777. struct device_node *parent)
  778. {
  779. return stm32_exti_init(&stm32f4xx_drv_data, np);
  780. }
  781. IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
  782. static int __init stm32h7_exti_of_init(struct device_node *np,
  783. struct device_node *parent)
  784. {
  785. return stm32_exti_init(&stm32h7xx_drv_data, np);
  786. }
  787. IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);