irq-sni-exiu.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for Socionext External Interrupt Unit (EXIU)
  4. *
  5. * Copyright (c) 2017-2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
  6. *
  7. * Based on irq-tegra.c:
  8. * Copyright (C) 2011 Google, Inc.
  9. * Copyright (C) 2010,2013, NVIDIA Corporation
  10. */
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/irq.h>
  14. #include <linux/irqchip.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/platform_device.h>
  20. #include <dt-bindings/interrupt-controller/arm-gic.h>
  21. #define NUM_IRQS 32
  22. #define EIMASK 0x00
  23. #define EISRCSEL 0x04
  24. #define EIREQSTA 0x08
  25. #define EIRAWREQSTA 0x0C
  26. #define EIREQCLR 0x10
  27. #define EILVL 0x14
  28. #define EIEDG 0x18
  29. #define EISIR 0x1C
  30. struct exiu_irq_data {
  31. void __iomem *base;
  32. u32 spi_base;
  33. };
  34. static void exiu_irq_eoi(struct irq_data *d)
  35. {
  36. struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
  37. writel(BIT(d->hwirq), data->base + EIREQCLR);
  38. irq_chip_eoi_parent(d);
  39. }
  40. static void exiu_irq_mask(struct irq_data *d)
  41. {
  42. struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
  43. u32 val;
  44. val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq);
  45. writel_relaxed(val, data->base + EIMASK);
  46. irq_chip_mask_parent(d);
  47. }
  48. static void exiu_irq_unmask(struct irq_data *d)
  49. {
  50. struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
  51. u32 val;
  52. val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
  53. writel_relaxed(val, data->base + EIMASK);
  54. irq_chip_unmask_parent(d);
  55. }
  56. static void exiu_irq_enable(struct irq_data *d)
  57. {
  58. struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
  59. u32 val;
  60. /* clear interrupts that were latched while disabled */
  61. writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
  62. val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
  63. writel_relaxed(val, data->base + EIMASK);
  64. irq_chip_enable_parent(d);
  65. }
  66. static int exiu_irq_set_type(struct irq_data *d, unsigned int type)
  67. {
  68. struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
  69. u32 val;
  70. val = readl_relaxed(data->base + EILVL);
  71. if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
  72. val |= BIT(d->hwirq);
  73. else
  74. val &= ~BIT(d->hwirq);
  75. writel_relaxed(val, data->base + EILVL);
  76. val = readl_relaxed(data->base + EIEDG);
  77. if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
  78. val &= ~BIT(d->hwirq);
  79. else
  80. val |= BIT(d->hwirq);
  81. writel_relaxed(val, data->base + EIEDG);
  82. writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
  83. return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
  84. }
  85. static struct irq_chip exiu_irq_chip = {
  86. .name = "EXIU",
  87. .irq_eoi = exiu_irq_eoi,
  88. .irq_enable = exiu_irq_enable,
  89. .irq_mask = exiu_irq_mask,
  90. .irq_unmask = exiu_irq_unmask,
  91. .irq_set_type = exiu_irq_set_type,
  92. .irq_set_affinity = irq_chip_set_affinity_parent,
  93. .flags = IRQCHIP_SET_TYPE_MASKED |
  94. IRQCHIP_SKIP_SET_WAKE |
  95. IRQCHIP_EOI_THREADED |
  96. IRQCHIP_MASK_ON_SUSPEND,
  97. };
  98. static int exiu_domain_translate(struct irq_domain *domain,
  99. struct irq_fwspec *fwspec,
  100. unsigned long *hwirq,
  101. unsigned int *type)
  102. {
  103. struct exiu_irq_data *info = domain->host_data;
  104. if (is_of_node(fwspec->fwnode)) {
  105. if (fwspec->param_count != 3)
  106. return -EINVAL;
  107. if (fwspec->param[0] != GIC_SPI)
  108. return -EINVAL; /* No PPI should point to this domain */
  109. *hwirq = fwspec->param[1] - info->spi_base;
  110. *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
  111. } else {
  112. if (fwspec->param_count != 2)
  113. return -EINVAL;
  114. *hwirq = fwspec->param[0];
  115. *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
  116. }
  117. return 0;
  118. }
  119. static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq,
  120. unsigned int nr_irqs, void *data)
  121. {
  122. struct irq_fwspec *fwspec = data;
  123. struct irq_fwspec parent_fwspec;
  124. struct exiu_irq_data *info = dom->host_data;
  125. irq_hw_number_t hwirq;
  126. parent_fwspec = *fwspec;
  127. if (is_of_node(dom->parent->fwnode)) {
  128. if (fwspec->param_count != 3)
  129. return -EINVAL; /* Not GIC compliant */
  130. if (fwspec->param[0] != GIC_SPI)
  131. return -EINVAL; /* No PPI should point to this domain */
  132. hwirq = fwspec->param[1] - info->spi_base;
  133. } else {
  134. hwirq = fwspec->param[0];
  135. parent_fwspec.param[0] = hwirq + info->spi_base + 32;
  136. }
  137. WARN_ON(nr_irqs != 1);
  138. irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info);
  139. parent_fwspec.fwnode = dom->parent->fwnode;
  140. return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec);
  141. }
  142. static const struct irq_domain_ops exiu_domain_ops = {
  143. .translate = exiu_domain_translate,
  144. .alloc = exiu_domain_alloc,
  145. .free = irq_domain_free_irqs_common,
  146. };
  147. static struct exiu_irq_data *exiu_init(const struct fwnode_handle *fwnode,
  148. struct resource *res)
  149. {
  150. struct exiu_irq_data *data;
  151. int err;
  152. data = kzalloc(sizeof(*data), GFP_KERNEL);
  153. if (!data)
  154. return ERR_PTR(-ENOMEM);
  155. if (fwnode_property_read_u32_array(fwnode, "socionext,spi-base",
  156. &data->spi_base, 1)) {
  157. err = -ENODEV;
  158. goto out_free;
  159. }
  160. data->base = ioremap(res->start, resource_size(res));
  161. if (!data->base) {
  162. err = -ENODEV;
  163. goto out_free;
  164. }
  165. /* clear and mask all interrupts */
  166. writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR);
  167. writel_relaxed(0xFFFFFFFF, data->base + EIMASK);
  168. return data;
  169. out_free:
  170. kfree(data);
  171. return ERR_PTR(err);
  172. }
  173. static int __init exiu_dt_init(struct device_node *node,
  174. struct device_node *parent)
  175. {
  176. struct irq_domain *parent_domain, *domain;
  177. struct exiu_irq_data *data;
  178. struct resource res;
  179. if (!parent) {
  180. pr_err("%pOF: no parent, giving up\n", node);
  181. return -ENODEV;
  182. }
  183. parent_domain = irq_find_host(parent);
  184. if (!parent_domain) {
  185. pr_err("%pOF: unable to obtain parent domain\n", node);
  186. return -ENXIO;
  187. }
  188. if (of_address_to_resource(node, 0, &res)) {
  189. pr_err("%pOF: failed to parse memory resource\n", node);
  190. return -ENXIO;
  191. }
  192. data = exiu_init(of_node_to_fwnode(node), &res);
  193. if (IS_ERR(data))
  194. return PTR_ERR(data);
  195. domain = irq_domain_add_hierarchy(parent_domain, 0, NUM_IRQS, node,
  196. &exiu_domain_ops, data);
  197. if (!domain) {
  198. pr_err("%pOF: failed to allocate domain\n", node);
  199. goto out_unmap;
  200. }
  201. pr_info("%pOF: %d interrupts forwarded to %pOF\n", node, NUM_IRQS,
  202. parent);
  203. return 0;
  204. out_unmap:
  205. iounmap(data->base);
  206. kfree(data);
  207. return -ENOMEM;
  208. }
  209. IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_dt_init);
  210. #ifdef CONFIG_ACPI
  211. static int exiu_acpi_probe(struct platform_device *pdev)
  212. {
  213. struct irq_domain *domain;
  214. struct exiu_irq_data *data;
  215. struct resource *res;
  216. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  217. if (!res) {
  218. dev_err(&pdev->dev, "failed to parse memory resource\n");
  219. return -ENXIO;
  220. }
  221. data = exiu_init(dev_fwnode(&pdev->dev), res);
  222. if (IS_ERR(data))
  223. return PTR_ERR(data);
  224. domain = acpi_irq_create_hierarchy(0, NUM_IRQS, dev_fwnode(&pdev->dev),
  225. &exiu_domain_ops, data);
  226. if (!domain) {
  227. dev_err(&pdev->dev, "failed to create IRQ domain\n");
  228. goto out_unmap;
  229. }
  230. dev_info(&pdev->dev, "%d interrupts forwarded\n", NUM_IRQS);
  231. return 0;
  232. out_unmap:
  233. iounmap(data->base);
  234. kfree(data);
  235. return -ENOMEM;
  236. }
  237. static const struct acpi_device_id exiu_acpi_ids[] = {
  238. { "SCX0008" },
  239. { /* sentinel */ }
  240. };
  241. MODULE_DEVICE_TABLE(acpi, exiu_acpi_ids);
  242. static struct platform_driver exiu_driver = {
  243. .driver = {
  244. .name = "exiu",
  245. .acpi_match_table = exiu_acpi_ids,
  246. },
  247. .probe = exiu_acpi_probe,
  248. };
  249. builtin_platform_driver(exiu_driver);
  250. #endif