irq-riscv-intc.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2012 Regents of the University of California
  4. * Copyright (C) 2017-2018 SiFive
  5. * Copyright (C) 2020 Western Digital Corporation or its affiliates.
  6. */
  7. #define pr_fmt(fmt) "riscv-intc: " fmt
  8. #include <linux/atomic.h>
  9. #include <linux/bits.h>
  10. #include <linux/cpu.h>
  11. #include <linux/irq.h>
  12. #include <linux/irqchip.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/smp.h>
  18. static struct irq_domain *intc_domain;
  19. static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
  20. {
  21. unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
  22. unsigned long epc = instruction_pointer(regs);
  23. u32 insn;
  24. #define MATCH_LR_W 0x1000202f
  25. #define MASK_LR_W 0xf9f0707f
  26. #define MATCH_DCACHE_CVAL1 0x0240000b
  27. #define MASK_DCACHE_CVAL1 0xfff07fff
  28. if ((epc & 0x7f) != 4)
  29. goto out;
  30. if (__get_user(insn, (u32 *)epc))
  31. goto out;
  32. if ((insn & MASK_LR_W) != MATCH_LR_W)
  33. goto out;
  34. if (__get_user(insn, (u32 *)(epc - 4)))
  35. goto out;
  36. if ((insn & MASK_DCACHE_CVAL1) != MATCH_DCACHE_CVAL1)
  37. goto out;
  38. instruction_pointer_set(regs, epc - 4);
  39. out:
  40. if (unlikely(cause >= BITS_PER_LONG))
  41. panic("unexpected interrupt cause");
  42. switch (cause) {
  43. #ifdef CONFIG_SMP
  44. case RV_IRQ_SOFT:
  45. /*
  46. * We only use software interrupts to pass IPIs, so if a
  47. * non-SMP system gets one, then we don't know what to do.
  48. */
  49. handle_IPI(regs);
  50. break;
  51. #endif
  52. default:
  53. handle_domain_irq(intc_domain, cause, regs);
  54. break;
  55. }
  56. }
  57. /*
  58. * On RISC-V systems local interrupts are masked or unmasked by writing
  59. * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written
  60. * on the local hart, these functions can only be called on the hart that
  61. * corresponds to the IRQ chip.
  62. */
  63. static void riscv_intc_irq_mask(struct irq_data *d)
  64. {
  65. csr_clear(CSR_IE, BIT(d->hwirq));
  66. }
  67. static void riscv_intc_irq_unmask(struct irq_data *d)
  68. {
  69. csr_set(CSR_IE, BIT(d->hwirq));
  70. }
  71. static int riscv_intc_cpu_starting(unsigned int cpu)
  72. {
  73. csr_set(CSR_IE, BIT(RV_IRQ_SOFT));
  74. return 0;
  75. }
  76. static int riscv_intc_cpu_dying(unsigned int cpu)
  77. {
  78. csr_clear(CSR_IE, BIT(RV_IRQ_SOFT));
  79. return 0;
  80. }
  81. static struct irq_chip riscv_intc_chip = {
  82. .name = "RISC-V INTC",
  83. .irq_mask = riscv_intc_irq_mask,
  84. .irq_unmask = riscv_intc_irq_unmask,
  85. };
  86. static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
  87. irq_hw_number_t hwirq)
  88. {
  89. irq_set_percpu_devid(irq);
  90. irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
  91. handle_percpu_devid_irq, NULL, NULL);
  92. return 0;
  93. }
  94. static const struct irq_domain_ops riscv_intc_domain_ops = {
  95. .map = riscv_intc_domain_map,
  96. .xlate = irq_domain_xlate_onecell,
  97. };
  98. static int __init riscv_intc_init(struct device_node *node,
  99. struct device_node *parent)
  100. {
  101. int rc, hartid;
  102. hartid = riscv_of_parent_hartid(node);
  103. if (hartid < 0) {
  104. pr_warn("unable to find hart id for %pOF\n", node);
  105. return 0;
  106. }
  107. /*
  108. * The DT will have one INTC DT node under each CPU (or HART)
  109. * DT node so riscv_intc_init() function will be called once
  110. * for each INTC DT node. We only need to do INTC initialization
  111. * for the INTC DT node belonging to boot CPU (or boot HART).
  112. */
  113. if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
  114. return 0;
  115. intc_domain = irq_domain_add_linear(node, BITS_PER_LONG,
  116. &riscv_intc_domain_ops, NULL);
  117. if (!intc_domain) {
  118. pr_err("unable to add IRQ domain\n");
  119. return -ENXIO;
  120. }
  121. rc = set_handle_irq(&riscv_intc_irq);
  122. if (rc) {
  123. pr_err("failed to set irq handler\n");
  124. return rc;
  125. }
  126. cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING,
  127. "irqchip/riscv/intc:starting",
  128. riscv_intc_cpu_starting,
  129. riscv_intc_cpu_dying);
  130. pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
  131. return 0;
  132. }
  133. IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);