irq-renesas-rza1.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas RZ/A1 IRQC Driver
  4. *
  5. * Copyright (C) 2019 Glider bvba
  6. */
  7. #include <linux/err.h>
  8. #include <linux/init.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/io.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/irq.h>
  13. #include <linux/module.h>
  14. #include <linux/of_irq.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <dt-bindings/interrupt-controller/arm-gic.h>
  18. #define IRQC_NUM_IRQ 8
  19. #define ICR0 0 /* Interrupt Control Register 0 */
  20. #define ICR0_NMIL BIT(15) /* NMI Input Level (0=low, 1=high) */
  21. #define ICR0_NMIE BIT(8) /* Edge Select (0=falling, 1=rising) */
  22. #define ICR0_NMIF BIT(1) /* NMI Interrupt Request */
  23. #define ICR1 2 /* Interrupt Control Register 1 */
  24. #define ICR1_IRQS(n, sense) ((sense) << ((n) * 2)) /* IRQ Sense Select */
  25. #define ICR1_IRQS_LEVEL_LOW 0
  26. #define ICR1_IRQS_EDGE_FALLING 1
  27. #define ICR1_IRQS_EDGE_RISING 2
  28. #define ICR1_IRQS_EDGE_BOTH 3
  29. #define ICR1_IRQS_MASK(n) ICR1_IRQS((n), 3)
  30. #define IRQRR 4 /* IRQ Interrupt Request Register */
  31. struct rza1_irqc_priv {
  32. struct device *dev;
  33. void __iomem *base;
  34. struct irq_chip chip;
  35. struct irq_domain *irq_domain;
  36. struct of_phandle_args map[IRQC_NUM_IRQ];
  37. };
  38. static struct rza1_irqc_priv *irq_data_to_priv(struct irq_data *data)
  39. {
  40. return data->domain->host_data;
  41. }
  42. static void rza1_irqc_eoi(struct irq_data *d)
  43. {
  44. struct rza1_irqc_priv *priv = irq_data_to_priv(d);
  45. u16 bit = BIT(irqd_to_hwirq(d));
  46. u16 tmp;
  47. tmp = readw_relaxed(priv->base + IRQRR);
  48. if (tmp & bit)
  49. writew_relaxed(GENMASK(IRQC_NUM_IRQ - 1, 0) & ~bit,
  50. priv->base + IRQRR);
  51. irq_chip_eoi_parent(d);
  52. }
  53. static int rza1_irqc_set_type(struct irq_data *d, unsigned int type)
  54. {
  55. struct rza1_irqc_priv *priv = irq_data_to_priv(d);
  56. unsigned int hw_irq = irqd_to_hwirq(d);
  57. u16 sense, tmp;
  58. switch (type & IRQ_TYPE_SENSE_MASK) {
  59. case IRQ_TYPE_LEVEL_LOW:
  60. sense = ICR1_IRQS_LEVEL_LOW;
  61. break;
  62. case IRQ_TYPE_EDGE_FALLING:
  63. sense = ICR1_IRQS_EDGE_FALLING;
  64. break;
  65. case IRQ_TYPE_EDGE_RISING:
  66. sense = ICR1_IRQS_EDGE_RISING;
  67. break;
  68. case IRQ_TYPE_EDGE_BOTH:
  69. sense = ICR1_IRQS_EDGE_BOTH;
  70. break;
  71. default:
  72. return -EINVAL;
  73. }
  74. tmp = readw_relaxed(priv->base + ICR1);
  75. tmp &= ~ICR1_IRQS_MASK(hw_irq);
  76. tmp |= ICR1_IRQS(hw_irq, sense);
  77. writew_relaxed(tmp, priv->base + ICR1);
  78. return 0;
  79. }
  80. static int rza1_irqc_alloc(struct irq_domain *domain, unsigned int virq,
  81. unsigned int nr_irqs, void *arg)
  82. {
  83. struct rza1_irqc_priv *priv = domain->host_data;
  84. struct irq_fwspec *fwspec = arg;
  85. unsigned int hwirq = fwspec->param[0];
  86. struct irq_fwspec spec;
  87. unsigned int i;
  88. int ret;
  89. ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &priv->chip,
  90. priv);
  91. if (ret)
  92. return ret;
  93. spec.fwnode = &priv->dev->of_node->fwnode;
  94. spec.param_count = priv->map[hwirq].args_count;
  95. for (i = 0; i < spec.param_count; i++)
  96. spec.param[i] = priv->map[hwirq].args[i];
  97. return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &spec);
  98. }
  99. static int rza1_irqc_translate(struct irq_domain *domain,
  100. struct irq_fwspec *fwspec, unsigned long *hwirq,
  101. unsigned int *type)
  102. {
  103. if (fwspec->param_count != 2 || fwspec->param[0] >= IRQC_NUM_IRQ)
  104. return -EINVAL;
  105. *hwirq = fwspec->param[0];
  106. *type = fwspec->param[1];
  107. return 0;
  108. }
  109. static const struct irq_domain_ops rza1_irqc_domain_ops = {
  110. .alloc = rza1_irqc_alloc,
  111. .translate = rza1_irqc_translate,
  112. };
  113. static int rza1_irqc_parse_map(struct rza1_irqc_priv *priv,
  114. struct device_node *gic_node)
  115. {
  116. unsigned int imaplen, i, j, ret;
  117. struct device *dev = priv->dev;
  118. struct device_node *ipar;
  119. const __be32 *imap;
  120. u32 intsize;
  121. imap = of_get_property(dev->of_node, "interrupt-map", &imaplen);
  122. if (!imap)
  123. return -EINVAL;
  124. for (i = 0; i < IRQC_NUM_IRQ; i++) {
  125. if (imaplen < 3)
  126. return -EINVAL;
  127. /* Check interrupt number, ignore sense */
  128. if (be32_to_cpup(imap) != i)
  129. return -EINVAL;
  130. ipar = of_find_node_by_phandle(be32_to_cpup(imap + 2));
  131. if (ipar != gic_node) {
  132. of_node_put(ipar);
  133. return -EINVAL;
  134. }
  135. imap += 3;
  136. imaplen -= 3;
  137. ret = of_property_read_u32(ipar, "#interrupt-cells", &intsize);
  138. of_node_put(ipar);
  139. if (ret)
  140. return ret;
  141. if (imaplen < intsize)
  142. return -EINVAL;
  143. priv->map[i].args_count = intsize;
  144. for (j = 0; j < intsize; j++)
  145. priv->map[i].args[j] = be32_to_cpup(imap++);
  146. imaplen -= intsize;
  147. }
  148. return 0;
  149. }
  150. static int rza1_irqc_probe(struct platform_device *pdev)
  151. {
  152. struct device *dev = &pdev->dev;
  153. struct device_node *np = dev->of_node;
  154. struct irq_domain *parent = NULL;
  155. struct device_node *gic_node;
  156. struct rza1_irqc_priv *priv;
  157. int ret;
  158. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  159. if (!priv)
  160. return -ENOMEM;
  161. platform_set_drvdata(pdev, priv);
  162. priv->dev = dev;
  163. priv->base = devm_platform_ioremap_resource(pdev, 0);
  164. if (IS_ERR(priv->base))
  165. return PTR_ERR(priv->base);
  166. gic_node = of_irq_find_parent(np);
  167. if (gic_node)
  168. parent = irq_find_host(gic_node);
  169. if (!parent) {
  170. dev_err(dev, "cannot find parent domain\n");
  171. ret = -ENODEV;
  172. goto out_put_node;
  173. }
  174. ret = rza1_irqc_parse_map(priv, gic_node);
  175. if (ret) {
  176. dev_err(dev, "cannot parse %s: %d\n", "interrupt-map", ret);
  177. goto out_put_node;
  178. }
  179. priv->chip.name = "rza1-irqc",
  180. priv->chip.irq_mask = irq_chip_mask_parent,
  181. priv->chip.irq_unmask = irq_chip_unmask_parent,
  182. priv->chip.irq_eoi = rza1_irqc_eoi,
  183. priv->chip.irq_retrigger = irq_chip_retrigger_hierarchy,
  184. priv->chip.irq_set_type = rza1_irqc_set_type,
  185. priv->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
  186. priv->irq_domain = irq_domain_add_hierarchy(parent, 0, IRQC_NUM_IRQ,
  187. np, &rza1_irqc_domain_ops,
  188. priv);
  189. if (!priv->irq_domain) {
  190. dev_err(dev, "cannot initialize irq domain\n");
  191. ret = -ENOMEM;
  192. }
  193. out_put_node:
  194. of_node_put(gic_node);
  195. return ret;
  196. }
  197. static int rza1_irqc_remove(struct platform_device *pdev)
  198. {
  199. struct rza1_irqc_priv *priv = platform_get_drvdata(pdev);
  200. irq_domain_remove(priv->irq_domain);
  201. return 0;
  202. }
  203. static const struct of_device_id rza1_irqc_dt_ids[] = {
  204. { .compatible = "renesas,rza1-irqc" },
  205. {},
  206. };
  207. MODULE_DEVICE_TABLE(of, rza1_irqc_dt_ids);
  208. static struct platform_driver rza1_irqc_device_driver = {
  209. .probe = rza1_irqc_probe,
  210. .remove = rza1_irqc_remove,
  211. .driver = {
  212. .name = "renesas_rza1_irqc",
  213. .of_match_table = rza1_irqc_dt_ids,
  214. }
  215. };
  216. static int __init rza1_irqc_init(void)
  217. {
  218. return platform_driver_register(&rza1_irqc_device_driver);
  219. }
  220. postcore_initcall(rza1_irqc_init);
  221. static void __exit rza1_irqc_exit(void)
  222. {
  223. platform_driver_unregister(&rza1_irqc_device_driver);
  224. }
  225. module_exit(rza1_irqc_exit);
  226. MODULE_AUTHOR("Geert Uytterhoeven <geert+renesas@glider.be>");
  227. MODULE_DESCRIPTION("Renesas RZ/A1 IRQC Driver");
  228. MODULE_LICENSE("GPL v2");