irq-renesas-irqc.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas IRQC Driver
  4. *
  5. * Copyright (C) 2013 Magnus Damm
  6. */
  7. #include <linux/init.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/ioport.h>
  11. #include <linux/io.h>
  12. #include <linux/irq.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/err.h>
  15. #include <linux/slab.h>
  16. #include <linux/module.h>
  17. #include <linux/pm_runtime.h>
  18. #define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
  19. #define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */
  20. #define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */
  21. #define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */
  22. #define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
  23. /* SYS-CPU vs. RT-CPU */
  24. #define DETECT_STATUS 0x100 /* IRQn Detect Status Register */
  25. #define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
  26. #define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
  27. #define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
  28. #define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */
  29. #define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */
  30. #define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */
  31. #define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */
  32. #define CHTEN_STS 0x120 /* Chattering Reduction Status Register */
  33. #define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
  34. /* IRQn Configuration Register */
  35. struct irqc_irq {
  36. int hw_irq;
  37. int requested_irq;
  38. struct irqc_priv *p;
  39. };
  40. struct irqc_priv {
  41. void __iomem *iomem;
  42. void __iomem *cpu_int_base;
  43. struct irqc_irq irq[IRQC_IRQ_MAX];
  44. unsigned int number_of_irqs;
  45. struct device *dev;
  46. struct irq_chip_generic *gc;
  47. struct irq_domain *irq_domain;
  48. atomic_t wakeup_path;
  49. };
  50. static struct irqc_priv *irq_data_to_priv(struct irq_data *data)
  51. {
  52. return data->domain->host_data;
  53. }
  54. static void irqc_dbg(struct irqc_irq *i, char *str)
  55. {
  56. dev_dbg(i->p->dev, "%s (%d:%d)\n", str, i->requested_irq, i->hw_irq);
  57. }
  58. static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
  59. [IRQ_TYPE_LEVEL_LOW] = 0x01,
  60. [IRQ_TYPE_LEVEL_HIGH] = 0x02,
  61. [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
  62. [IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */
  63. [IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */
  64. };
  65. static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
  66. {
  67. struct irqc_priv *p = irq_data_to_priv(d);
  68. int hw_irq = irqd_to_hwirq(d);
  69. unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
  70. u32 tmp;
  71. irqc_dbg(&p->irq[hw_irq], "sense");
  72. if (!value)
  73. return -EINVAL;
  74. tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
  75. tmp &= ~0x3f;
  76. tmp |= value;
  77. iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
  78. return 0;
  79. }
  80. static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
  81. {
  82. struct irqc_priv *p = irq_data_to_priv(d);
  83. int hw_irq = irqd_to_hwirq(d);
  84. irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
  85. if (on)
  86. atomic_inc(&p->wakeup_path);
  87. else
  88. atomic_dec(&p->wakeup_path);
  89. return 0;
  90. }
  91. static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
  92. {
  93. struct irqc_irq *i = dev_id;
  94. struct irqc_priv *p = i->p;
  95. u32 bit = BIT(i->hw_irq);
  96. irqc_dbg(i, "demux1");
  97. if (ioread32(p->iomem + DETECT_STATUS) & bit) {
  98. iowrite32(bit, p->iomem + DETECT_STATUS);
  99. irqc_dbg(i, "demux2");
  100. generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq));
  101. return IRQ_HANDLED;
  102. }
  103. return IRQ_NONE;
  104. }
  105. static int irqc_probe(struct platform_device *pdev)
  106. {
  107. struct device *dev = &pdev->dev;
  108. const char *name = dev_name(dev);
  109. struct irqc_priv *p;
  110. struct resource *irq;
  111. int ret;
  112. int k;
  113. p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
  114. if (!p)
  115. return -ENOMEM;
  116. p->dev = dev;
  117. platform_set_drvdata(pdev, p);
  118. pm_runtime_enable(dev);
  119. pm_runtime_get_sync(dev);
  120. /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
  121. for (k = 0; k < IRQC_IRQ_MAX; k++) {
  122. irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
  123. if (!irq)
  124. break;
  125. p->irq[k].p = p;
  126. p->irq[k].hw_irq = k;
  127. p->irq[k].requested_irq = irq->start;
  128. }
  129. p->number_of_irqs = k;
  130. if (p->number_of_irqs < 1) {
  131. dev_err(dev, "not enough IRQ resources\n");
  132. ret = -EINVAL;
  133. goto err_runtime_pm_disable;
  134. }
  135. /* ioremap IOMEM and setup read/write callbacks */
  136. p->iomem = devm_platform_ioremap_resource(pdev, 0);
  137. if (IS_ERR(p->iomem)) {
  138. ret = PTR_ERR(p->iomem);
  139. goto err_runtime_pm_disable;
  140. }
  141. p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
  142. p->irq_domain = irq_domain_add_linear(dev->of_node, p->number_of_irqs,
  143. &irq_generic_chip_ops, p);
  144. if (!p->irq_domain) {
  145. ret = -ENXIO;
  146. dev_err(dev, "cannot initialize irq domain\n");
  147. goto err_runtime_pm_disable;
  148. }
  149. ret = irq_alloc_domain_generic_chips(p->irq_domain, p->number_of_irqs,
  150. 1, "irqc", handle_level_irq,
  151. 0, 0, IRQ_GC_INIT_NESTED_LOCK);
  152. if (ret) {
  153. dev_err(dev, "cannot allocate generic chip\n");
  154. goto err_remove_domain;
  155. }
  156. p->gc = irq_get_domain_generic_chip(p->irq_domain, 0);
  157. p->gc->reg_base = p->cpu_int_base;
  158. p->gc->chip_types[0].regs.enable = IRQC_EN_SET;
  159. p->gc->chip_types[0].regs.disable = IRQC_EN_STS;
  160. p->gc->chip_types[0].chip.parent_device = dev;
  161. p->gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
  162. p->gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
  163. p->gc->chip_types[0].chip.irq_set_type = irqc_irq_set_type;
  164. p->gc->chip_types[0].chip.irq_set_wake = irqc_irq_set_wake;
  165. p->gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
  166. /* request interrupts one by one */
  167. for (k = 0; k < p->number_of_irqs; k++) {
  168. if (devm_request_irq(dev, p->irq[k].requested_irq,
  169. irqc_irq_handler, 0, name, &p->irq[k])) {
  170. dev_err(dev, "failed to request IRQ\n");
  171. ret = -ENOENT;
  172. goto err_remove_domain;
  173. }
  174. }
  175. dev_info(dev, "driving %d irqs\n", p->number_of_irqs);
  176. return 0;
  177. err_remove_domain:
  178. irq_domain_remove(p->irq_domain);
  179. err_runtime_pm_disable:
  180. pm_runtime_put(dev);
  181. pm_runtime_disable(dev);
  182. return ret;
  183. }
  184. static int irqc_remove(struct platform_device *pdev)
  185. {
  186. struct irqc_priv *p = platform_get_drvdata(pdev);
  187. irq_domain_remove(p->irq_domain);
  188. pm_runtime_put(&pdev->dev);
  189. pm_runtime_disable(&pdev->dev);
  190. return 0;
  191. }
  192. static int __maybe_unused irqc_suspend(struct device *dev)
  193. {
  194. struct irqc_priv *p = dev_get_drvdata(dev);
  195. if (atomic_read(&p->wakeup_path))
  196. device_set_wakeup_path(dev);
  197. return 0;
  198. }
  199. static SIMPLE_DEV_PM_OPS(irqc_pm_ops, irqc_suspend, NULL);
  200. static const struct of_device_id irqc_dt_ids[] = {
  201. { .compatible = "renesas,irqc", },
  202. {},
  203. };
  204. MODULE_DEVICE_TABLE(of, irqc_dt_ids);
  205. static struct platform_driver irqc_device_driver = {
  206. .probe = irqc_probe,
  207. .remove = irqc_remove,
  208. .driver = {
  209. .name = "renesas_irqc",
  210. .of_match_table = irqc_dt_ids,
  211. .pm = &irqc_pm_ops,
  212. }
  213. };
  214. static int __init irqc_init(void)
  215. {
  216. return platform_driver_register(&irqc_device_driver);
  217. }
  218. postcore_initcall(irqc_init);
  219. static void __exit irqc_exit(void)
  220. {
  221. platform_driver_unregister(&irqc_device_driver);
  222. }
  223. module_exit(irqc_exit);
  224. MODULE_AUTHOR("Magnus Damm");
  225. MODULE_DESCRIPTION("Renesas IRQC Driver");
  226. MODULE_LICENSE("GPL v2");