irq-renesas-intc-irqpin.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas INTC External IRQ Pin Driver
  4. *
  5. * Copyright (C) 2013 Magnus Damm
  6. */
  7. #include <linux/init.h>
  8. #include <linux/of.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/spinlock.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/ioport.h>
  13. #include <linux/io.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/err.h>
  17. #include <linux/slab.h>
  18. #include <linux/module.h>
  19. #include <linux/of_device.h>
  20. #include <linux/pm_runtime.h>
  21. #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
  22. #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
  23. #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
  24. #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
  25. #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
  26. #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
  27. #define INTC_IRQPIN_REG_NR_MANDATORY 5
  28. #define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
  29. #define INTC_IRQPIN_REG_NR 6
  30. /* INTC external IRQ PIN hardware register access:
  31. *
  32. * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
  33. * PRIO is read-write 32-bit with 4-bits per IRQ (**)
  34. * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
  35. * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
  36. * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
  37. *
  38. * (*) May be accessed by more than one driver instance - lock needed
  39. * (**) Read-modify-write access by one driver instance - lock needed
  40. * (***) Accessed by one driver instance only - no locking needed
  41. */
  42. struct intc_irqpin_iomem {
  43. void __iomem *iomem;
  44. unsigned long (*read)(void __iomem *iomem);
  45. void (*write)(void __iomem *iomem, unsigned long data);
  46. int width;
  47. };
  48. struct intc_irqpin_irq {
  49. int hw_irq;
  50. int requested_irq;
  51. int domain_irq;
  52. struct intc_irqpin_priv *p;
  53. };
  54. struct intc_irqpin_priv {
  55. struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
  56. struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
  57. unsigned int sense_bitfield_width;
  58. struct platform_device *pdev;
  59. struct irq_chip irq_chip;
  60. struct irq_domain *irq_domain;
  61. atomic_t wakeup_path;
  62. unsigned shared_irqs:1;
  63. u8 shared_irq_mask;
  64. };
  65. struct intc_irqpin_config {
  66. int irlm_bit; /* -1 if non-existent */
  67. };
  68. static unsigned long intc_irqpin_read32(void __iomem *iomem)
  69. {
  70. return ioread32(iomem);
  71. }
  72. static unsigned long intc_irqpin_read8(void __iomem *iomem)
  73. {
  74. return ioread8(iomem);
  75. }
  76. static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
  77. {
  78. iowrite32(data, iomem);
  79. }
  80. static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
  81. {
  82. iowrite8(data, iomem);
  83. }
  84. static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
  85. int reg)
  86. {
  87. struct intc_irqpin_iomem *i = &p->iomem[reg];
  88. return i->read(i->iomem);
  89. }
  90. static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
  91. int reg, unsigned long data)
  92. {
  93. struct intc_irqpin_iomem *i = &p->iomem[reg];
  94. i->write(i->iomem, data);
  95. }
  96. static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
  97. int reg, int hw_irq)
  98. {
  99. return BIT((p->iomem[reg].width - 1) - hw_irq);
  100. }
  101. static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
  102. int reg, int hw_irq)
  103. {
  104. intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
  105. }
  106. static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
  107. static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
  108. int reg, int shift,
  109. int width, int value)
  110. {
  111. unsigned long flags;
  112. unsigned long tmp;
  113. raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
  114. tmp = intc_irqpin_read(p, reg);
  115. tmp &= ~(((1 << width) - 1) << shift);
  116. tmp |= value << shift;
  117. intc_irqpin_write(p, reg, tmp);
  118. raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
  119. }
  120. static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
  121. int irq, int do_mask)
  122. {
  123. /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
  124. int bitfield_width = 4;
  125. int shift = 32 - (irq + 1) * bitfield_width;
  126. intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
  127. shift, bitfield_width,
  128. do_mask ? 0 : (1 << bitfield_width) - 1);
  129. }
  130. static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
  131. {
  132. /* The SENSE register is assumed to be 32-bit. */
  133. int bitfield_width = p->sense_bitfield_width;
  134. int shift = 32 - (irq + 1) * bitfield_width;
  135. dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
  136. if (value >= (1 << bitfield_width))
  137. return -EINVAL;
  138. intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
  139. bitfield_width, value);
  140. return 0;
  141. }
  142. static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
  143. {
  144. dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
  145. str, i->requested_irq, i->hw_irq, i->domain_irq);
  146. }
  147. static void intc_irqpin_irq_enable(struct irq_data *d)
  148. {
  149. struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
  150. int hw_irq = irqd_to_hwirq(d);
  151. intc_irqpin_dbg(&p->irq[hw_irq], "enable");
  152. intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
  153. }
  154. static void intc_irqpin_irq_disable(struct irq_data *d)
  155. {
  156. struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
  157. int hw_irq = irqd_to_hwirq(d);
  158. intc_irqpin_dbg(&p->irq[hw_irq], "disable");
  159. intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
  160. }
  161. static void intc_irqpin_shared_irq_enable(struct irq_data *d)
  162. {
  163. struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
  164. int hw_irq = irqd_to_hwirq(d);
  165. intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
  166. intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
  167. p->shared_irq_mask &= ~BIT(hw_irq);
  168. }
  169. static void intc_irqpin_shared_irq_disable(struct irq_data *d)
  170. {
  171. struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
  172. int hw_irq = irqd_to_hwirq(d);
  173. intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
  174. intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
  175. p->shared_irq_mask |= BIT(hw_irq);
  176. }
  177. static void intc_irqpin_irq_enable_force(struct irq_data *d)
  178. {
  179. struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
  180. int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
  181. intc_irqpin_irq_enable(d);
  182. /* enable interrupt through parent interrupt controller,
  183. * assumes non-shared interrupt with 1:1 mapping
  184. * needed for busted IRQs on some SoCs like sh73a0
  185. */
  186. irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
  187. }
  188. static void intc_irqpin_irq_disable_force(struct irq_data *d)
  189. {
  190. struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
  191. int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
  192. /* disable interrupt through parent interrupt controller,
  193. * assumes non-shared interrupt with 1:1 mapping
  194. * needed for busted IRQs on some SoCs like sh73a0
  195. */
  196. irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
  197. intc_irqpin_irq_disable(d);
  198. }
  199. #define INTC_IRQ_SENSE_VALID 0x10
  200. #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
  201. static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
  202. [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
  203. [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
  204. [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
  205. [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
  206. [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
  207. };
  208. static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
  209. {
  210. unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
  211. struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
  212. if (!(value & INTC_IRQ_SENSE_VALID))
  213. return -EINVAL;
  214. return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
  215. value ^ INTC_IRQ_SENSE_VALID);
  216. }
  217. static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
  218. {
  219. struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
  220. int hw_irq = irqd_to_hwirq(d);
  221. irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
  222. if (on)
  223. atomic_inc(&p->wakeup_path);
  224. else
  225. atomic_dec(&p->wakeup_path);
  226. return 0;
  227. }
  228. static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
  229. {
  230. struct intc_irqpin_irq *i = dev_id;
  231. struct intc_irqpin_priv *p = i->p;
  232. unsigned long bit;
  233. intc_irqpin_dbg(i, "demux1");
  234. bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
  235. if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
  236. intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
  237. intc_irqpin_dbg(i, "demux2");
  238. generic_handle_irq(i->domain_irq);
  239. return IRQ_HANDLED;
  240. }
  241. return IRQ_NONE;
  242. }
  243. static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
  244. {
  245. struct intc_irqpin_priv *p = dev_id;
  246. unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
  247. irqreturn_t status = IRQ_NONE;
  248. int k;
  249. for (k = 0; k < 8; k++) {
  250. if (reg_source & BIT(7 - k)) {
  251. if (BIT(k) & p->shared_irq_mask)
  252. continue;
  253. status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
  254. }
  255. }
  256. return status;
  257. }
  258. /*
  259. * This lock class tells lockdep that INTC External IRQ Pin irqs are in a
  260. * different category than their parents, so it won't report false recursion.
  261. */
  262. static struct lock_class_key intc_irqpin_irq_lock_class;
  263. /* And this is for the request mutex */
  264. static struct lock_class_key intc_irqpin_irq_request_class;
  265. static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
  266. irq_hw_number_t hw)
  267. {
  268. struct intc_irqpin_priv *p = h->host_data;
  269. p->irq[hw].domain_irq = virq;
  270. p->irq[hw].hw_irq = hw;
  271. intc_irqpin_dbg(&p->irq[hw], "map");
  272. irq_set_chip_data(virq, h->host_data);
  273. irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
  274. &intc_irqpin_irq_request_class);
  275. irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
  276. return 0;
  277. }
  278. static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
  279. .map = intc_irqpin_irq_domain_map,
  280. .xlate = irq_domain_xlate_twocell,
  281. };
  282. static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
  283. .irlm_bit = 23, /* ICR0.IRLM0 */
  284. };
  285. static const struct intc_irqpin_config intc_irqpin_rmobile = {
  286. .irlm_bit = -1,
  287. };
  288. static const struct of_device_id intc_irqpin_dt_ids[] = {
  289. { .compatible = "renesas,intc-irqpin", },
  290. { .compatible = "renesas,intc-irqpin-r8a7778",
  291. .data = &intc_irqpin_irlm_r8a777x },
  292. { .compatible = "renesas,intc-irqpin-r8a7779",
  293. .data = &intc_irqpin_irlm_r8a777x },
  294. { .compatible = "renesas,intc-irqpin-r8a7740",
  295. .data = &intc_irqpin_rmobile },
  296. { .compatible = "renesas,intc-irqpin-sh73a0",
  297. .data = &intc_irqpin_rmobile },
  298. {},
  299. };
  300. MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
  301. static int intc_irqpin_probe(struct platform_device *pdev)
  302. {
  303. const struct intc_irqpin_config *config;
  304. struct device *dev = &pdev->dev;
  305. struct intc_irqpin_priv *p;
  306. struct intc_irqpin_iomem *i;
  307. struct resource *io[INTC_IRQPIN_REG_NR];
  308. struct resource *irq;
  309. struct irq_chip *irq_chip;
  310. void (*enable_fn)(struct irq_data *d);
  311. void (*disable_fn)(struct irq_data *d);
  312. const char *name = dev_name(dev);
  313. bool control_parent;
  314. unsigned int nirqs;
  315. int ref_irq;
  316. int ret;
  317. int k;
  318. p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
  319. if (!p)
  320. return -ENOMEM;
  321. /* deal with driver instance configuration */
  322. of_property_read_u32(dev->of_node, "sense-bitfield-width",
  323. &p->sense_bitfield_width);
  324. control_parent = of_property_read_bool(dev->of_node, "control-parent");
  325. if (!p->sense_bitfield_width)
  326. p->sense_bitfield_width = 4; /* default to 4 bits */
  327. p->pdev = pdev;
  328. platform_set_drvdata(pdev, p);
  329. config = of_device_get_match_data(dev);
  330. pm_runtime_enable(dev);
  331. pm_runtime_get_sync(dev);
  332. /* get hold of register banks */
  333. memset(io, 0, sizeof(io));
  334. for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
  335. io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
  336. if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
  337. dev_err(dev, "not enough IOMEM resources\n");
  338. ret = -EINVAL;
  339. goto err0;
  340. }
  341. }
  342. /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
  343. for (k = 0; k < INTC_IRQPIN_MAX; k++) {
  344. irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
  345. if (!irq)
  346. break;
  347. p->irq[k].p = p;
  348. p->irq[k].requested_irq = irq->start;
  349. }
  350. nirqs = k;
  351. if (nirqs < 1) {
  352. dev_err(dev, "not enough IRQ resources\n");
  353. ret = -EINVAL;
  354. goto err0;
  355. }
  356. /* ioremap IOMEM and setup read/write callbacks */
  357. for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
  358. i = &p->iomem[k];
  359. /* handle optional registers */
  360. if (!io[k])
  361. continue;
  362. switch (resource_size(io[k])) {
  363. case 1:
  364. i->width = 8;
  365. i->read = intc_irqpin_read8;
  366. i->write = intc_irqpin_write8;
  367. break;
  368. case 4:
  369. i->width = 32;
  370. i->read = intc_irqpin_read32;
  371. i->write = intc_irqpin_write32;
  372. break;
  373. default:
  374. dev_err(dev, "IOMEM size mismatch\n");
  375. ret = -EINVAL;
  376. goto err0;
  377. }
  378. i->iomem = devm_ioremap(dev, io[k]->start,
  379. resource_size(io[k]));
  380. if (!i->iomem) {
  381. dev_err(dev, "failed to remap IOMEM\n");
  382. ret = -ENXIO;
  383. goto err0;
  384. }
  385. }
  386. /* configure "individual IRQ mode" where needed */
  387. if (config && config->irlm_bit >= 0) {
  388. if (io[INTC_IRQPIN_REG_IRLM])
  389. intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
  390. config->irlm_bit, 1, 1);
  391. else
  392. dev_warn(dev, "unable to select IRLM mode\n");
  393. }
  394. /* mask all interrupts using priority */
  395. for (k = 0; k < nirqs; k++)
  396. intc_irqpin_mask_unmask_prio(p, k, 1);
  397. /* clear all pending interrupts */
  398. intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
  399. /* scan for shared interrupt lines */
  400. ref_irq = p->irq[0].requested_irq;
  401. p->shared_irqs = 1;
  402. for (k = 1; k < nirqs; k++) {
  403. if (ref_irq != p->irq[k].requested_irq) {
  404. p->shared_irqs = 0;
  405. break;
  406. }
  407. }
  408. /* use more severe masking method if requested */
  409. if (control_parent) {
  410. enable_fn = intc_irqpin_irq_enable_force;
  411. disable_fn = intc_irqpin_irq_disable_force;
  412. } else if (!p->shared_irqs) {
  413. enable_fn = intc_irqpin_irq_enable;
  414. disable_fn = intc_irqpin_irq_disable;
  415. } else {
  416. enable_fn = intc_irqpin_shared_irq_enable;
  417. disable_fn = intc_irqpin_shared_irq_disable;
  418. }
  419. irq_chip = &p->irq_chip;
  420. irq_chip->name = "intc-irqpin";
  421. irq_chip->parent_device = dev;
  422. irq_chip->irq_mask = disable_fn;
  423. irq_chip->irq_unmask = enable_fn;
  424. irq_chip->irq_set_type = intc_irqpin_irq_set_type;
  425. irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
  426. irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
  427. p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
  428. &intc_irqpin_irq_domain_ops, p);
  429. if (!p->irq_domain) {
  430. ret = -ENXIO;
  431. dev_err(dev, "cannot initialize irq domain\n");
  432. goto err0;
  433. }
  434. if (p->shared_irqs) {
  435. /* request one shared interrupt */
  436. if (devm_request_irq(dev, p->irq[0].requested_irq,
  437. intc_irqpin_shared_irq_handler,
  438. IRQF_SHARED, name, p)) {
  439. dev_err(dev, "failed to request low IRQ\n");
  440. ret = -ENOENT;
  441. goto err1;
  442. }
  443. } else {
  444. /* request interrupts one by one */
  445. for (k = 0; k < nirqs; k++) {
  446. if (devm_request_irq(dev, p->irq[k].requested_irq,
  447. intc_irqpin_irq_handler, 0, name,
  448. &p->irq[k])) {
  449. dev_err(dev, "failed to request low IRQ\n");
  450. ret = -ENOENT;
  451. goto err1;
  452. }
  453. }
  454. }
  455. /* unmask all interrupts on prio level */
  456. for (k = 0; k < nirqs; k++)
  457. intc_irqpin_mask_unmask_prio(p, k, 0);
  458. dev_info(dev, "driving %d irqs\n", nirqs);
  459. return 0;
  460. err1:
  461. irq_domain_remove(p->irq_domain);
  462. err0:
  463. pm_runtime_put(dev);
  464. pm_runtime_disable(dev);
  465. return ret;
  466. }
  467. static int intc_irqpin_remove(struct platform_device *pdev)
  468. {
  469. struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
  470. irq_domain_remove(p->irq_domain);
  471. pm_runtime_put(&pdev->dev);
  472. pm_runtime_disable(&pdev->dev);
  473. return 0;
  474. }
  475. static int __maybe_unused intc_irqpin_suspend(struct device *dev)
  476. {
  477. struct intc_irqpin_priv *p = dev_get_drvdata(dev);
  478. if (atomic_read(&p->wakeup_path))
  479. device_set_wakeup_path(dev);
  480. return 0;
  481. }
  482. static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
  483. static struct platform_driver intc_irqpin_device_driver = {
  484. .probe = intc_irqpin_probe,
  485. .remove = intc_irqpin_remove,
  486. .driver = {
  487. .name = "renesas_intc_irqpin",
  488. .of_match_table = intc_irqpin_dt_ids,
  489. .pm = &intc_irqpin_pm_ops,
  490. }
  491. };
  492. static int __init intc_irqpin_init(void)
  493. {
  494. return platform_driver_register(&intc_irqpin_device_driver);
  495. }
  496. postcore_initcall(intc_irqpin_init);
  497. static void __exit intc_irqpin_exit(void)
  498. {
  499. platform_driver_unregister(&intc_irqpin_device_driver);
  500. }
  501. module_exit(intc_irqpin_exit);
  502. MODULE_AUTHOR("Magnus Damm");
  503. MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
  504. MODULE_LICENSE("GPL v2");